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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Driver for Microchip S/PDIF TX Controller
0004 //
0005 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
0006 //
0007 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
0008 
0009 #include <linux/clk.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/spinlock.h>
0013 
0014 #include <sound/asoundef.h>
0015 #include <sound/dmaengine_pcm.h>
0016 #include <sound/pcm_params.h>
0017 #include <sound/soc.h>
0018 
0019 /*
0020  * ---- S/PDIF Transmitter Controller Register map ----
0021  */
0022 #define SPDIFTX_CR          0x00    /* Control Register */
0023 #define SPDIFTX_MR          0x04    /* Mode Register */
0024 #define SPDIFTX_CDR         0x0C    /* Common Data Register */
0025 
0026 #define SPDIFTX_IER         0x14    /* Interrupt Enable Register */
0027 #define SPDIFTX_IDR         0x18    /* Interrupt Disable Register */
0028 #define SPDIFTX_IMR         0x1C    /* Interrupt Mask Register */
0029 #define SPDIFTX_ISR         0x20    /* Interrupt Status Register */
0030 
0031 #define SPDIFTX_CH1UD(reg)  (0x50 + (reg) * 4)  /* User Data 1 Register x */
0032 #define SPDIFTX_CH1S(reg)   (0x80 + (reg) * 4)  /* Channel Status 1 Register x */
0033 
0034 #define SPDIFTX_VERSION         0xF0
0035 
0036 /*
0037  * ---- Control Register (Write-only) ----
0038  */
0039 #define SPDIFTX_CR_SWRST        BIT(0)  /* Software Reset */
0040 #define SPDIFTX_CR_FCLR         BIT(1)  /* FIFO clear */
0041 
0042 /*
0043  * ---- Mode Register (Read/Write) ----
0044  */
0045 /* Transmit Enable */
0046 #define SPDIFTX_MR_TXEN_MASK        GENMASK(0, 0)
0047 #define SPDIFTX_MR_TXEN_DISABLE     (0 << 0)
0048 #define SPDIFTX_MR_TXEN_ENABLE      (1 << 0)
0049 
0050 /* Multichannel Transfer */
0051 #define SPDIFTX_MR_MULTICH_MASK     GENAMSK(1, 1)
0052 #define SPDIFTX_MR_MULTICH_MONO     (0 << 1)
0053 #define SPDIFTX_MR_MULTICH_DUAL     (1 << 1)
0054 
0055 /* Data Word Endian Mode */
0056 #define SPDIFTX_MR_ENDIAN_MASK      GENMASK(2, 2)
0057 #define SPDIFTX_MR_ENDIAN_LITTLE    (0 << 2)
0058 #define SPDIFTX_MR_ENDIAN_BIG       (1 << 2)
0059 
0060 /* Data Justification */
0061 #define SPDIFTX_MR_JUSTIFY_MASK     GENMASK(3, 3)
0062 #define SPDIFTX_MR_JUSTIFY_LSB      (0 << 3)
0063 #define SPDIFTX_MR_JUSTIFY_MSB      (1 << 3)
0064 
0065 /* Common Audio Register Transfer Mode */
0066 #define SPDIFTX_MR_CMODE_MASK           GENMASK(5, 4)
0067 #define SPDIFTX_MR_CMODE_INDEX_ACCESS       (0 << 4)
0068 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS      (1 << 4)
0069 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS    (2 << 4)
0070 
0071 /* Valid Bits per Sample */
0072 #define SPDIFTX_MR_VBPS_MASK        GENMASK(13, 8)
0073 #define SPDIFTX_MR_VBPS(bps)        (((bps) << 8) & SPDIFTX_MR_VBPS_MASK)
0074 
0075 /* Chunk Size */
0076 #define SPDIFTX_MR_CHUNK_MASK       GENMASK(19, 16)
0077 #define SPDIFTX_MR_CHUNK(size)      (((size) << 16) & SPDIFTX_MR_CHUNK_MASK)
0078 
0079 /* Validity Bits for Channels 1 and 2 */
0080 #define SPDIFTX_MR_VALID1           BIT(24)
0081 #define SPDIFTX_MR_VALID2           BIT(25)
0082 
0083 /* Disable Null Frame on underrun */
0084 #define SPDIFTX_MR_DNFR_MASK        GENMASK(27, 27)
0085 #define SPDIFTX_MR_DNFR_INVALID     (0 << 27)
0086 #define SPDIFTX_MR_DNFR_VALID       (1 << 27)
0087 
0088 /* Bytes per Sample */
0089 #define SPDIFTX_MR_BPS_MASK     GENMASK(29, 28)
0090 #define SPDIFTX_MR_BPS(bytes) \
0091     ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK)
0092 
0093 /*
0094  * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ----
0095  */
0096 #define SPDIFTX_IR_TXRDY        BIT(0)
0097 #define SPDIFTX_IR_TXEMPTY      BIT(1)
0098 #define SPDIFTX_IR_TXFULL       BIT(2)
0099 #define SPDIFTX_IR_TXCHUNK      BIT(3)
0100 #define SPDIFTX_IR_TXUDR        BIT(4)
0101 #define SPDIFTX_IR_TXOVR        BIT(5)
0102 #define SPDIFTX_IR_CSRDY        BIT(6)
0103 #define SPDIFTX_IR_UDRDY        BIT(7)
0104 #define SPDIFTX_IR_TXRDYCH(ch)      BIT((ch) + 8)
0105 #define SPDIFTX_IR_SECE         BIT(10)
0106 #define SPDIFTX_IR_TXUDRCH(ch)      BIT((ch) + 11)
0107 #define SPDIFTX_IR_BEND         BIT(13)
0108 
0109 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg)
0110 {
0111     switch (reg) {
0112     case SPDIFTX_MR:
0113     case SPDIFTX_IMR:
0114     case SPDIFTX_ISR:
0115     case SPDIFTX_CH1UD(0):
0116     case SPDIFTX_CH1UD(1):
0117     case SPDIFTX_CH1UD(2):
0118     case SPDIFTX_CH1UD(3):
0119     case SPDIFTX_CH1UD(4):
0120     case SPDIFTX_CH1UD(5):
0121     case SPDIFTX_CH1S(0):
0122     case SPDIFTX_CH1S(1):
0123     case SPDIFTX_CH1S(2):
0124     case SPDIFTX_CH1S(3):
0125     case SPDIFTX_CH1S(4):
0126     case SPDIFTX_CH1S(5):
0127         return true;
0128     default:
0129         return false;
0130     }
0131 }
0132 
0133 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg)
0134 {
0135     switch (reg) {
0136     case SPDIFTX_CR:
0137     case SPDIFTX_MR:
0138     case SPDIFTX_CDR:
0139     case SPDIFTX_IER:
0140     case SPDIFTX_IDR:
0141     case SPDIFTX_CH1UD(0):
0142     case SPDIFTX_CH1UD(1):
0143     case SPDIFTX_CH1UD(2):
0144     case SPDIFTX_CH1UD(3):
0145     case SPDIFTX_CH1UD(4):
0146     case SPDIFTX_CH1UD(5):
0147     case SPDIFTX_CH1S(0):
0148     case SPDIFTX_CH1S(1):
0149     case SPDIFTX_CH1S(2):
0150     case SPDIFTX_CH1S(3):
0151     case SPDIFTX_CH1S(4):
0152     case SPDIFTX_CH1S(5):
0153         return true;
0154     default:
0155         return false;
0156     }
0157 }
0158 
0159 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg)
0160 {
0161     switch (reg) {
0162     case SPDIFTX_CDR:
0163     case SPDIFTX_ISR:
0164         return true;
0165     default:
0166         return false;
0167     }
0168 }
0169 
0170 static const struct regmap_config mchp_spdiftx_regmap_config = {
0171     .reg_bits = 32,
0172     .reg_stride = 4,
0173     .val_bits = 32,
0174     .max_register = SPDIFTX_VERSION,
0175     .readable_reg = mchp_spdiftx_readable_reg,
0176     .writeable_reg = mchp_spdiftx_writeable_reg,
0177     .precious_reg = mchp_spdiftx_precious_reg,
0178 };
0179 
0180 #define SPDIFTX_GCLK_RATIO  128
0181 
0182 #define SPDIFTX_CS_BITS     192
0183 #define SPDIFTX_UD_BITS     192
0184 
0185 struct mchp_spdiftx_mixer_control {
0186     unsigned char               ch_stat[SPDIFTX_CS_BITS / 8];
0187     unsigned char               user_data[SPDIFTX_UD_BITS / 8];
0188     spinlock_t              lock; /* exclusive access to control data */
0189 };
0190 
0191 struct mchp_spdiftx_dev {
0192     struct mchp_spdiftx_mixer_control   control;
0193     struct snd_dmaengine_dai_dma_data   playback;
0194     struct device               *dev;
0195     struct regmap               *regmap;
0196     struct clk              *pclk;
0197     struct clk              *gclk;
0198     unsigned int                fmt;
0199     unsigned int                gclk_enabled:1;
0200 };
0201 
0202 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev)
0203 {
0204     u32 mr;
0205 
0206     regmap_read(dev->regmap, SPDIFTX_MR, &mr);
0207     return !!(mr & SPDIFTX_MR_TXEN_ENABLE);
0208 }
0209 
0210 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev)
0211 {
0212     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0213     u32 val;
0214     int i;
0215 
0216     for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) {
0217         val = (ctrl->ch_stat[(i * 4) + 0] << 0) |
0218               (ctrl->ch_stat[(i * 4) + 1] << 8) |
0219               (ctrl->ch_stat[(i * 4) + 2] << 16) |
0220               (ctrl->ch_stat[(i * 4) + 3] << 24);
0221 
0222         regmap_write(dev->regmap, SPDIFTX_CH1S(i), val);
0223     }
0224 }
0225 
0226 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev)
0227 {
0228     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0229     u32 val;
0230     int i;
0231 
0232     for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) {
0233         val = (ctrl->user_data[(i * 4) + 0] << 0) |
0234               (ctrl->user_data[(i * 4) + 1] << 8) |
0235               (ctrl->user_data[(i * 4) + 2] << 16) |
0236               (ctrl->user_data[(i * 4) + 3] << 24);
0237 
0238         regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val);
0239     }
0240 }
0241 
0242 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id)
0243 {
0244     struct mchp_spdiftx_dev *dev = dev_id;
0245     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0246     u32 sr, imr, pending, idr = 0;
0247 
0248     regmap_read(dev->regmap, SPDIFTX_ISR, &sr);
0249     regmap_read(dev->regmap, SPDIFTX_IMR, &imr);
0250     pending = sr & imr;
0251 
0252     if (!pending)
0253         return IRQ_NONE;
0254 
0255     if (pending & SPDIFTX_IR_TXUDR) {
0256         dev_warn(dev->dev, "underflow detected\n");
0257         idr |= SPDIFTX_IR_TXUDR;
0258     }
0259 
0260     if (pending & SPDIFTX_IR_TXOVR) {
0261         dev_warn(dev->dev, "overflow detected\n");
0262         idr |= SPDIFTX_IR_TXOVR;
0263     }
0264 
0265     if (pending & SPDIFTX_IR_UDRDY) {
0266         spin_lock(&ctrl->lock);
0267         mchp_spdiftx_user_data_write(dev);
0268         spin_unlock(&ctrl->lock);
0269         idr |= SPDIFTX_IR_UDRDY;
0270     }
0271 
0272     if (pending & SPDIFTX_IR_CSRDY) {
0273         spin_lock(&ctrl->lock);
0274         mchp_spdiftx_channel_status_write(dev);
0275         spin_unlock(&ctrl->lock);
0276         idr |= SPDIFTX_IR_CSRDY;
0277     }
0278 
0279     regmap_write(dev->regmap, SPDIFTX_IDR, idr);
0280 
0281     return IRQ_HANDLED;
0282 }
0283 
0284 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream,
0285                     struct snd_soc_dai *dai)
0286 {
0287     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0288 
0289     /* Software reset the IP */
0290     regmap_write(dev->regmap, SPDIFTX_CR,
0291              SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
0292 
0293     return 0;
0294 }
0295 
0296 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream,
0297                       struct snd_soc_dai *dai)
0298 {
0299     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0300 
0301     /* Disable interrupts */
0302     regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff);
0303 }
0304 
0305 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd,
0306                 struct snd_soc_dai *dai)
0307 {
0308     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0309     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0310     u32 mr;
0311     int running;
0312     int ret;
0313 
0314     /* do not start/stop while channel status or user data is updated */
0315     spin_lock(&ctrl->lock);
0316     regmap_read(dev->regmap, SPDIFTX_MR, &mr);
0317     running = !!(mr & SPDIFTX_MR_TXEN_ENABLE);
0318 
0319     switch (cmd) {
0320     case SNDRV_PCM_TRIGGER_START:
0321     case SNDRV_PCM_TRIGGER_RESUME:
0322     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0323         if (!running) {
0324             mr &= ~SPDIFTX_MR_TXEN_MASK;
0325             mr |= SPDIFTX_MR_TXEN_ENABLE;
0326         }
0327         break;
0328     case SNDRV_PCM_TRIGGER_STOP:
0329     case SNDRV_PCM_TRIGGER_SUSPEND:
0330     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0331         if (running) {
0332             mr &= ~SPDIFTX_MR_TXEN_MASK;
0333             mr |= SPDIFTX_MR_TXEN_DISABLE;
0334         }
0335         break;
0336     default:
0337         spin_unlock(&ctrl->lock);
0338         return -EINVAL;
0339     }
0340 
0341     ret = regmap_write(dev->regmap, SPDIFTX_MR, mr);
0342     spin_unlock(&ctrl->lock);
0343     if (ret)
0344         dev_err(dev->dev, "unable to disable TX: %d\n", ret);
0345 
0346     return ret;
0347 }
0348 
0349 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream,
0350                   struct snd_pcm_hw_params *params,
0351                   struct snd_soc_dai *dai)
0352 {
0353     unsigned long flags;
0354     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0355     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0356     u32 mr;
0357     unsigned int bps = params_physical_width(params) / 8;
0358     int ret;
0359 
0360     dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
0361         __func__, params_rate(params), params_format(params),
0362         params_width(params), params_channels(params));
0363 
0364     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
0365         dev_err(dev->dev, "Capture is not supported\n");
0366         return -EINVAL;
0367     }
0368 
0369     regmap_read(dev->regmap, SPDIFTX_MR, &mr);
0370 
0371     if (mr & SPDIFTX_MR_TXEN_ENABLE) {
0372         dev_err(dev->dev, "PCM already running\n");
0373         return -EBUSY;
0374     }
0375 
0376     /* Defaults: Toggle mode, justify to LSB, chunksize 1 */
0377     mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB;
0378     dev->playback.maxburst = 1;
0379     switch (params_channels(params)) {
0380     case 1:
0381         mr |= SPDIFTX_MR_MULTICH_MONO;
0382         break;
0383     case 2:
0384         mr |= SPDIFTX_MR_MULTICH_DUAL;
0385         if (bps > 2)
0386             dev->playback.maxburst = 2;
0387         break;
0388     default:
0389         dev_err(dev->dev, "unsupported number of channels: %d\n",
0390             params_channels(params));
0391         return -EINVAL;
0392     }
0393     mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst);
0394 
0395     switch (params_format(params)) {
0396     case SNDRV_PCM_FORMAT_S8:
0397         mr |= SPDIFTX_MR_VBPS(8);
0398         break;
0399     case SNDRV_PCM_FORMAT_S16_BE:
0400         mr |= SPDIFTX_MR_ENDIAN_BIG;
0401         fallthrough;
0402     case SNDRV_PCM_FORMAT_S16_LE:
0403         mr |= SPDIFTX_MR_VBPS(16);
0404         break;
0405     case SNDRV_PCM_FORMAT_S18_3BE:
0406         mr |= SPDIFTX_MR_ENDIAN_BIG;
0407         fallthrough;
0408     case SNDRV_PCM_FORMAT_S18_3LE:
0409         mr |= SPDIFTX_MR_VBPS(18);
0410         break;
0411     case SNDRV_PCM_FORMAT_S20_3BE:
0412         mr |= SPDIFTX_MR_ENDIAN_BIG;
0413         fallthrough;
0414     case SNDRV_PCM_FORMAT_S20_3LE:
0415         mr |= SPDIFTX_MR_VBPS(20);
0416         break;
0417     case SNDRV_PCM_FORMAT_S24_3BE:
0418         mr |= SPDIFTX_MR_ENDIAN_BIG;
0419         fallthrough;
0420     case SNDRV_PCM_FORMAT_S24_3LE:
0421         mr |= SPDIFTX_MR_VBPS(24);
0422         break;
0423     case SNDRV_PCM_FORMAT_S24_BE:
0424         mr |= SPDIFTX_MR_ENDIAN_BIG;
0425         fallthrough;
0426     case SNDRV_PCM_FORMAT_S24_LE:
0427         mr |= SPDIFTX_MR_VBPS(24);
0428         break;
0429     case SNDRV_PCM_FORMAT_S32_BE:
0430         mr |= SPDIFTX_MR_ENDIAN_BIG;
0431         fallthrough;
0432     case SNDRV_PCM_FORMAT_S32_LE:
0433         mr |= SPDIFTX_MR_VBPS(32);
0434         break;
0435     default:
0436         dev_err(dev->dev, "unsupported PCM format: %d\n",
0437             params_format(params));
0438         return -EINVAL;
0439     }
0440 
0441     mr |= SPDIFTX_MR_BPS(bps);
0442 
0443     spin_lock_irqsave(&ctrl->lock, flags);
0444     ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS;
0445     switch (params_rate(params)) {
0446     case 22050:
0447         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050;
0448         break;
0449     case 24000:
0450         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000;
0451         break;
0452     case 32000:
0453         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000;
0454         break;
0455     case 44100:
0456         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100;
0457         break;
0458     case 48000:
0459         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000;
0460         break;
0461     case 88200:
0462         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200;
0463         break;
0464     case 96000:
0465         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000;
0466         break;
0467     case 176400:
0468         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400;
0469         break;
0470     case 192000:
0471         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000;
0472         break;
0473     case 8000:
0474     case 11025:
0475     case 16000:
0476     case 64000:
0477         ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID;
0478         break;
0479     default:
0480         dev_err(dev->dev, "unsupported sample frequency: %u\n",
0481             params_rate(params));
0482         spin_unlock_irqrestore(&ctrl->lock, flags);
0483         return -EINVAL;
0484     }
0485     mchp_spdiftx_channel_status_write(dev);
0486     spin_unlock_irqrestore(&ctrl->lock, flags);
0487 
0488     if (dev->gclk_enabled) {
0489         clk_disable_unprepare(dev->gclk);
0490         dev->gclk_enabled = 0;
0491     }
0492     ret = clk_set_rate(dev->gclk, params_rate(params) *
0493                       SPDIFTX_GCLK_RATIO);
0494     if (ret) {
0495         dev_err(dev->dev,
0496             "unable to change gclk rate to: rate %u * ratio %u\n",
0497             params_rate(params), SPDIFTX_GCLK_RATIO);
0498         return ret;
0499     }
0500     ret = clk_prepare_enable(dev->gclk);
0501     if (ret) {
0502         dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
0503         return ret;
0504     }
0505     dev->gclk_enabled = 1;
0506     dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__,
0507         params_rate(params) * SPDIFTX_GCLK_RATIO);
0508 
0509     /* Enable interrupts */
0510     regmap_write(dev->regmap, SPDIFTX_IER,
0511              SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
0512 
0513     regmap_write(dev->regmap, SPDIFTX_MR, mr);
0514 
0515     return 0;
0516 }
0517 
0518 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream,
0519                 struct snd_soc_dai *dai)
0520 {
0521     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0522 
0523     regmap_write(dev->regmap, SPDIFTX_IDR,
0524              SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
0525     if (dev->gclk_enabled) {
0526         clk_disable_unprepare(dev->gclk);
0527         dev->gclk_enabled = 0;
0528     }
0529 
0530     return regmap_write(dev->regmap, SPDIFTX_CR,
0531                 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
0532 }
0533 
0534 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = {
0535     .startup    = mchp_spdiftx_dai_startup,
0536     .shutdown   = mchp_spdiftx_dai_shutdown,
0537     .trigger    = mchp_spdiftx_trigger,
0538     .hw_params  = mchp_spdiftx_hw_params,
0539     .hw_free    = mchp_spdiftx_hw_free,
0540 };
0541 
0542 #define MCHP_SPDIFTX_RATES  SNDRV_PCM_RATE_8000_192000
0543 
0544 #define MCHP_SPDIFTX_FORMATS    (SNDRV_PCM_FMTBIT_S8 |      \
0545                  SNDRV_PCM_FMTBIT_S16_LE |  \
0546                  SNDRV_PCM_FMTBIT_U16_BE |  \
0547                  SNDRV_PCM_FMTBIT_S18_3LE | \
0548                  SNDRV_PCM_FMTBIT_S18_3BE | \
0549                  SNDRV_PCM_FMTBIT_S20_3LE | \
0550                  SNDRV_PCM_FMTBIT_S20_3BE | \
0551                  SNDRV_PCM_FMTBIT_S24_3LE | \
0552                  SNDRV_PCM_FMTBIT_S24_3BE | \
0553                  SNDRV_PCM_FMTBIT_S24_LE |  \
0554                  SNDRV_PCM_FMTBIT_S24_BE |  \
0555                  SNDRV_PCM_FMTBIT_S32_LE |  \
0556                  SNDRV_PCM_FMTBIT_S32_BE    \
0557                  )
0558 
0559 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol,
0560                  struct snd_ctl_elem_info *uinfo)
0561 {
0562     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0563     uinfo->count = 1;
0564 
0565     return 0;
0566 }
0567 
0568 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol,
0569                    struct snd_ctl_elem_value *uvalue)
0570 {
0571     unsigned long flags;
0572     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0573     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0574     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0575 
0576     spin_lock_irqsave(&ctrl->lock, flags);
0577     memcpy(uvalue->value.iec958.status, ctrl->ch_stat,
0578            sizeof(ctrl->ch_stat));
0579     spin_unlock_irqrestore(&ctrl->lock, flags);
0580 
0581     return 0;
0582 }
0583 
0584 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol,
0585                    struct snd_ctl_elem_value *uvalue)
0586 {
0587     unsigned long flags;
0588     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0589     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0590     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0591     int changed = 0;
0592     int i;
0593 
0594     spin_lock_irqsave(&ctrl->lock, flags);
0595     for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) {
0596         if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i])
0597             changed = 1;
0598         ctrl->ch_stat[i] = uvalue->value.iec958.status[i];
0599     }
0600 
0601     if (changed) {
0602         /* don't enable IP while we copy the channel status */
0603         if (mchp_spdiftx_is_running(dev)) {
0604             /*
0605              * if SPDIF is running, wait for interrupt to write
0606              * channel status
0607              */
0608             regmap_write(dev->regmap, SPDIFTX_IER,
0609                      SPDIFTX_IR_CSRDY);
0610         } else {
0611             mchp_spdiftx_channel_status_write(dev);
0612         }
0613     }
0614     spin_unlock_irqrestore(&ctrl->lock, flags);
0615 
0616     return changed;
0617 }
0618 
0619 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol,
0620                 struct snd_ctl_elem_value *uvalue)
0621 {
0622     memset(uvalue->value.iec958.status, 0xff,
0623            sizeof(uvalue->value.iec958.status));
0624 
0625     return 0;
0626 }
0627 
0628 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol,
0629                     struct snd_ctl_elem_value *uvalue)
0630 {
0631     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0632     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0633     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0634     unsigned long flags;
0635 
0636     spin_lock_irqsave(&ctrl->lock, flags);
0637     memcpy(uvalue->value.iec958.subcode, ctrl->user_data,
0638            sizeof(ctrl->user_data));
0639     spin_unlock_irqrestore(&ctrl->lock, flags);
0640 
0641     return 0;
0642 }
0643 
0644 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol,
0645                     struct snd_ctl_elem_value *uvalue)
0646 {
0647     unsigned long flags;
0648     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0649     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0650     struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
0651     int changed = 0;
0652     int i;
0653 
0654     spin_lock_irqsave(&ctrl->lock, flags);
0655     for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) {
0656         if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i])
0657             changed = 1;
0658 
0659         ctrl->user_data[i] = uvalue->value.iec958.subcode[i];
0660     }
0661     if (changed) {
0662         if (mchp_spdiftx_is_running(dev)) {
0663             /*
0664              * if SPDIF is running, wait for interrupt to write
0665              * user data
0666              */
0667             regmap_write(dev->regmap, SPDIFTX_IER,
0668                      SPDIFTX_IR_UDRDY);
0669         } else {
0670             mchp_spdiftx_user_data_write(dev);
0671         }
0672     }
0673     spin_unlock_irqrestore(&ctrl->lock, flags);
0674 
0675     return changed;
0676 }
0677 
0678 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = {
0679     /* Channel status controller */
0680     {
0681         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0682         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
0683         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
0684             SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0685         .info = mchp_spdiftx_info,
0686         .get = mchp_spdiftx_cs_get,
0687         .put = mchp_spdiftx_cs_put,
0688     },
0689     {
0690         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0691         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
0692         .access = SNDRV_CTL_ELEM_ACCESS_READ,
0693             SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0694         .info = mchp_spdiftx_info,
0695         .get = mchp_spdiftx_cs_mask,
0696     },
0697     /* User bits controller */
0698     {
0699         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0700         .name = "IEC958 Subcode Playback Default",
0701         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
0702         .info = mchp_spdiftx_info,
0703         .get = mchp_spdiftx_subcode_get,
0704         .put = mchp_spdiftx_subcode_put,
0705     },
0706 };
0707 
0708 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai)
0709 {
0710     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0711     int ret;
0712 
0713     snd_soc_dai_init_dma_data(dai, &dev->playback, NULL);
0714 
0715     ret = clk_prepare_enable(dev->pclk);
0716     if (ret) {
0717         dev_err(dev->dev,
0718             "failed to enable the peripheral clock: %d\n", ret);
0719         return ret;
0720     }
0721 
0722     /* Add controls */
0723     snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls,
0724                  ARRAY_SIZE(mchp_spdiftx_ctrls));
0725 
0726     return 0;
0727 }
0728 
0729 static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai)
0730 {
0731     struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
0732 
0733     clk_disable_unprepare(dev->pclk);
0734 
0735     return 0;
0736 }
0737 
0738 static struct snd_soc_dai_driver mchp_spdiftx_dai = {
0739     .name = "mchp-spdiftx",
0740     .probe  = mchp_spdiftx_dai_probe,
0741     .remove = mchp_spdiftx_dai_remove,
0742     .playback = {
0743         .stream_name = "S/PDIF Playback",
0744         .channels_min = 1,
0745         .channels_max = 2,
0746         .rates = MCHP_SPDIFTX_RATES,
0747         .formats = MCHP_SPDIFTX_FORMATS,
0748     },
0749     .ops = &mchp_spdiftx_dai_ops,
0750 };
0751 
0752 static const struct snd_soc_component_driver mchp_spdiftx_component = {
0753     .name           = "mchp-spdiftx",
0754     .legacy_dai_naming  = 1,
0755 };
0756 
0757 static const struct of_device_id mchp_spdiftx_dt_ids[] = {
0758     {
0759         .compatible = "microchip,sama7g5-spdiftx",
0760     },
0761     { /* sentinel */ }
0762 };
0763 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids);
0764 
0765 static int mchp_spdiftx_probe(struct platform_device *pdev)
0766 {
0767     struct mchp_spdiftx_dev *dev;
0768     struct resource *mem;
0769     struct regmap *regmap;
0770     void __iomem *base;
0771     struct mchp_spdiftx_mixer_control *ctrl;
0772     int irq;
0773     int err;
0774 
0775     /* Get memory for driver data. */
0776     dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
0777     if (!dev)
0778         return -ENOMEM;
0779 
0780     /* Map I/O registers. */
0781     base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
0782     if (IS_ERR(base))
0783         return PTR_ERR(base);
0784 
0785     regmap = devm_regmap_init_mmio(&pdev->dev, base,
0786                        &mchp_spdiftx_regmap_config);
0787     if (IS_ERR(regmap))
0788         return PTR_ERR(regmap);
0789 
0790     /* Request IRQ */
0791     irq = platform_get_irq(pdev, 0);
0792     if (irq < 0)
0793         return irq;
0794 
0795     err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0,
0796                    dev_name(&pdev->dev), dev);
0797     if (err)
0798         return err;
0799 
0800     /* Get the peripheral clock */
0801     dev->pclk = devm_clk_get(&pdev->dev, "pclk");
0802     if (IS_ERR(dev->pclk)) {
0803         err = PTR_ERR(dev->pclk);
0804         dev_err(&pdev->dev,
0805             "failed to get the peripheral clock: %d\n", err);
0806         return err;
0807     }
0808 
0809     /* Get the generic clock */
0810     dev->gclk = devm_clk_get(&pdev->dev, "gclk");
0811     if (IS_ERR(dev->gclk)) {
0812         err = PTR_ERR(dev->gclk);
0813         dev_err(&pdev->dev,
0814             "failed to get the PMC generic clock: %d\n", err);
0815         return err;
0816     }
0817 
0818     ctrl = &dev->control;
0819     spin_lock_init(&ctrl->lock);
0820 
0821     /* Init channel status */
0822     ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
0823                IEC958_AES0_CON_EMPHASIS_NONE;
0824 
0825     dev->dev = &pdev->dev;
0826     dev->regmap = regmap;
0827     platform_set_drvdata(pdev, dev);
0828 
0829     dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR;
0830     dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0831 
0832     err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
0833     if (err) {
0834         dev_err(&pdev->dev, "failed to register PMC: %d\n", err);
0835         return err;
0836     }
0837 
0838     err = devm_snd_soc_register_component(&pdev->dev,
0839                           &mchp_spdiftx_component,
0840                           &mchp_spdiftx_dai, 1);
0841     if (err)
0842         dev_err(&pdev->dev, "failed to register component: %d\n", err);
0843 
0844     return err;
0845 }
0846 
0847 static struct platform_driver mchp_spdiftx_driver = {
0848     .probe  = mchp_spdiftx_probe,
0849     .driver = {
0850         .name   = "mchp_spdiftx",
0851         .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids),
0852     },
0853 };
0854 
0855 module_platform_driver(mchp_spdiftx_driver);
0856 
0857 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
0858 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver");
0859 MODULE_LICENSE("GPL v2");
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