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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces
0004 //
0005 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
0006 //
0007 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
0008 
0009 #include <dt-bindings/sound/microchip,pdmc.h>
0010 
0011 #include <linux/clk.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/regmap.h>
0015 
0016 #include <sound/core.h>
0017 #include <sound/dmaengine_pcm.h>
0018 #include <sound/pcm_params.h>
0019 #include <sound/tlv.h>
0020 
0021 /*
0022  * ---- PDMC Register map ----
0023  */
0024 #define MCHP_PDMC_CR            0x00    /* Control Register */
0025 #define MCHP_PDMC_MR            0x04    /* Mode Register */
0026 #define MCHP_PDMC_CFGR          0x08    /* Configuration Register */
0027 #define MCHP_PDMC_RHR           0x0C    /* Receive Holding Register */
0028 #define MCHP_PDMC_IER           0x14    /* Interrupt Enable Register */
0029 #define MCHP_PDMC_IDR           0x18    /* Interrupt Disable Register */
0030 #define MCHP_PDMC_IMR           0x1C    /* Interrupt Mask Register */
0031 #define MCHP_PDMC_ISR           0x20    /* Interrupt Status Register */
0032 #define MCHP_PDMC_VER           0x50    /* Version Register */
0033 
0034 /*
0035  * ---- Control Register (Write-only) ----
0036  */
0037 #define MCHP_PDMC_CR_SWRST      BIT(0)  /* Software Reset */
0038 
0039 /*
0040  * ---- Mode Register (Read/Write) ----
0041  */
0042 #define MCHP_PDMC_MR_PDMCEN_MASK    GENMASK(3, 0)
0043 #define MCHP_PDMC_MR_PDMCEN(ch)     (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK)
0044 
0045 #define MCHP_PDMC_MR_OSR_MASK       GENMASK(17, 16)
0046 #define MCHP_PDMC_MR_OSR64      (1 << 16)
0047 #define MCHP_PDMC_MR_OSR128     (2 << 16)
0048 #define MCHP_PDMC_MR_OSR256     (3 << 16)
0049 
0050 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20)
0051 #define MCHP_PDMC_MR_SINCORDER(order)   (((order) << 20) & \
0052                      MCHP_PDMC_MR_SINCORDER_MASK)
0053 
0054 #define MCHP_PDMC_MR_SINC_OSR_MASK  GENMASK(27, 24)
0055 #define MCHP_PDMC_MR_SINC_OSR_DIS   (0 << 24)
0056 #define MCHP_PDMC_MR_SINC_OSR_8     (1 << 24)
0057 #define MCHP_PDMC_MR_SINC_OSR_16    (2 << 24)
0058 #define MCHP_PDMC_MR_SINC_OSR_32    (3 << 24)
0059 #define MCHP_PDMC_MR_SINC_OSR_64    (4 << 24)
0060 #define MCHP_PDMC_MR_SINC_OSR_128   (5 << 24)
0061 #define MCHP_PDMC_MR_SINC_OSR_256   (6 << 24)
0062 
0063 #define MCHP_PDMC_MR_CHUNK_MASK     GENMASK(31, 28)
0064 #define MCHP_PDMC_MR_CHUNK(chunk)   (((chunk) << 28) & \
0065                      MCHP_PDMC_MR_CHUNK_MASK)
0066 
0067 /*
0068  * ---- Configuration Register (Read/Write) ----
0069  */
0070 #define MCHP_PDMC_CFGR_BSSEL_MASK   (BIT(0) | BIT(2) | BIT(4) | BIT(6))
0071 #define MCHP_PDMC_CFGR_BSSEL(ch)    BIT((ch) * 2)
0072 
0073 #define MCHP_PDMC_CFGR_PDMSEL_MASK  (BIT(16) | BIT(18) | BIT(20) | BIT(22))
0074 #define MCHP_PDMC_CFGR_PDMSEL(ch)   BIT((ch) * 2 + 16)
0075 
0076 /*
0077  * ---- Interrupt Enable/Disable/Mask/Status Registers ----
0078  */
0079 #define MCHP_PDMC_IR_RXRDY      BIT(0)
0080 #define MCHP_PDMC_IR_RXEMPTY        BIT(1)
0081 #define MCHP_PDMC_IR_RXFULL     BIT(2)
0082 #define MCHP_PDMC_IR_RXCHUNK        BIT(3)
0083 #define MCHP_PDMC_IR_RXUDR      BIT(4)
0084 #define MCHP_PDMC_IR_RXOVR      BIT(5)
0085 
0086 /*
0087  * ---- Version Register (Read-only) ----
0088  */
0089 #define MCHP_PDMC_VER_VERSION       GENMASK(11, 0)
0090 
0091 #define MCHP_PDMC_MAX_CHANNELS      4
0092 #define MCHP_PDMC_DS_NO         2
0093 #define MCHP_PDMC_EDGE_NO       2
0094 
0095 struct mic_map {
0096     int ds_pos;
0097     int clk_edge;
0098 };
0099 
0100 struct mchp_pdmc_chmap {
0101     struct snd_pcm_chmap_elem *chmap;
0102     struct mchp_pdmc *dd;
0103     struct snd_pcm *pcm;
0104     struct snd_kcontrol *kctl;
0105 };
0106 
0107 struct mchp_pdmc {
0108     struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS];
0109     struct device *dev;
0110     struct snd_dmaengine_dai_dma_data addr;
0111     struct regmap *regmap;
0112     struct clk *pclk;
0113     struct clk *gclk;
0114     u32 pdmcen;
0115     int mic_no;
0116     int sinc_order;
0117     bool audio_filter_en;
0118     u8 gclk_enabled:1;
0119 };
0120 
0121 static const char *const mchp_pdmc_sinc_filter_order_text[] = {
0122     "1", "2", "3", "4", "5"
0123 };
0124 
0125 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = {
0126     1, 2, 3, 4, 5,
0127 };
0128 
0129 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = {
0130     .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text),
0131     .texts = mchp_pdmc_sinc_filter_order_text,
0132     .values = mchp_pdmc_sinc_filter_order_values,
0133 };
0134 
0135 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol,
0136                     struct snd_ctl_elem_value *uvalue)
0137 {
0138     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0139     struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
0140     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0141     unsigned int item;
0142 
0143     item = snd_soc_enum_val_to_item(e, dd->sinc_order);
0144     uvalue->value.enumerated.item[0] = item;
0145 
0146     return 0;
0147 }
0148 
0149 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol,
0150                     struct snd_ctl_elem_value *uvalue)
0151 {
0152     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0153     struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
0154     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0155     unsigned int *item = uvalue->value.enumerated.item;
0156     unsigned int val;
0157 
0158     if (item[0] >= e->items)
0159         return -EINVAL;
0160 
0161     val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
0162     if (val == dd->sinc_order)
0163         return 0;
0164 
0165     dd->sinc_order = val;
0166 
0167     return 1;
0168 }
0169 
0170 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol,
0171                 struct snd_ctl_elem_value *uvalue)
0172 {
0173     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0174     struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
0175 
0176     uvalue->value.integer.value[0] = !!dd->audio_filter_en;
0177 
0178     return 0;
0179 }
0180 
0181 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol,
0182                 struct snd_ctl_elem_value *uvalue)
0183 {
0184     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0185     struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
0186     bool af = uvalue->value.integer.value[0] ? true : false;
0187 
0188     if (dd->audio_filter_en == af)
0189         return 0;
0190 
0191     dd->audio_filter_en = af;
0192 
0193     return 1;
0194 }
0195 
0196 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0197 {
0198     struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
0199 
0200     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0201     uinfo->count = info->dd->mic_no;
0202     uinfo->value.integer.min = 0;
0203     uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */
0204     return 0;
0205 }
0206 
0207 static inline struct snd_pcm_substream *
0208 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx)
0209 {
0210     struct snd_pcm_substream *s;
0211 
0212     for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next)
0213         if (s->number == idx)
0214             return s;
0215     return NULL;
0216 }
0217 
0218 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream,
0219                               struct mchp_pdmc_chmap *ch_info)
0220 {
0221     struct snd_pcm_chmap_elem *map;
0222 
0223     for (map = ch_info->chmap; map->channels; map++) {
0224         if (map->channels == substream->runtime->channels)
0225             return map;
0226     }
0227     return NULL;
0228 }
0229 
0230 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol,
0231                    struct snd_ctl_elem_value *ucontrol)
0232 {
0233     struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
0234     struct mchp_pdmc *dd = info->dd;
0235     unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
0236     struct snd_pcm_substream *substream;
0237     const struct snd_pcm_chmap_elem *map;
0238     int i;
0239     u32 cfgr_val = 0;
0240 
0241     if (!info->chmap)
0242         return -EINVAL;
0243     substream = mchp_pdmc_chmap_substream(info, idx);
0244     if (!substream)
0245         return -ENODEV;
0246     memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no);
0247     if (!substream->runtime)
0248         return 0; /* no channels set */
0249 
0250     map = mchp_pdmc_chmap_get(substream, info);
0251     if (!map)
0252         return -EINVAL;
0253 
0254     for (i = 0; i < map->channels; i++) {
0255         int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
0256                            map->map[i] - SNDRV_CHMAP_FL;
0257 
0258         /* make sure the reported channel map is the real one, so write the map */
0259         if (dd->channel_mic_map[map_idx].ds_pos)
0260             cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
0261         if (dd->channel_mic_map[map_idx].clk_edge)
0262             cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
0263 
0264         ucontrol->value.integer.value[i] = map->map[i];
0265     }
0266 
0267     regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
0268 
0269     return 0;
0270 }
0271 
0272 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol,
0273                    struct snd_ctl_elem_value *ucontrol)
0274 {
0275     struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
0276     struct mchp_pdmc *dd = info->dd;
0277     unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
0278     struct snd_pcm_substream *substream;
0279     struct snd_pcm_chmap_elem *map;
0280     u32 cfgr_val = 0;
0281     int i;
0282 
0283     if (!info->chmap)
0284         return -EINVAL;
0285     substream = mchp_pdmc_chmap_substream(info, idx);
0286     if (!substream)
0287         return -ENODEV;
0288 
0289     map = mchp_pdmc_chmap_get(substream, info);
0290     if (!map)
0291         return -EINVAL;
0292 
0293     for (i = 0; i < map->channels; i++) {
0294         int map_idx;
0295 
0296         map->map[i] = ucontrol->value.integer.value[i];
0297         map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
0298                            map->map[i] - SNDRV_CHMAP_FL;
0299 
0300         /* configure IP for the desired channel map */
0301         if (dd->channel_mic_map[map_idx].ds_pos)
0302             cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
0303         if (dd->channel_mic_map[map_idx].clk_edge)
0304             cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
0305     }
0306 
0307     regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
0308 
0309     return 0;
0310 }
0311 
0312 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol)
0313 {
0314     struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
0315 
0316     info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL;
0317     kfree(info);
0318 }
0319 
0320 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
0321                    unsigned int size, unsigned int __user *tlv)
0322 {
0323     struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
0324     const struct snd_pcm_chmap_elem *map;
0325     unsigned int __user *dst;
0326     int c, count = 0;
0327 
0328     if (!info->chmap)
0329         return -EINVAL;
0330     if (size < 8)
0331         return -ENOMEM;
0332     if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
0333         return -EFAULT;
0334     size -= 8;
0335     dst = tlv + 2;
0336     for (map = info->chmap; map->channels; map++) {
0337         int chs_bytes = map->channels * 4;
0338 
0339         if (size < 8)
0340             return -ENOMEM;
0341         if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
0342             put_user(chs_bytes, dst + 1))
0343             return -EFAULT;
0344         dst += 2;
0345         size -= 8;
0346         count += 8;
0347         if (size < chs_bytes)
0348             return -ENOMEM;
0349         size -= chs_bytes;
0350         count += chs_bytes;
0351         for (c = 0; c < map->channels; c++) {
0352             if (put_user(map->map[c], dst))
0353                 return -EFAULT;
0354             dst++;
0355         }
0356     }
0357     if (put_user(count, tlv + 1))
0358         return -EFAULT;
0359     return 0;
0360 }
0361 
0362 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = {
0363     SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put),
0364     {
0365         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0366         .name = "SINC Filter Order",
0367         .info = snd_soc_info_enum_double,
0368         .get = mchp_pdmc_sinc_order_get,
0369         .put = mchp_pdmc_sinc_order_put,
0370         .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum,
0371     },
0372 };
0373 
0374 static int mchp_pdmc_close(struct snd_soc_component *component,
0375                struct snd_pcm_substream *substream)
0376 {
0377     return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls,
0378                           ARRAY_SIZE(mchp_pdmc_snd_controls));
0379 }
0380 
0381 static int mchp_pdmc_open(struct snd_soc_component *component,
0382               struct snd_pcm_substream *substream)
0383 {
0384     int i;
0385 
0386     /* remove controls that can't be changed at runtime */
0387     for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) {
0388         const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i];
0389         struct snd_ctl_elem_id id;
0390         struct snd_kcontrol *kctl;
0391         int err;
0392 
0393         if (component->name_prefix)
0394             snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix,
0395                  control->name);
0396         else
0397             strscpy(id.name, control->name, sizeof(id.name));
0398 
0399         id.numid = 0;
0400         id.iface = control->iface;
0401         id.device = control->device;
0402         id.subdevice = control->subdevice;
0403         id.index = control->index;
0404         kctl = snd_ctl_find_id(component->card->snd_card, &id);
0405         if (!kctl) {
0406             dev_err(component->dev, "Failed to find %s\n", control->name);
0407             continue;
0408         }
0409         err = snd_ctl_remove(component->card->snd_card, kctl);
0410         if (err < 0) {
0411             dev_err(component->dev, "%d: Failed to remove %s\n", err,
0412                 control->name);
0413             continue;
0414         }
0415     }
0416 
0417     return 0;
0418 }
0419 
0420 static const struct snd_soc_component_driver mchp_pdmc_dai_component = {
0421     .name = "mchp-pdmc",
0422     .controls = mchp_pdmc_snd_controls,
0423     .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls),
0424     .open = &mchp_pdmc_open,
0425     .close = &mchp_pdmc_close,
0426     .legacy_dai_naming = 1,
0427 };
0428 
0429 static const unsigned int mchp_pdmc_1mic[] = {1};
0430 static const unsigned int mchp_pdmc_2mic[] = {1, 2};
0431 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3};
0432 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4};
0433 
0434 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = {
0435     {
0436         .list = mchp_pdmc_1mic,
0437         .count = ARRAY_SIZE(mchp_pdmc_1mic),
0438     },
0439     {
0440         .list = mchp_pdmc_2mic,
0441         .count = ARRAY_SIZE(mchp_pdmc_2mic),
0442     },
0443     {
0444         .list = mchp_pdmc_3mic,
0445         .count = ARRAY_SIZE(mchp_pdmc_3mic),
0446     },
0447     {
0448         .list = mchp_pdmc_4mic,
0449         .count = ARRAY_SIZE(mchp_pdmc_4mic),
0450     },
0451 };
0452 
0453 static int mchp_pdmc_startup(struct snd_pcm_substream *substream,
0454                  struct snd_soc_dai *dai)
0455 {
0456     struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
0457     int ret;
0458 
0459     ret = clk_prepare_enable(dd->pclk);
0460     if (ret) {
0461         dev_err(dd->dev, "failed to enable the peripheral clock: %d\n", ret);
0462         return ret;
0463     }
0464 
0465     regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST);
0466 
0467     snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
0468                    &mchp_pdmc_chan_constr[dd->mic_no - 1]);
0469 
0470     return 0;
0471 }
0472 
0473 static void mchp_pdmc_shutdown(struct snd_pcm_substream *substream,
0474                    struct snd_soc_dai *dai)
0475 {
0476     struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
0477 
0478     clk_disable_unprepare(dd->pclk);
0479 }
0480 
0481 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai)
0482 {
0483     struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
0484 
0485     snd_soc_dai_init_dma_data(dai, NULL, &dd->addr);
0486 
0487     return 0;
0488 }
0489 
0490 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0491 {
0492     unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK;
0493     unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0494 
0495     /* IP needs to be bitclock master */
0496     if (fmt_master != SND_SOC_DAIFMT_BP_FP &&
0497         fmt_master != SND_SOC_DAIFMT_BP_FC)
0498         return -EINVAL;
0499 
0500     /* IP supports only PDM interface */
0501     if (fmt_format != SND_SOC_DAIFMT_PDM)
0502         return -EINVAL;
0503 
0504     return 0;
0505 }
0506 
0507 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr)
0508 {
0509     if (audio_filter_en) {
0510         switch (osr) {
0511         case 64:
0512             return MCHP_PDMC_MR_OSR64;
0513         case 128:
0514             return MCHP_PDMC_MR_OSR128;
0515         case 256:
0516             return MCHP_PDMC_MR_OSR256;
0517         }
0518     } else {
0519         switch (osr) {
0520         case 8:
0521             return MCHP_PDMC_MR_SINC_OSR_8;
0522         case 16:
0523             return MCHP_PDMC_MR_SINC_OSR_16;
0524         case 32:
0525             return MCHP_PDMC_MR_SINC_OSR_32;
0526         case 64:
0527             return MCHP_PDMC_MR_SINC_OSR_64;
0528         case 128:
0529             return MCHP_PDMC_MR_SINC_OSR_128;
0530         case 256:
0531             return MCHP_PDMC_MR_SINC_OSR_256;
0532         }
0533     }
0534     return 0;
0535 }
0536 
0537 static inline int mchp_pdmc_period_to_maxburst(int period_size)
0538 {
0539     if (!(period_size % 8))
0540         return 8;
0541     if (!(period_size % 4))
0542         return 4;
0543     if (!(period_size % 2))
0544         return 2;
0545     return 1;
0546 }
0547 
0548 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = {
0549     { .channels = 1,
0550       .map = { SNDRV_CHMAP_MONO } },
0551     { .channels = 2,
0552       .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
0553     { .channels = 3,
0554       .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
0555            SNDRV_CHMAP_RL } },
0556     { .channels = 4,
0557       .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
0558            SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
0559     { }
0560 };
0561 
0562 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream,
0563                    struct snd_pcm_hw_params *params,
0564                    struct snd_soc_dai *dai)
0565 {
0566     struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
0567     struct snd_soc_component *comp = dai->component;
0568     unsigned long gclk_rate = 0;
0569     unsigned long best_diff_rate = ~0UL;
0570     unsigned int channels = params_channels(params);
0571     unsigned int osr = 0, osr_start;
0572     unsigned int fs = params_rate(params);
0573     u32 mr_val = 0;
0574     u32 cfgr_val = 0;
0575     int i;
0576     int ret;
0577 
0578     dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
0579         __func__, params_rate(params), params_format(params),
0580         params_width(params), params_channels(params));
0581 
0582     if (channels > dd->mic_no) {
0583         dev_err(comp->dev, "more channels %u than microphones %d\n",
0584             channels, dd->mic_no);
0585         return -EINVAL;
0586     }
0587 
0588     dd->pdmcen = 0;
0589     for (i = 0; i < channels; i++) {
0590         dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i);
0591         if (dd->channel_mic_map[i].ds_pos)
0592             cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
0593         if (dd->channel_mic_map[i].clk_edge)
0594             cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
0595     }
0596 
0597     if (dd->gclk_enabled) {
0598         clk_disable_unprepare(dd->gclk);
0599         dd->gclk_enabled = 0;
0600     }
0601 
0602     for (osr_start = dd->audio_filter_en ? 64 : 8;
0603          osr_start <= 256 && best_diff_rate; osr_start *= 2) {
0604         long round_rate;
0605         unsigned long diff_rate;
0606 
0607         round_rate = clk_round_rate(dd->gclk,
0608                         (unsigned long)fs * 16 * osr_start);
0609         if (round_rate < 0)
0610             continue;
0611         diff_rate = abs((fs * 16 * osr_start) - round_rate);
0612         if (diff_rate < best_diff_rate) {
0613             best_diff_rate = diff_rate;
0614             osr = osr_start;
0615             gclk_rate = fs * 16 * osr;
0616         }
0617     }
0618     if (!gclk_rate) {
0619         dev_err(comp->dev, "invalid sampling rate: %u\n", fs);
0620         return -EINVAL;
0621     }
0622 
0623     /* set the rate */
0624     ret = clk_set_rate(dd->gclk, gclk_rate);
0625     if (ret) {
0626         dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n",
0627             gclk_rate, ret);
0628         return ret;
0629     }
0630 
0631     mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr);
0632 
0633     mr_val |= MCHP_PDMC_MR_SINCORDER(dd->sinc_order);
0634 
0635     dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream));
0636     mr_val |= MCHP_PDMC_MR_CHUNK(dd->addr.maxburst);
0637     dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst);
0638 
0639     clk_prepare_enable(dd->gclk);
0640     dd->gclk_enabled = 1;
0641 
0642     snd_soc_component_update_bits(comp, MCHP_PDMC_MR,
0643                       MCHP_PDMC_MR_OSR_MASK |
0644                       MCHP_PDMC_MR_SINCORDER_MASK |
0645                       MCHP_PDMC_MR_SINC_OSR_MASK |
0646                       MCHP_PDMC_MR_CHUNK_MASK, mr_val);
0647 
0648     snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val);
0649 
0650     return 0;
0651 }
0652 
0653 static int mchp_pdmc_hw_free(struct snd_pcm_substream *substream,
0654                  struct snd_soc_dai *dai)
0655 {
0656     struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
0657 
0658     if (dd->gclk_enabled) {
0659         clk_disable_unprepare(dd->gclk);
0660         dd->gclk_enabled = 0;
0661     }
0662 
0663     return 0;
0664 }
0665 
0666 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream,
0667                  int cmd, struct snd_soc_dai *dai)
0668 {
0669     struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
0670     struct snd_soc_component *cpu = dai->component;
0671 #ifdef DEBUG
0672     u32 val;
0673 #endif
0674 
0675     switch (cmd) {
0676     case SNDRV_PCM_TRIGGER_START:
0677     case SNDRV_PCM_TRIGGER_RESUME:
0678     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0679         /* Enable overrun and underrun error interrupts */
0680         regmap_write(dd->regmap, MCHP_PDMC_IER,
0681                  MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
0682         snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
0683                           MCHP_PDMC_MR_PDMCEN_MASK,
0684                           dd->pdmcen);
0685         break;
0686     case SNDRV_PCM_TRIGGER_STOP:
0687     case SNDRV_PCM_TRIGGER_SUSPEND:
0688     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0689         /* Disable overrun and underrun error interrupts */
0690         regmap_write(dd->regmap, MCHP_PDMC_IDR,
0691                  MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
0692         snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
0693                           MCHP_PDMC_MR_PDMCEN_MASK, 0);
0694         break;
0695     default:
0696         return -EINVAL;
0697     }
0698 
0699 #ifdef DEBUG
0700     regmap_read(dd->regmap, MCHP_PDMC_MR, &val);
0701     dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val);
0702     regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val);
0703     dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val);
0704     regmap_read(dd->regmap, MCHP_PDMC_IMR, &val);
0705     dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val);
0706 #endif
0707 
0708     return 0;
0709 }
0710 
0711 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = {
0712     .set_fmt    = mchp_pdmc_set_fmt,
0713     .startup    = mchp_pdmc_startup,
0714     .shutdown   = mchp_pdmc_shutdown,
0715     .hw_params  = mchp_pdmc_hw_params,
0716     .hw_free    = mchp_pdmc_hw_free,
0717     .trigger    = mchp_pdmc_trigger,
0718 };
0719 
0720 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd)
0721 {
0722     struct mchp_pdmc_chmap *info;
0723     struct snd_kcontrol_new knew = {
0724         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0725         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
0726             SNDRV_CTL_ELEM_ACCESS_TLV_READ |
0727             SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK,
0728         .info = mchp_pdmc_chmap_ctl_info,
0729         .get = mchp_pdmc_chmap_ctl_get,
0730         .put = mchp_pdmc_chmap_ctl_put,
0731         .tlv.c = mchp_pdmc_chmap_ctl_tlv,
0732     };
0733     int err;
0734 
0735     if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl))
0736         return -EBUSY;
0737     info = kzalloc(sizeof(*info), GFP_KERNEL);
0738     if (!info)
0739         return -ENOMEM;
0740     info->pcm = pcm;
0741     info->dd = dd;
0742     info->chmap = mchp_pdmc_std_chmaps;
0743     knew.name = "Capture Channel Map";
0744     knew.device = pcm->device;
0745     knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count;
0746     info->kctl = snd_ctl_new1(&knew, info);
0747     if (!info->kctl) {
0748         kfree(info);
0749         return -ENOMEM;
0750     }
0751     info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free;
0752     err = snd_ctl_add(pcm->card, info->kctl);
0753     if (err < 0)
0754         return err;
0755     pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl;
0756     return 0;
0757 }
0758 
0759 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd,
0760                  struct snd_soc_dai *dai)
0761 {
0762     struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
0763     int ret;
0764 
0765     ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd);
0766     if (ret < 0) {
0767         dev_err(dd->dev, "failed to add channel map controls: %d\n", ret);
0768         return ret;
0769     }
0770 
0771     return 0;
0772 }
0773 
0774 static struct snd_soc_dai_driver mchp_pdmc_dai = {
0775     .probe  = mchp_pdmc_dai_probe,
0776     .capture = {
0777         .stream_name    = "Capture",
0778         .channels_min   = 1,
0779         .channels_max   = 4,
0780         .rate_min   = 8000,
0781         .rate_max   = 192000,
0782         .rates      = SNDRV_PCM_RATE_KNOT,
0783         .formats    = SNDRV_PCM_FMTBIT_S24_LE,
0784     },
0785     .ops = &mchp_pdmc_dai_ops,
0786     .pcm_new = &mchp_pdmc_pcm_new,
0787 };
0788 
0789 /* PDMC interrupt handler */
0790 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id)
0791 {
0792     struct mchp_pdmc *dd = (struct mchp_pdmc *)dev_id;
0793     u32 isr, msr, pending;
0794     irqreturn_t ret = IRQ_NONE;
0795 
0796     regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr);
0797     regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr);
0798 
0799     pending = isr & msr;
0800     dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n",
0801         MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending);
0802     if (!pending)
0803         return IRQ_NONE;
0804 
0805     if (pending & MCHP_PDMC_IR_RXUDR) {
0806         dev_warn(dd->dev, "underrun detected\n");
0807         regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR);
0808         ret = IRQ_HANDLED;
0809     }
0810     if (pending & MCHP_PDMC_IR_RXOVR) {
0811         dev_warn(dd->dev, "overrun detected\n");
0812         regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR);
0813         ret = IRQ_HANDLED;
0814     }
0815 
0816     return ret;
0817 }
0818 
0819 /* regmap configuration */
0820 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg)
0821 {
0822     switch (reg) {
0823     case MCHP_PDMC_MR:
0824     case MCHP_PDMC_CFGR:
0825     case MCHP_PDMC_IMR:
0826     case MCHP_PDMC_ISR:
0827     case MCHP_PDMC_VER:
0828         return true;
0829     default:
0830         return false;
0831     }
0832 }
0833 
0834 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg)
0835 {
0836     switch (reg) {
0837     case MCHP_PDMC_CR:
0838     case MCHP_PDMC_MR:
0839     case MCHP_PDMC_CFGR:
0840     case MCHP_PDMC_IER:
0841     case MCHP_PDMC_IDR:
0842         return true;
0843     default:
0844         return false;
0845     }
0846 }
0847 
0848 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg)
0849 {
0850     switch (reg) {
0851     case MCHP_PDMC_RHR:
0852     case MCHP_PDMC_ISR:
0853         return true;
0854     default:
0855         return false;
0856     }
0857 }
0858 
0859 static const struct regmap_config mchp_pdmc_regmap_config = {
0860     .reg_bits   = 32,
0861     .reg_stride = 4,
0862     .val_bits   = 32,
0863     .max_register   = MCHP_PDMC_VER,
0864     .readable_reg   = mchp_pdmc_readable_reg,
0865     .writeable_reg  = mchp_pdmc_writeable_reg,
0866     .precious_reg   = mchp_pdmc_precious_reg,
0867 };
0868 
0869 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
0870 {
0871     struct device_node *np = dd->dev->of_node;
0872     bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0};
0873     int i;
0874     int ret;
0875 
0876     if (!np) {
0877         dev_err(dd->dev, "device node not found\n");
0878         return -EINVAL;
0879     }
0880 
0881     dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos");
0882     if (dd->mic_no < 0) {
0883         dev_err(dd->dev, "failed to get microchip,mic-pos: %d",
0884             dd->mic_no);
0885         return dd->mic_no;
0886     }
0887     if (!dd->mic_no || dd->mic_no % 2 ||
0888         dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) {
0889         dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d",
0890             dd->mic_no);
0891         return -EINVAL;
0892     }
0893 
0894     dd->mic_no /= 2;
0895 
0896     dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no);
0897 
0898     /*
0899      * by default, we consider the order of microphones in
0900      * microchip,mic-pos to be the same with the channel mapping;
0901      * 1st microphone channel 0, 2nd microphone channel 1, etc.
0902      */
0903     for (i = 0; i < dd->mic_no; i++) {
0904         int ds;
0905         int edge;
0906 
0907         ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2,
0908                          &ds);
0909         if (ret) {
0910             dev_err(dd->dev,
0911                 "failed to get value no %d value from microchip,mic-pos: %d",
0912                 i * 2, ret);
0913             return ret;
0914         }
0915         if (ds >= MCHP_PDMC_DS_NO) {
0916             dev_err(dd->dev,
0917                 "invalid DS index in microchip,mic-pos array: %d",
0918                 ds);
0919             return -EINVAL;
0920         }
0921 
0922         ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1,
0923                          &edge);
0924         if (ret) {
0925             dev_err(dd->dev,
0926                 "failed to get value no %d value from microchip,mic-pos: %d",
0927                 i * 2 + 1, ret);
0928             return ret;
0929         }
0930 
0931         if (edge != MCHP_PDMC_CLK_POSITIVE &&
0932             edge != MCHP_PDMC_CLK_NEGATIVE) {
0933             dev_err(dd->dev,
0934                 "invalid edge in microchip,mic-pos array: %d", edge);
0935             return -EINVAL;
0936         }
0937         if (mic_ch[ds][edge]) {
0938             dev_err(dd->dev,
0939                 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array",
0940                 ds, edge);
0941             return -EINVAL;
0942         }
0943         mic_ch[ds][edge] = true;
0944         dd->channel_mic_map[i].ds_pos = ds;
0945         dd->channel_mic_map[i].clk_edge = edge;
0946     }
0947 
0948     return 0;
0949 }
0950 
0951 /* used to clean the channel index found on RHR's MSB */
0952 static int mchp_pdmc_process(struct snd_pcm_substream *substream,
0953                  int channel, unsigned long hwoff,
0954                  void *buf, unsigned long bytes)
0955 {
0956     struct snd_pcm_runtime *runtime = substream->runtime;
0957     u8 *dma_ptr = runtime->dma_area + hwoff +
0958               channel * (runtime->dma_bytes / runtime->channels);
0959     u8 *dma_ptr_end = dma_ptr + bytes;
0960     unsigned int sample_size = samples_to_bytes(runtime, 1);
0961 
0962     for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size)
0963         *dma_ptr = 0;
0964 
0965     return 0;
0966 }
0967 
0968 static struct snd_dmaengine_pcm_config mchp_pdmc_config = {
0969     .process = mchp_pdmc_process,
0970     .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
0971 };
0972 
0973 static int mchp_pdmc_probe(struct platform_device *pdev)
0974 {
0975     struct device *dev = &pdev->dev;
0976     struct mchp_pdmc *dd;
0977     struct resource *res;
0978     void __iomem *io_base;
0979     u32 version;
0980     int irq;
0981     int ret;
0982 
0983     dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
0984     if (!dd)
0985         return -ENOMEM;
0986 
0987     dd->dev = &pdev->dev;
0988     ret = mchp_pdmc_dt_init(dd);
0989     if (ret < 0)
0990         return ret;
0991 
0992     irq = platform_get_irq(pdev, 0);
0993     if (irq < 0)
0994         return irq;
0995 
0996     dd->pclk = devm_clk_get(dev, "pclk");
0997     if (IS_ERR(dd->pclk)) {
0998         ret = PTR_ERR(dd->pclk);
0999         dev_err(dev, "failed to get peripheral clock: %d\n", ret);
1000         return ret;
1001     }
1002 
1003     dd->gclk = devm_clk_get(dev, "gclk");
1004     if (IS_ERR(dd->gclk)) {
1005         ret = PTR_ERR(dd->gclk);
1006         dev_err(dev, "failed to get GCK: %d\n", ret);
1007         return ret;
1008     }
1009 
1010     io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1011     if (IS_ERR(io_base)) {
1012         ret = PTR_ERR(io_base);
1013         dev_err(dev, "failed to remap register memory: %d\n", ret);
1014         return ret;
1015     }
1016 
1017     dd->regmap = devm_regmap_init_mmio(dev, io_base,
1018                        &mchp_pdmc_regmap_config);
1019     if (IS_ERR(dd->regmap)) {
1020         ret = PTR_ERR(dd->regmap);
1021         dev_err(dev, "failed to init register map: %d\n", ret);
1022         return ret;
1023     }
1024 
1025     ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0,
1026                    dev_name(&pdev->dev), (void *)dd);
1027     if (ret < 0) {
1028         dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
1029             irq, ret);
1030         return ret;
1031     }
1032 
1033     /* by default audio filter is enabled and the SINC Filter order
1034      * will be set to the recommended value, 3
1035      */
1036     dd->audio_filter_en = true;
1037     dd->sinc_order = 3;
1038 
1039     dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR;
1040     platform_set_drvdata(pdev, dd);
1041 
1042     /* register platform */
1043     ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0);
1044     if (ret) {
1045         dev_err(dev, "could not register platform: %d\n", ret);
1046         return ret;
1047     }
1048 
1049     ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component,
1050                           &mchp_pdmc_dai, 1);
1051     if (ret) {
1052         dev_err(dev, "could not register CPU DAI: %d\n", ret);
1053         return ret;
1054     }
1055 
1056     /* print IP version */
1057     regmap_read(dd->regmap, MCHP_PDMC_VER, &version);
1058     dev_info(dd->dev, "hw version: %#lx\n",
1059          version & MCHP_PDMC_VER_VERSION);
1060 
1061     return 0;
1062 }
1063 
1064 static const struct of_device_id mchp_pdmc_of_match[] = {
1065     {
1066         .compatible = "microchip,sama7g5-pdmc",
1067     }, {
1068         /* sentinel */
1069     }
1070 };
1071 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match);
1072 
1073 static struct platform_driver mchp_pdmc_driver = {
1074     .driver = {
1075         .name       = "mchp-pdmc",
1076         .of_match_table = of_match_ptr(mchp_pdmc_of_match),
1077         .pm     = &snd_soc_pm_ops,
1078     },
1079     .probe  = mchp_pdmc_probe,
1080 };
1081 module_platform_driver(mchp_pdmc_driver);
1082 
1083 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture");
1084 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
1085 MODULE_LICENSE("GPL v2");
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