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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Driver for Microchip I2S Multi-channel controller
0004 //
0005 // Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
0006 //
0007 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
0008 
0009 #include <linux/init.h>
0010 #include <linux/module.h>
0011 #include <linux/device.h>
0012 #include <linux/slab.h>
0013 
0014 #include <linux/delay.h>
0015 #include <linux/io.h>
0016 #include <linux/clk.h>
0017 #include <linux/mfd/syscon.h>
0018 #include <linux/lcm.h>
0019 #include <linux/of_device.h>
0020 
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/initval.h>
0025 #include <sound/soc.h>
0026 #include <sound/dmaengine_pcm.h>
0027 
0028 /*
0029  * ---- I2S Controller Register map ----
0030  */
0031 #define MCHP_I2SMCC_CR      0x0000  /* Control Register */
0032 #define MCHP_I2SMCC_MRA     0x0004  /* Mode Register A */
0033 #define MCHP_I2SMCC_MRB     0x0008  /* Mode Register B */
0034 #define MCHP_I2SMCC_SR      0x000C  /* Status Register */
0035 #define MCHP_I2SMCC_IERA    0x0010  /* Interrupt Enable Register A */
0036 #define MCHP_I2SMCC_IDRA    0x0014  /* Interrupt Disable Register A */
0037 #define MCHP_I2SMCC_IMRA    0x0018  /* Interrupt Mask Register A */
0038 #define MCHP_I2SMCC_ISRA    0X001C  /* Interrupt Status Register A */
0039 
0040 #define MCHP_I2SMCC_IERB    0x0020  /* Interrupt Enable Register B */
0041 #define MCHP_I2SMCC_IDRB    0x0024  /* Interrupt Disable Register B */
0042 #define MCHP_I2SMCC_IMRB    0x0028  /* Interrupt Mask Register B */
0043 #define MCHP_I2SMCC_ISRB    0X002C  /* Interrupt Status Register B */
0044 
0045 #define MCHP_I2SMCC_RHR     0x0030  /* Receiver Holding Register */
0046 #define MCHP_I2SMCC_THR     0x0034  /* Transmitter Holding Register */
0047 
0048 #define MCHP_I2SMCC_RHL0R   0x0040  /* Receiver Holding Left 0 Register */
0049 #define MCHP_I2SMCC_RHR0R   0x0044  /* Receiver Holding Right 0 Register */
0050 
0051 #define MCHP_I2SMCC_RHL1R   0x0048  /* Receiver Holding Left 1 Register */
0052 #define MCHP_I2SMCC_RHR1R   0x004C  /* Receiver Holding Right 1 Register */
0053 
0054 #define MCHP_I2SMCC_RHL2R   0x0050  /* Receiver Holding Left 2 Register */
0055 #define MCHP_I2SMCC_RHR2R   0x0054  /* Receiver Holding Right 2 Register */
0056 
0057 #define MCHP_I2SMCC_RHL3R   0x0058  /* Receiver Holding Left 3 Register */
0058 #define MCHP_I2SMCC_RHR3R   0x005C  /* Receiver Holding Right 3 Register */
0059 
0060 #define MCHP_I2SMCC_THL0R   0x0060  /* Transmitter Holding Left 0 Register */
0061 #define MCHP_I2SMCC_THR0R   0x0064  /* Transmitter Holding Right 0 Register */
0062 
0063 #define MCHP_I2SMCC_THL1R   0x0068  /* Transmitter Holding Left 1 Register */
0064 #define MCHP_I2SMCC_THR1R   0x006C  /* Transmitter Holding Right 1 Register */
0065 
0066 #define MCHP_I2SMCC_THL2R   0x0070  /* Transmitter Holding Left 2 Register */
0067 #define MCHP_I2SMCC_THR2R   0x0074  /* Transmitter Holding Right 2 Register */
0068 
0069 #define MCHP_I2SMCC_THL3R   0x0078  /* Transmitter Holding Left 3 Register */
0070 #define MCHP_I2SMCC_THR3R   0x007C  /* Transmitter Holding Right 3 Register */
0071 
0072 #define MCHP_I2SMCC_VERSION 0x00FC  /* Version Register */
0073 
0074 /*
0075  * ---- Control Register (Write-only) ----
0076  */
0077 #define MCHP_I2SMCC_CR_RXEN     BIT(0)  /* Receiver Enable */
0078 #define MCHP_I2SMCC_CR_RXDIS        BIT(1)  /* Receiver Disable */
0079 #define MCHP_I2SMCC_CR_CKEN     BIT(2)  /* Clock Enable */
0080 #define MCHP_I2SMCC_CR_CKDIS        BIT(3)  /* Clock Disable */
0081 #define MCHP_I2SMCC_CR_TXEN     BIT(4)  /* Transmitter Enable */
0082 #define MCHP_I2SMCC_CR_TXDIS        BIT(5)  /* Transmitter Disable */
0083 #define MCHP_I2SMCC_CR_SWRST        BIT(7)  /* Software Reset */
0084 
0085 /*
0086  * ---- Mode Register A (Read/Write) ----
0087  */
0088 #define MCHP_I2SMCC_MRA_MODE_MASK       GENMASK(0, 0)
0089 #define MCHP_I2SMCC_MRA_MODE_SLAVE      (0 << 0)
0090 #define MCHP_I2SMCC_MRA_MODE_MASTER     (1 << 0)
0091 
0092 #define MCHP_I2SMCC_MRA_DATALENGTH_MASK         GENMASK(3, 1)
0093 #define MCHP_I2SMCC_MRA_DATALENGTH_32_BITS      (0 << 1)
0094 #define MCHP_I2SMCC_MRA_DATALENGTH_24_BITS      (1 << 1)
0095 #define MCHP_I2SMCC_MRA_DATALENGTH_20_BITS      (2 << 1)
0096 #define MCHP_I2SMCC_MRA_DATALENGTH_18_BITS      (3 << 1)
0097 #define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS      (4 << 1)
0098 #define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS_COMPACT  (5 << 1)
0099 #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS       (6 << 1)
0100 #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT   (7 << 1)
0101 
0102 #define MCHP_I2SMCC_MRA_WIRECFG_MASK        GENMASK(5, 4)
0103 #define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin)    (((pin) << 4) & \
0104                          MCHP_I2SMCC_MRA_WIRECFG_MASK)
0105 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0 (0 << 4)
0106 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1 (1 << 4)
0107 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2 (2 << 4)
0108 #define MCHP_I2SMCC_MRA_WIRECFG_TDM_3       (3 << 4)
0109 
0110 #define MCHP_I2SMCC_MRA_FORMAT_MASK     GENMASK(7, 6)
0111 #define MCHP_I2SMCC_MRA_FORMAT_I2S      (0 << 6)
0112 #define MCHP_I2SMCC_MRA_FORMAT_LJ       (1 << 6) /* Left Justified */
0113 #define MCHP_I2SMCC_MRA_FORMAT_TDM      (2 << 6)
0114 #define MCHP_I2SMCC_MRA_FORMAT_TDMLJ        (3 << 6)
0115 
0116 /* Transmitter uses one DMA channel ... */
0117 /* Left audio samples duplicated to right audio channel */
0118 #define MCHP_I2SMCC_MRA_RXMONO          BIT(8)
0119 
0120 /* I2SDO output of I2SC is internally connected to I2SDI input */
0121 #define MCHP_I2SMCC_MRA_RXLOOP          BIT(9)
0122 
0123 /* Receiver uses one DMA channel ... */
0124 /* Left audio samples duplicated to right audio channel */
0125 #define MCHP_I2SMCC_MRA_TXMONO          BIT(10)
0126 
0127 /* x sample transmitted when underrun */
0128 #define MCHP_I2SMCC_MRA_TXSAME_ZERO     (0 << 11) /* Zero sample */
0129 #define MCHP_I2SMCC_MRA_TXSAME_PREVIOUS     (1 << 11) /* Previous sample */
0130 
0131 /* select between peripheral clock and generated clock */
0132 #define MCHP_I2SMCC_MRA_SRCCLK_PCLK     (0 << 12)
0133 #define MCHP_I2SMCC_MRA_SRCCLK_GCLK     (1 << 12)
0134 
0135 /* Number of TDM Channels - 1 */
0136 #define MCHP_I2SMCC_MRA_NBCHAN_MASK     GENMASK(15, 13)
0137 #define MCHP_I2SMCC_MRA_NBCHAN(ch) \
0138     ((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)
0139 
0140 /* Selected Clock to I2SMCC Master Clock ratio */
0141 #define MCHP_I2SMCC_MRA_IMCKDIV_MASK        GENMASK(21, 16)
0142 #define MCHP_I2SMCC_MRA_IMCKDIV(div) \
0143     (((div) << 16) & MCHP_I2SMCC_MRA_IMCKDIV_MASK)
0144 
0145 /* TDM Frame Synchronization */
0146 #define MCHP_I2SMCC_MRA_TDMFS_MASK      GENMASK(23, 22)
0147 #define MCHP_I2SMCC_MRA_TDMFS_SLOT      (0 << 22)
0148 #define MCHP_I2SMCC_MRA_TDMFS_HALF      (1 << 22)
0149 #define MCHP_I2SMCC_MRA_TDMFS_BIT       (2 << 22)
0150 
0151 /* Selected Clock to I2SMC Serial Clock ratio */
0152 #define MCHP_I2SMCC_MRA_ISCKDIV_MASK        GENMASK(29, 24)
0153 #define MCHP_I2SMCC_MRA_ISCKDIV(div) \
0154     (((div) << 24) & MCHP_I2SMCC_MRA_ISCKDIV_MASK)
0155 
0156 /* Master Clock mode */
0157 #define MCHP_I2SMCC_MRA_IMCKMODE_MASK       GENMASK(30, 30)
0158 /* 0: No master clock generated*/
0159 #define MCHP_I2SMCC_MRA_IMCKMODE_NONE       (0 << 30)
0160 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
0161 #define MCHP_I2SMCC_MRA_IMCKMODE_GEN        (1 << 30)
0162 
0163 /* Slot Width */
0164 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
0165 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
0166 #define MCHP_I2SMCC_MRA_IWS         BIT(31)
0167 
0168 /*
0169  * ---- Mode Register B (Read/Write) ----
0170  */
0171 /* all enabled I2S left channels are filled first, then I2S right channels */
0172 #define MCHP_I2SMCC_MRB_CRAMODE_LEFT_FIRST  (0 << 0)
0173 /*
0174  * an enabled I2S left channel is filled, then the corresponding right
0175  * channel, until all channels are filled
0176  */
0177 #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR     (1 << 0)
0178 
0179 #define MCHP_I2SMCC_MRB_FIFOEN          BIT(4)
0180 
0181 #define MCHP_I2SMCC_MRB_DMACHUNK_MASK       GENMASK(9, 8)
0182 #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \
0183     (((fls(no_words) - 1) << 8) & MCHP_I2SMCC_MRB_DMACHUNK_MASK)
0184 
0185 #define MCHP_I2SMCC_MRB_CLKSEL_MASK     GENMASK(16, 16)
0186 #define MCHP_I2SMCC_MRB_CLKSEL_EXT      (0 << 16)
0187 #define MCHP_I2SMCC_MRB_CLKSEL_INT      (1 << 16)
0188 
0189 /*
0190  * ---- Status Registers (Read-only) ----
0191  */
0192 #define MCHP_I2SMCC_SR_RXEN     BIT(0)  /* Receiver Enabled */
0193 #define MCHP_I2SMCC_SR_TXEN     BIT(4)  /* Transmitter Enabled */
0194 
0195 /*
0196  * ---- Interrupt Enable/Disable/Mask/Status Registers A ----
0197  */
0198 #define MCHP_I2SMCC_INT_TXRDY_MASK(ch)      GENMASK((ch) - 1, 0)
0199 #define MCHP_I2SMCC_INT_TXRDYCH(ch)     BIT(ch)
0200 #define MCHP_I2SMCC_INT_TXUNF_MASK(ch)      GENMASK((ch) + 7, 8)
0201 #define MCHP_I2SMCC_INT_TXUNFCH(ch)     BIT((ch) + 8)
0202 #define MCHP_I2SMCC_INT_RXRDY_MASK(ch)      GENMASK((ch) + 15, 16)
0203 #define MCHP_I2SMCC_INT_RXRDYCH(ch)     BIT((ch) + 16)
0204 #define MCHP_I2SMCC_INT_RXOVF_MASK(ch)      GENMASK((ch) + 23, 24)
0205 #define MCHP_I2SMCC_INT_RXOVFCH(ch)     BIT((ch) + 24)
0206 
0207 /*
0208  * ---- Interrupt Enable/Disable/Mask/Status Registers B ----
0209  */
0210 #define MCHP_I2SMCC_INT_WERR            BIT(0)
0211 #define MCHP_I2SMCC_INT_TXFFRDY         BIT(8)
0212 #define MCHP_I2SMCC_INT_TXFFEMP         BIT(9)
0213 #define MCHP_I2SMCC_INT_RXFFRDY         BIT(12)
0214 #define MCHP_I2SMCC_INT_RXFFFUL         BIT(13)
0215 
0216 /*
0217  * ---- Version Register (Read-only) ----
0218  */
0219 #define MCHP_I2SMCC_VERSION_MASK        GENMASK(11, 0)
0220 
0221 #define MCHP_I2SMCC_MAX_CHANNELS        8
0222 #define MCHP_I2MCC_TDM_SLOT_WIDTH       32
0223 
0224 static const struct regmap_config mchp_i2s_mcc_regmap_config = {
0225     .reg_bits = 32,
0226     .reg_stride = 4,
0227     .val_bits = 32,
0228     .max_register = MCHP_I2SMCC_VERSION,
0229 };
0230 
0231 struct mchp_i2s_mcc_soc_data {
0232     unsigned int    data_pin_pair_num;
0233     bool        has_fifo;
0234 };
0235 
0236 struct mchp_i2s_mcc_dev {
0237     struct wait_queue_head          wq_txrdy;
0238     struct wait_queue_head          wq_rxrdy;
0239     struct device               *dev;
0240     struct regmap               *regmap;
0241     struct clk              *pclk;
0242     struct clk              *gclk;
0243     const struct mchp_i2s_mcc_soc_data  *soc;
0244     struct snd_dmaengine_dai_dma_data   playback;
0245     struct snd_dmaengine_dai_dma_data   capture;
0246     unsigned int                fmt;
0247     unsigned int                sysclk;
0248     unsigned int                frame_length;
0249     int                 tdm_slots;
0250     int                 channels;
0251     u8                  tdm_data_pair;
0252     unsigned int                gclk_use:1;
0253     unsigned int                gclk_running:1;
0254     unsigned int                tx_rdy:1;
0255     unsigned int                rx_rdy:1;
0256 };
0257 
0258 static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
0259 {
0260     struct mchp_i2s_mcc_dev *dev = dev_id;
0261     u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0;
0262     irqreturn_t ret = IRQ_NONE;
0263 
0264     regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
0265     regmap_read(dev->regmap, MCHP_I2SMCC_ISRA, &sra);
0266     pendinga = imra & sra;
0267 
0268     regmap_read(dev->regmap, MCHP_I2SMCC_IMRB, &imrb);
0269     regmap_read(dev->regmap, MCHP_I2SMCC_ISRB, &srb);
0270     pendingb = imrb & srb;
0271 
0272     if (!pendinga && !pendingb)
0273         return IRQ_NONE;
0274 
0275     /*
0276      * Tx/Rx ready interrupts are enabled when stopping only, to assure
0277      * availability and to disable clocks if necessary
0278      */
0279     if (dev->soc->has_fifo) {
0280         idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY |
0281                     MCHP_I2SMCC_INT_RXFFRDY);
0282     } else {
0283         idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
0284                     MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
0285     }
0286     if (idra || idrb)
0287         ret = IRQ_HANDLED;
0288 
0289     if ((!dev->soc->has_fifo &&
0290          (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
0291          (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
0292          (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) ||
0293         (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) {
0294         dev->tx_rdy = 1;
0295         wake_up_interruptible(&dev->wq_txrdy);
0296     }
0297     if ((!dev->soc->has_fifo &&
0298          (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
0299          (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
0300          (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) ||
0301         (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) {
0302         dev->rx_rdy = 1;
0303         wake_up_interruptible(&dev->wq_rxrdy);
0304     }
0305     if (dev->soc->has_fifo)
0306         regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb);
0307     else
0308         regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
0309 
0310     return ret;
0311 }
0312 
0313 static int mchp_i2s_mcc_set_sysclk(struct snd_soc_dai *dai,
0314                    int clk_id, unsigned int freq, int dir)
0315 {
0316     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0317 
0318     dev_dbg(dev->dev, "%s() clk_id=%d freq=%u dir=%d\n",
0319         __func__, clk_id, freq, dir);
0320 
0321     /* We do not need SYSCLK */
0322     if (dir == SND_SOC_CLOCK_IN)
0323         return 0;
0324 
0325     dev->sysclk = freq;
0326 
0327     return 0;
0328 }
0329 
0330 static int mchp_i2s_mcc_set_bclk_ratio(struct snd_soc_dai *dai,
0331                        unsigned int ratio)
0332 {
0333     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0334 
0335     dev_dbg(dev->dev, "%s() ratio=%u\n", __func__, ratio);
0336 
0337     dev->frame_length = ratio;
0338 
0339     return 0;
0340 }
0341 
0342 static int mchp_i2s_mcc_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0343 {
0344     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0345 
0346     dev_dbg(dev->dev, "%s() fmt=%#x\n", __func__, fmt);
0347 
0348     /* We don't support any kind of clock inversion */
0349     if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
0350         return -EINVAL;
0351 
0352     /* We can't generate only FSYNC */
0353     if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == SND_SOC_DAIFMT_BC_FP)
0354         return -EINVAL;
0355 
0356     /* We can only reconfigure the IP when it's stopped */
0357     if (fmt & SND_SOC_DAIFMT_CONT)
0358         return -EINVAL;
0359 
0360     dev->fmt = fmt;
0361 
0362     return 0;
0363 }
0364 
0365 static int mchp_i2s_mcc_set_dai_tdm_slot(struct snd_soc_dai *dai,
0366                      unsigned int tx_mask,
0367                      unsigned int rx_mask,
0368                      int slots, int slot_width)
0369 {
0370     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0371 
0372     dev_dbg(dev->dev,
0373         "%s() tx_mask=0x%08x rx_mask=0x%08x slots=%d width=%d\n",
0374         __func__, tx_mask, rx_mask, slots, slot_width);
0375 
0376     if (slots < 0 || slots > MCHP_I2SMCC_MAX_CHANNELS ||
0377         slot_width != MCHP_I2MCC_TDM_SLOT_WIDTH)
0378         return -EINVAL;
0379 
0380     if (slots) {
0381         /* We do not support daisy chain */
0382         if (rx_mask != GENMASK(slots - 1, 0) ||
0383             rx_mask != tx_mask)
0384             return -EINVAL;
0385     }
0386 
0387     dev->tdm_slots = slots;
0388     dev->frame_length = slots * MCHP_I2MCC_TDM_SLOT_WIDTH;
0389 
0390     return 0;
0391 }
0392 
0393 static int mchp_i2s_mcc_clk_get_rate_diff(struct clk *clk,
0394                       unsigned long rate,
0395                       struct clk **best_clk,
0396                       unsigned long *best_rate,
0397                       unsigned long *best_diff_rate)
0398 {
0399     long round_rate;
0400     unsigned int diff_rate;
0401 
0402     round_rate = clk_round_rate(clk, rate);
0403     if (round_rate < 0)
0404         return (int)round_rate;
0405 
0406     diff_rate = abs(rate - round_rate);
0407     if (diff_rate < *best_diff_rate) {
0408         *best_clk = clk;
0409         *best_diff_rate = diff_rate;
0410         *best_rate = rate;
0411     }
0412 
0413     return 0;
0414 }
0415 
0416 static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev,
0417                     unsigned int bclk, unsigned int *mra,
0418                     unsigned long *best_rate)
0419 {
0420     unsigned long clk_rate;
0421     unsigned long lcm_rate;
0422     unsigned long best_diff_rate = ~0;
0423     unsigned int sysclk;
0424     struct clk *best_clk = NULL;
0425     int ret;
0426 
0427     /* For code simplification */
0428     if (!dev->sysclk)
0429         sysclk = bclk;
0430     else
0431         sysclk = dev->sysclk;
0432 
0433     /*
0434      * MCLK is Selected CLK / (2 * IMCKDIV),
0435      * BCLK is Selected CLK / (2 * ISCKDIV);
0436      * if IMCKDIV or ISCKDIV are 0, MCLK or BCLK = Selected CLK
0437      */
0438     lcm_rate = lcm(sysclk, bclk);
0439     if ((lcm_rate / sysclk % 2 == 1 && lcm_rate / sysclk > 2) ||
0440         (lcm_rate / bclk % 2 == 1 && lcm_rate / bclk > 2))
0441         lcm_rate *= 2;
0442 
0443     for (clk_rate = lcm_rate;
0444          (clk_rate == sysclk || clk_rate / (sysclk * 2) <= GENMASK(5, 0)) &&
0445          (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0));
0446          clk_rate += lcm_rate) {
0447         ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate,
0448                              &best_clk, best_rate,
0449                              &best_diff_rate);
0450         if (ret) {
0451             dev_err(dev->dev, "gclk error for rate %lu: %d",
0452                 clk_rate, ret);
0453         } else {
0454             if (!best_diff_rate) {
0455                 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n",
0456                     clk_rate);
0457                 break;
0458             }
0459         }
0460 
0461         ret = mchp_i2s_mcc_clk_get_rate_diff(dev->pclk, clk_rate,
0462                              &best_clk, best_rate,
0463                              &best_diff_rate);
0464         if (ret) {
0465             dev_err(dev->dev, "pclk error for rate %lu: %d",
0466                 clk_rate, ret);
0467         } else {
0468             if (!best_diff_rate) {
0469                 dev_dbg(dev->dev, "found perfect rate on pclk: %lu\n",
0470                     clk_rate);
0471                 break;
0472             }
0473         }
0474     }
0475 
0476     /* check if clocks returned only errors */
0477     if (!best_clk) {
0478         dev_err(dev->dev, "unable to change rate to clocks\n");
0479         return -EINVAL;
0480     }
0481 
0482     dev_dbg(dev->dev, "source CLK is %s with rate %lu, diff %lu\n",
0483         best_clk == dev->pclk ? "pclk" : "gclk",
0484         *best_rate, best_diff_rate);
0485 
0486     /* Configure divisors */
0487     if (dev->sysclk)
0488         *mra |= MCHP_I2SMCC_MRA_IMCKDIV(*best_rate / (2 * sysclk));
0489     *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk));
0490 
0491     if (best_clk == dev->gclk)
0492         *mra |= MCHP_I2SMCC_MRA_SRCCLK_GCLK;
0493     else
0494         *mra |= MCHP_I2SMCC_MRA_SRCCLK_PCLK;
0495 
0496     return 0;
0497 }
0498 
0499 static int mchp_i2s_mcc_is_running(struct mchp_i2s_mcc_dev *dev)
0500 {
0501     u32 sr;
0502 
0503     regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
0504     return !!(sr & (MCHP_I2SMCC_SR_TXEN | MCHP_I2SMCC_SR_RXEN));
0505 }
0506 
0507 static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
0508                   struct snd_pcm_hw_params *params,
0509                   struct snd_soc_dai *dai)
0510 {
0511     unsigned long rate = 0;
0512     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0513     u32 mra = 0;
0514     u32 mrb = 0;
0515     unsigned int channels = params_channels(params);
0516     unsigned int frame_length = dev->frame_length;
0517     unsigned int bclk_rate;
0518     int set_divs = 0;
0519     int ret;
0520     bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0521 
0522     dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
0523         __func__, params_rate(params), params_format(params),
0524         params_width(params), params_channels(params));
0525 
0526     switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0527     case SND_SOC_DAIFMT_I2S:
0528         if (dev->tdm_slots) {
0529             dev_err(dev->dev, "I2S with TDM is not supported\n");
0530             return -EINVAL;
0531         }
0532         mra |= MCHP_I2SMCC_MRA_FORMAT_I2S;
0533         break;
0534     case SND_SOC_DAIFMT_LEFT_J:
0535         if (dev->tdm_slots) {
0536             dev_err(dev->dev, "Left-Justified with TDM is not supported\n");
0537             return -EINVAL;
0538         }
0539         mra |= MCHP_I2SMCC_MRA_FORMAT_LJ;
0540         break;
0541     case SND_SOC_DAIFMT_DSP_A:
0542         mra |= MCHP_I2SMCC_MRA_FORMAT_TDM;
0543         break;
0544     default:
0545         dev_err(dev->dev, "unsupported bus format\n");
0546         return -EINVAL;
0547     }
0548 
0549     switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0550     case SND_SOC_DAIFMT_BP_FP:
0551         /* cpu is BCLK and LRC master */
0552         mra |= MCHP_I2SMCC_MRA_MODE_MASTER;
0553         if (dev->sysclk)
0554             mra |= MCHP_I2SMCC_MRA_IMCKMODE_GEN;
0555         set_divs = 1;
0556         break;
0557     case SND_SOC_DAIFMT_BP_FC:
0558         /* cpu is BCLK master */
0559         mrb |= MCHP_I2SMCC_MRB_CLKSEL_INT;
0560         set_divs = 1;
0561         fallthrough;
0562     case SND_SOC_DAIFMT_BC_FC:
0563         /* cpu is slave */
0564         mra |= MCHP_I2SMCC_MRA_MODE_SLAVE;
0565         if (dev->sysclk)
0566             dev_warn(dev->dev, "Unable to generate MCLK in Slave mode\n");
0567         break;
0568     default:
0569         dev_err(dev->dev, "unsupported master/slave mode\n");
0570         return -EINVAL;
0571     }
0572 
0573     if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
0574         /* for I2S and LEFT_J one pin is needed for every 2 channels */
0575         if (channels > dev->soc->data_pin_pair_num * 2) {
0576             dev_err(dev->dev,
0577                 "unsupported number of audio channels: %d\n",
0578                 channels);
0579             return -EINVAL;
0580         }
0581 
0582         /* enable for interleaved format */
0583         mrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR;
0584 
0585         switch (channels) {
0586         case 1:
0587             if (is_playback)
0588                 mra |= MCHP_I2SMCC_MRA_TXMONO;
0589             else
0590                 mra |= MCHP_I2SMCC_MRA_RXMONO;
0591             break;
0592         case 2:
0593             break;
0594         case 4:
0595             mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1;
0596             break;
0597         case 8:
0598             mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2;
0599             break;
0600         default:
0601             dev_err(dev->dev, "unsupported number of audio channels\n");
0602             return -EINVAL;
0603         }
0604 
0605         if (!frame_length)
0606             frame_length = 2 * params_physical_width(params);
0607     } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {
0608         mra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair);
0609 
0610         if (dev->tdm_slots) {
0611             if (channels % 2 && channels * 2 <= dev->tdm_slots) {
0612                 /*
0613                  * Duplicate data for even-numbered channels
0614                  * to odd-numbered channels
0615                  */
0616                 if (is_playback)
0617                     mra |= MCHP_I2SMCC_MRA_TXMONO;
0618                 else
0619                     mra |= MCHP_I2SMCC_MRA_RXMONO;
0620             }
0621             channels = dev->tdm_slots;
0622         }
0623 
0624         mra |= MCHP_I2SMCC_MRA_NBCHAN(channels);
0625         if (!frame_length)
0626             frame_length = channels * MCHP_I2MCC_TDM_SLOT_WIDTH;
0627     }
0628 
0629     /*
0630      * We must have the same burst size configured
0631      * in the DMA transfer and in out IP
0632      */
0633     mrb |= MCHP_I2SMCC_MRB_DMACHUNK(channels);
0634     if (is_playback)
0635         dev->playback.maxburst = 1 << (fls(channels) - 1);
0636     else
0637         dev->capture.maxburst = 1 << (fls(channels) - 1);
0638 
0639     switch (params_format(params)) {
0640     case SNDRV_PCM_FORMAT_S8:
0641         mra |= MCHP_I2SMCC_MRA_DATALENGTH_8_BITS;
0642         break;
0643     case SNDRV_PCM_FORMAT_S16_LE:
0644         mra |= MCHP_I2SMCC_MRA_DATALENGTH_16_BITS;
0645         break;
0646     case SNDRV_PCM_FORMAT_S18_3LE:
0647         mra |= MCHP_I2SMCC_MRA_DATALENGTH_18_BITS |
0648                MCHP_I2SMCC_MRA_IWS;
0649         break;
0650     case SNDRV_PCM_FORMAT_S20_3LE:
0651         mra |= MCHP_I2SMCC_MRA_DATALENGTH_20_BITS |
0652                MCHP_I2SMCC_MRA_IWS;
0653         break;
0654     case SNDRV_PCM_FORMAT_S24_3LE:
0655         mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS |
0656                MCHP_I2SMCC_MRA_IWS;
0657         break;
0658     case SNDRV_PCM_FORMAT_S24_LE:
0659         mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS;
0660         break;
0661     case SNDRV_PCM_FORMAT_S32_LE:
0662         mra |= MCHP_I2SMCC_MRA_DATALENGTH_32_BITS;
0663         break;
0664     default:
0665         dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
0666         return -EINVAL;
0667     }
0668 
0669     if (set_divs) {
0670         bclk_rate = frame_length * params_rate(params);
0671         ret = mchp_i2s_mcc_config_divs(dev, bclk_rate, &mra,
0672                            &rate);
0673         if (ret) {
0674             dev_err(dev->dev,
0675                 "unable to configure the divisors: %d\n", ret);
0676             return ret;
0677         }
0678     }
0679 
0680     /* enable FIFO if available */
0681     if (dev->soc->has_fifo)
0682         mrb |= MCHP_I2SMCC_MRB_FIFOEN;
0683 
0684     /*
0685      * If we are already running, the wanted setup must be
0686      * the same with the one that's currently ongoing
0687      */
0688     if (mchp_i2s_mcc_is_running(dev)) {
0689         u32 mra_cur;
0690         u32 mrb_cur;
0691 
0692         regmap_read(dev->regmap, MCHP_I2SMCC_MRA, &mra_cur);
0693         regmap_read(dev->regmap, MCHP_I2SMCC_MRB, &mrb_cur);
0694         if (mra != mra_cur || mrb != mrb_cur)
0695             return -EINVAL;
0696 
0697         return 0;
0698     }
0699 
0700     if (mra & MCHP_I2SMCC_MRA_SRCCLK_GCLK && !dev->gclk_use) {
0701         /* set the rate */
0702         ret = clk_set_rate(dev->gclk, rate);
0703         if (ret) {
0704             dev_err(dev->dev,
0705                 "unable to set rate %lu to GCLK: %d\n",
0706                 rate, ret);
0707             return ret;
0708         }
0709 
0710         ret = clk_prepare(dev->gclk);
0711         if (ret < 0) {
0712             dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret);
0713             return ret;
0714         }
0715         dev->gclk_use = 1;
0716     }
0717 
0718     /* Save the number of channels to know what interrupts to enable */
0719     dev->channels = channels;
0720 
0721     ret = regmap_write(dev->regmap, MCHP_I2SMCC_MRA, mra);
0722     if (ret < 0) {
0723         if (dev->gclk_use) {
0724             clk_unprepare(dev->gclk);
0725             dev->gclk_use = 0;
0726         }
0727         return ret;
0728     }
0729     return regmap_write(dev->regmap, MCHP_I2SMCC_MRB, mrb);
0730 }
0731 
0732 static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream,
0733                 struct snd_soc_dai *dai)
0734 {
0735     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0736     bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0737     long err;
0738 
0739     if (is_playback) {
0740         err = wait_event_interruptible_timeout(dev->wq_txrdy,
0741                                dev->tx_rdy,
0742                                msecs_to_jiffies(500));
0743         if (err == 0) {
0744             dev_warn_once(dev->dev,
0745                       "Timeout waiting for Tx ready\n");
0746             if (dev->soc->has_fifo)
0747                 regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
0748                          MCHP_I2SMCC_INT_TXFFRDY);
0749             else
0750                 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
0751                          MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
0752 
0753             dev->tx_rdy = 1;
0754         }
0755     } else {
0756         err = wait_event_interruptible_timeout(dev->wq_rxrdy,
0757                                dev->rx_rdy,
0758                                msecs_to_jiffies(500));
0759         if (err == 0) {
0760             dev_warn_once(dev->dev,
0761                       "Timeout waiting for Rx ready\n");
0762             if (dev->soc->has_fifo)
0763                 regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
0764                          MCHP_I2SMCC_INT_RXFFRDY);
0765             else
0766                 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
0767                          MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
0768             dev->rx_rdy = 1;
0769         }
0770     }
0771 
0772     if (!mchp_i2s_mcc_is_running(dev)) {
0773         regmap_write(dev->regmap, MCHP_I2SMCC_CR, MCHP_I2SMCC_CR_CKDIS);
0774 
0775         if (dev->gclk_running) {
0776             clk_disable(dev->gclk);
0777             dev->gclk_running = 0;
0778         }
0779         if (dev->gclk_use) {
0780             clk_unprepare(dev->gclk);
0781             dev->gclk_use = 0;
0782         }
0783     }
0784 
0785     return 0;
0786 }
0787 
0788 static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,
0789                 struct snd_soc_dai *dai)
0790 {
0791     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0792     bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0793     u32 cr = 0;
0794     u32 iera = 0, ierb = 0;
0795     u32 sr;
0796     int err;
0797 
0798     switch (cmd) {
0799     case SNDRV_PCM_TRIGGER_START:
0800     case SNDRV_PCM_TRIGGER_RESUME:
0801     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0802         if (is_playback)
0803             cr = MCHP_I2SMCC_CR_TXEN | MCHP_I2SMCC_CR_CKEN;
0804         else
0805             cr = MCHP_I2SMCC_CR_RXEN | MCHP_I2SMCC_CR_CKEN;
0806         break;
0807     case SNDRV_PCM_TRIGGER_STOP:
0808     case SNDRV_PCM_TRIGGER_SUSPEND:
0809     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0810         regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
0811         if (is_playback && (sr & MCHP_I2SMCC_SR_TXEN)) {
0812             cr = MCHP_I2SMCC_CR_TXDIS;
0813             dev->tx_rdy = 0;
0814             /*
0815              * Enable Tx Ready interrupts on all channels
0816              * to assure all data is sent
0817              */
0818             if (dev->soc->has_fifo)
0819                 ierb = MCHP_I2SMCC_INT_TXFFRDY;
0820             else
0821                 iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
0822         } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {
0823             cr = MCHP_I2SMCC_CR_RXDIS;
0824             dev->rx_rdy = 0;
0825             /*
0826              * Enable Rx Ready interrupts on all channels
0827              * to assure all data is received
0828              */
0829             if (dev->soc->has_fifo)
0830                 ierb = MCHP_I2SMCC_INT_RXFFRDY;
0831             else
0832                 iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
0833         }
0834         break;
0835     default:
0836         return -EINVAL;
0837     }
0838 
0839     if ((cr & MCHP_I2SMCC_CR_CKEN) && dev->gclk_use &&
0840         !dev->gclk_running) {
0841         err = clk_enable(dev->gclk);
0842         if (err) {
0843             dev_err_once(dev->dev, "failed to enable GCLK: %d\n",
0844                      err);
0845         } else {
0846             dev->gclk_running = 1;
0847         }
0848     }
0849 
0850     if (dev->soc->has_fifo)
0851         regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb);
0852     else
0853         regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
0854     regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);
0855 
0856     return 0;
0857 }
0858 
0859 static int mchp_i2s_mcc_startup(struct snd_pcm_substream *substream,
0860                 struct snd_soc_dai *dai)
0861 {
0862     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0863 
0864     /* Software reset the IP if it's not running */
0865     if (!mchp_i2s_mcc_is_running(dev)) {
0866         return regmap_write(dev->regmap, MCHP_I2SMCC_CR,
0867                     MCHP_I2SMCC_CR_SWRST);
0868     }
0869 
0870     return 0;
0871 }
0872 
0873 static const struct snd_soc_dai_ops mchp_i2s_mcc_dai_ops = {
0874     .set_sysclk = mchp_i2s_mcc_set_sysclk,
0875     .set_bclk_ratio = mchp_i2s_mcc_set_bclk_ratio,
0876     .startup    = mchp_i2s_mcc_startup,
0877     .trigger    = mchp_i2s_mcc_trigger,
0878     .hw_params  = mchp_i2s_mcc_hw_params,
0879     .hw_free    = mchp_i2s_mcc_hw_free,
0880     .set_fmt    = mchp_i2s_mcc_set_dai_fmt,
0881     .set_tdm_slot   = mchp_i2s_mcc_set_dai_tdm_slot,
0882 };
0883 
0884 static int mchp_i2s_mcc_dai_probe(struct snd_soc_dai *dai)
0885 {
0886     struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
0887 
0888     init_waitqueue_head(&dev->wq_txrdy);
0889     init_waitqueue_head(&dev->wq_rxrdy);
0890     dev->tx_rdy = 1;
0891     dev->rx_rdy = 1;
0892 
0893     snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
0894 
0895     return 0;
0896 }
0897 
0898 #define MCHP_I2SMCC_RATES              SNDRV_PCM_RATE_8000_192000
0899 
0900 #define MCHP_I2SMCC_FORMATS (SNDRV_PCM_FMTBIT_S8 |          \
0901                  SNDRV_PCM_FMTBIT_S16_LE |      \
0902                  SNDRV_PCM_FMTBIT_S18_3LE |     \
0903                  SNDRV_PCM_FMTBIT_S20_3LE |     \
0904                  SNDRV_PCM_FMTBIT_S24_3LE |     \
0905                  SNDRV_PCM_FMTBIT_S24_LE |      \
0906                  SNDRV_PCM_FMTBIT_S32_LE)
0907 
0908 static struct snd_soc_dai_driver mchp_i2s_mcc_dai = {
0909     .probe  = mchp_i2s_mcc_dai_probe,
0910     .playback = {
0911         .stream_name = "I2SMCC-Playback",
0912         .channels_min = 1,
0913         .channels_max = 8,
0914         .rates = MCHP_I2SMCC_RATES,
0915         .formats = MCHP_I2SMCC_FORMATS,
0916     },
0917     .capture = {
0918         .stream_name = "I2SMCC-Capture",
0919         .channels_min = 1,
0920         .channels_max = 8,
0921         .rates = MCHP_I2SMCC_RATES,
0922         .formats = MCHP_I2SMCC_FORMATS,
0923     },
0924     .ops = &mchp_i2s_mcc_dai_ops,
0925     .symmetric_rate = 1,
0926     .symmetric_sample_bits = 1,
0927     .symmetric_channels = 1,
0928 };
0929 
0930 static const struct snd_soc_component_driver mchp_i2s_mcc_component = {
0931     .name           = "mchp-i2s-mcc",
0932     .legacy_dai_naming  = 1,
0933 };
0934 
0935 #ifdef CONFIG_OF
0936 static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = {
0937     .data_pin_pair_num = 1,
0938 };
0939 
0940 static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {
0941     .data_pin_pair_num = 4,
0942     .has_fifo = true,
0943 };
0944 
0945 static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
0946     {
0947         .compatible = "microchip,sam9x60-i2smcc",
0948         .data = &mchp_i2s_mcc_sam9x60,
0949     },
0950     {
0951         .compatible = "microchip,sama7g5-i2smcc",
0952         .data = &mchp_i2s_mcc_sama7g5,
0953     },
0954     { /* sentinel */ }
0955 };
0956 MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);
0957 #endif
0958 
0959 static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev,
0960                        struct mchp_i2s_mcc_dev *dev)
0961 {
0962     int err;
0963 
0964     if (!dev->soc) {
0965         dev_err(&pdev->dev, "failed to get soc data\n");
0966         return -ENODEV;
0967     }
0968 
0969     if (dev->soc->data_pin_pair_num == 1)
0970         return 0;
0971 
0972     err = of_property_read_u8(pdev->dev.of_node, "microchip,tdm-data-pair",
0973                   &dev->tdm_data_pair);
0974     if (err < 0 && err != -EINVAL) {
0975         dev_err(&pdev->dev,
0976             "bad property data for 'microchip,tdm-data-pair': %d",
0977             err);
0978         return err;
0979     }
0980     if (err == -EINVAL) {
0981         dev_info(&pdev->dev,
0982              "'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\n");
0983         dev->tdm_data_pair = 0;
0984     } else {
0985         if (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) {
0986             dev_err(&pdev->dev,
0987                 "invalid value for 'microchip,tdm-data-pair': %d\n",
0988                 dev->tdm_data_pair);
0989             return -EINVAL;
0990         }
0991         dev_dbg(&pdev->dev, "TMD format on DIN/DOUT %d pins\n",
0992             dev->tdm_data_pair);
0993     }
0994 
0995     return 0;
0996 }
0997 
0998 static int mchp_i2s_mcc_probe(struct platform_device *pdev)
0999 {
1000     struct mchp_i2s_mcc_dev *dev;
1001     struct resource *mem;
1002     struct regmap *regmap;
1003     void __iomem *base;
1004     u32 version;
1005     int irq;
1006     int err;
1007 
1008     dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1009     if (!dev)
1010         return -ENOMEM;
1011 
1012     base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
1013     if (IS_ERR(base))
1014         return PTR_ERR(base);
1015 
1016     regmap = devm_regmap_init_mmio(&pdev->dev, base,
1017                        &mchp_i2s_mcc_regmap_config);
1018     if (IS_ERR(regmap))
1019         return PTR_ERR(regmap);
1020 
1021     irq = platform_get_irq(pdev, 0);
1022     if (irq < 0)
1023         return irq;
1024 
1025     err = devm_request_irq(&pdev->dev, irq, mchp_i2s_mcc_interrupt, 0,
1026                    dev_name(&pdev->dev), dev);
1027     if (err)
1028         return err;
1029 
1030     dev->pclk = devm_clk_get(&pdev->dev, "pclk");
1031     if (IS_ERR(dev->pclk)) {
1032         err = PTR_ERR(dev->pclk);
1033         dev_err(&pdev->dev,
1034             "failed to get the peripheral clock: %d\n", err);
1035         return err;
1036     }
1037 
1038     /* Get the optional generated clock */
1039     dev->gclk = devm_clk_get(&pdev->dev, "gclk");
1040     if (IS_ERR(dev->gclk)) {
1041         if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
1042             return -EPROBE_DEFER;
1043         dev_warn(&pdev->dev,
1044              "generated clock not found: %d\n", err);
1045         dev->gclk = NULL;
1046     }
1047 
1048     dev->soc = of_device_get_match_data(&pdev->dev);
1049     err = mchp_i2s_mcc_soc_data_parse(pdev, dev);
1050     if (err < 0)
1051         return err;
1052 
1053     dev->dev = &pdev->dev;
1054     dev->regmap = regmap;
1055     platform_set_drvdata(pdev, dev);
1056 
1057     err = clk_prepare_enable(dev->pclk);
1058     if (err) {
1059         dev_err(&pdev->dev,
1060             "failed to enable the peripheral clock: %d\n", err);
1061         return err;
1062     }
1063 
1064     err = devm_snd_soc_register_component(&pdev->dev,
1065                           &mchp_i2s_mcc_component,
1066                           &mchp_i2s_mcc_dai, 1);
1067     if (err) {
1068         dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
1069         clk_disable_unprepare(dev->pclk);
1070         return err;
1071     }
1072 
1073     dev->playback.addr  = (dma_addr_t)mem->start + MCHP_I2SMCC_THR;
1074     dev->capture.addr   = (dma_addr_t)mem->start + MCHP_I2SMCC_RHR;
1075 
1076     err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1077     if (err) {
1078         dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
1079         clk_disable_unprepare(dev->pclk);
1080         return err;
1081     }
1082 
1083     /* Get IP version. */
1084     regmap_read(dev->regmap, MCHP_I2SMCC_VERSION, &version);
1085     dev_info(&pdev->dev, "hw version: %#lx\n",
1086          version & MCHP_I2SMCC_VERSION_MASK);
1087 
1088     return 0;
1089 }
1090 
1091 static int mchp_i2s_mcc_remove(struct platform_device *pdev)
1092 {
1093     struct mchp_i2s_mcc_dev *dev = platform_get_drvdata(pdev);
1094 
1095     clk_disable_unprepare(dev->pclk);
1096 
1097     return 0;
1098 }
1099 
1100 static struct platform_driver mchp_i2s_mcc_driver = {
1101     .driver     = {
1102         .name   = "mchp_i2s_mcc",
1103         .of_match_table = of_match_ptr(mchp_i2s_mcc_dt_ids),
1104     },
1105     .probe      = mchp_i2s_mcc_probe,
1106     .remove     = mchp_i2s_mcc_remove,
1107 };
1108 module_platform_driver(mchp_i2s_mcc_driver);
1109 
1110 MODULE_DESCRIPTION("Microchip I2S Multi-Channel Controller driver");
1111 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
1112 MODULE_LICENSE("GPL v2");
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