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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ATMEL_PDMIC_H_
0003 #define __ATMEL_PDMIC_H_
0004 
0005 #include <linux/bitops.h>
0006 
0007 #define PDMIC_CR    0x00000000
0008 
0009 #define PDMIC_CR_SWRST      0x1
0010 #define PDMIC_CR_SWRST_MASK BIT(0)
0011 #define PDMIC_CR_SWRST_SHIFT    (0)
0012 
0013 #define PDMIC_CR_ENPDM_DIS  0x0
0014 #define PDMIC_CR_ENPDM_EN   0x1
0015 #define PDMIC_CR_ENPDM_MASK BIT(4)
0016 #define PDMIC_CR_ENPDM_SHIFT    (4)
0017 
0018 #define PDMIC_MR    0x00000004
0019 
0020 #define PDMIC_MR_CLKS_PCK   0x0
0021 #define PDMIC_MR_CLKS_GCK   0x1
0022 #define PDMIC_MR_CLKS_MASK  BIT(4)
0023 #define PDMIC_MR_CLKS_SHIFT (4)
0024 
0025 #define PDMIC_MR_PRESCAL_MASK   GENMASK(14, 8)
0026 #define PDMIC_MR_PRESCAL_SHIFT  (8)
0027 
0028 #define PDMIC_CDR   0x00000014
0029 
0030 #define PDMIC_IER   0x00000018
0031 #define PDMIC_IER_OVRE          BIT(25)
0032 
0033 #define PDMIC_IDR   0x0000001c
0034 #define PDMIC_IDR_OVRE          BIT(25)
0035 
0036 #define PDMIC_IMR   0x00000020
0037 
0038 #define PDMIC_ISR   0x00000024
0039 #define PDMIC_ISR_OVRE          BIT(25)
0040 
0041 #define PDMIC_DSPR0 0x00000058
0042 
0043 #define PDMIC_DSPR0_HPFBYP_DIS      0x1
0044 #define PDMIC_DSPR0_HPFBYP_EN       0x0
0045 #define PDMIC_DSPR0_HPFBYP_MASK     BIT(1)
0046 #define PDMIC_DSPR0_HPFBYP_SHIFT    (1)
0047 
0048 #define PDMIC_DSPR0_SINBYP_DIS      0x1
0049 #define PDMIC_DSPR0_SINBYP_EN       0x0
0050 #define PDMIC_DSPR0_SINBYP_MASK     BIT(2)
0051 #define PDMIC_DSPR0_SINBYP_SHIFT    (2)
0052 
0053 #define PDMIC_DSPR0_SIZE_16_BITS    0x0
0054 #define PDMIC_DSPR0_SIZE_32_BITS    0x1
0055 #define PDMIC_DSPR0_SIZE_MASK       BIT(3)
0056 #define PDMIC_DSPR0_SIZE_SHIFT      (3)
0057 
0058 #define PDMIC_DSPR0_OSR_128     0x0
0059 #define PDMIC_DSPR0_OSR_64      0x1
0060 #define PDMIC_DSPR0_OSR_MASK        GENMASK(6, 4)
0061 #define PDMIC_DSPR0_OSR_SHIFT       (4)
0062 
0063 #define PDMIC_DSPR0_SCALE_MASK      GENMASK(11, 8)
0064 #define PDMIC_DSPR0_SCALE_SHIFT     (8)
0065 
0066 #define PDMIC_DSPR0_SHIFT_MASK      GENMASK(15, 12)
0067 #define PDMIC_DSPR0_SHIFT_SHIFT     (12)
0068 
0069 #define PDMIC_DSPR1 0x0000005c
0070 
0071 #define PDMIC_DSPR1_DGAIN_MASK      GENMASK(14, 0)
0072 #define PDMIC_DSPR1_DGAIN_SHIFT     (0)
0073 
0074 #define PDMIC_DSPR1_OFFSET_MASK     GENMASK(31, 16)
0075 #define PDMIC_DSPR1_OFFSET_SHIFT    (16)
0076 
0077 #define PDMIC_WPMR  0x000000e4
0078 
0079 #define PDMIC_WPSR  0x000000e8
0080 
0081 #endif