soc/atmel/atmel-i2s.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for Atmel I2S controller
0004  *
0005  * Copyright (C) 2015 Atmel Corporation
0006  *
0007  * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
0008  */
0009
0010 #include <linux/init.h>
0011 #include <linux/module.h>
0012 #include <linux/device.h>
0013 #include <linux/slab.h>
0014 #include <linux/delay.h>
0015 #include <linux/io.h>
0016 #include <linux/clk.h>
0017 #include <linux/mfd/syscon.h>
0018
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/initval.h>
0023 #include <sound/soc.h>
0024 #include <sound/dmaengine_pcm.h>
0025
0026 #define ATMEL_I2SC_MAX_TDM_CHANNELS 8
0027
0028 /*
0029  * ---- I2S Controller Register map ----
0030  */
0031 #define ATMEL_I2SC_CR       0x0000  /* Control Register */
0032 #define ATMEL_I2SC_MR       0x0004  /* Mode Register */
0033 #define ATMEL_I2SC_SR       0x0008  /* Status Register */
0034 #define ATMEL_I2SC_SCR      0x000c  /* Status Clear Register */
0035 #define ATMEL_I2SC_SSR      0x0010  /* Status Set Register */
0036 #define ATMEL_I2SC_IER      0x0014  /* Interrupt Enable Register */
0037 #define ATMEL_I2SC_IDR      0x0018  /* Interrupt Disable Register */
0038 #define ATMEL_I2SC_IMR      0x001c  /* Interrupt Mask Register */
0039 #define ATMEL_I2SC_RHR      0x0020  /* Receiver Holding Register */
0040 #define ATMEL_I2SC_THR      0x0024  /* Transmitter Holding Register */
0041 #define ATMEL_I2SC_VERSION  0x0028  /* Version Register */
0042
0043 /*
0044  * ---- Control Register (Write-only) ----
0045  */
0046 #define ATMEL_I2SC_CR_RXEN  BIT(0)  /* Receiver Enable */
0047 #define ATMEL_I2SC_CR_RXDIS BIT(1)  /* Receiver Disable */
0048 #define ATMEL_I2SC_CR_CKEN  BIT(2)  /* Clock Enable */
0049 #define ATMEL_I2SC_CR_CKDIS BIT(3)  /* Clock Disable */
0050 #define ATMEL_I2SC_CR_TXEN  BIT(4)  /* Transmitter Enable */
0051 #define ATMEL_I2SC_CR_TXDIS BIT(5)  /* Transmitter Disable */
0052 #define ATMEL_I2SC_CR_SWRST BIT(7)  /* Software Reset */
0053
0054 /*
0055  * ---- Mode Register (Read/Write) ----
0056  */
0057 #define ATMEL_I2SC_MR_MODE_MASK     GENMASK(0, 0)
0058 #define ATMEL_I2SC_MR_MODE_SLAVE    (0 << 0)
0059 #define ATMEL_I2SC_MR_MODE_MASTER   (1 << 0)
0060
0061 #define ATMEL_I2SC_MR_DATALENGTH_MASK       GENMASK(4, 2)
0062 #define ATMEL_I2SC_MR_DATALENGTH_32_BITS    (0 << 2)
0063 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS    (1 << 2)
0064 #define ATMEL_I2SC_MR_DATALENGTH_20_BITS    (2 << 2)
0065 #define ATMEL_I2SC_MR_DATALENGTH_18_BITS    (3 << 2)
0066 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS    (4 << 2)
0067 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT    (5 << 2)
0068 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS     (6 << 2)
0069 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2)
0070
0071 #define ATMEL_I2SC_MR_FORMAT_MASK   GENMASK(7, 6)
0072 #define ATMEL_I2SC_MR_FORMAT_I2S    (0 << 6)
0073 #define ATMEL_I2SC_MR_FORMAT_LJ     (1 << 6)  /* Left Justified */
0074 #define ATMEL_I2SC_MR_FORMAT_TDM    (2 << 6)
0075 #define ATMEL_I2SC_MR_FORMAT_TDMLJ  (3 << 6)
0076
0077 /* Left audio samples duplicated to right audio channel */
0078 #define ATMEL_I2SC_MR_RXMONO        BIT(8)
0079
0080 /* Receiver uses one DMA channel ... */
0081 #define ATMEL_I2SC_MR_RXDMA_MASK    GENMASK(9, 9)
0082 #define ATMEL_I2SC_MR_RXDMA_SINGLE  (0 << 9)  /* for all audio channels */
0083 #define ATMEL_I2SC_MR_RXDMA_MULTIPLE    (1 << 9)  /* per audio channel */
0084
0085 /* I2SDO output of I2SC is internally connected to I2SDI input */
0086 #define ATMEL_I2SC_MR_RXLOOP        BIT(10)
0087
0088 /* Left audio samples duplicated to right audio channel */
0089 #define ATMEL_I2SC_MR_TXMONO        BIT(12)
0090
0091 /* Transmitter uses one DMA channel ... */
0092 #define ATMEL_I2SC_MR_TXDMA_MASK    GENMASK(13, 13)
0093 #define ATMEL_I2SC_MR_TXDMA_SINGLE  (0 << 13)  /* for all audio channels */
0094 #define ATMEL_I2SC_MR_TXDME_MULTIPLE    (1 << 13)  /* per audio channel */
0095
0096 /* x sample transmitted when underrun */
0097 #define ATMEL_I2SC_MR_TXSAME_MASK   GENMASK(14, 14)
0098 #define ATMEL_I2SC_MR_TXSAME_ZERO   (0 << 14)  /* Zero sample */
0099 #define ATMEL_I2SC_MR_TXSAME_PREVIOUS   (1 << 14)  /* Previous sample */
0100
0101 /* Audio Clock to I2SC Master Clock ratio */
0102 #define ATMEL_I2SC_MR_IMCKDIV_MASK  GENMASK(21, 16)
0103 #define ATMEL_I2SC_MR_IMCKDIV(div) \
0104     (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK)
0105
0106 /* Master Clock to fs ratio */
0107 #define ATMEL_I2SC_MR_IMCKFS_MASK   GENMASK(29, 24)
0108 #define ATMEL_I2SC_MR_IMCKFS(fs) \
0109     (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK)
0110
0111 /* Master Clock mode */
0112 #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30)
0113 /* 0: No master clock generated (selected clock drives I2SCK pin) */
0114 #define ATMEL_I2SC_MR_IMCKMODE_I2SCK    (0 << 30)
0115 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
0116 #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK   (1 << 30)
0117
0118 /* Slot Width */
0119 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
0120 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
0121 #define ATMEL_I2SC_MR_IWS       BIT(31)
0122
0123 /*
0124  * ---- Status Registers ----
0125  */
0126 #define ATMEL_I2SC_SR_RXEN  BIT(0)  /* Receiver Enabled */
0127 #define ATMEL_I2SC_SR_RXRDY BIT(1)  /* Receive Ready */
0128 #define ATMEL_I2SC_SR_RXOR  BIT(2)  /* Receive Overrun */
0129
0130 #define ATMEL_I2SC_SR_TXEN  BIT(4)  /* Transmitter Enabled */
0131 #define ATMEL_I2SC_SR_TXRDY BIT(5)  /* Transmit Ready */
0132 #define ATMEL_I2SC_SR_TXUR  BIT(6)  /* Transmit Underrun */
0133
0134 /* Receive Overrun Channel */
0135 #define ATMEL_I2SC_SR_RXORCH_MASK   GENMASK(15, 8)
0136 #define ATMEL_I2SC_SR_RXORCH(ch)    (1 << (((ch) & 0x7) + 8))
0137
0138 /* Transmit Underrun Channel */
0139 #define ATMEL_I2SC_SR_TXURCH_MASK   GENMASK(27, 20)
0140 #define ATMEL_I2SC_SR_TXURCH(ch)    (1 << (((ch) & 0x7) + 20))
0141
0142 /*
0143  * ---- Interrupt Enable/Disable/Mask Registers ----
0144  */
0145 #define ATMEL_I2SC_INT_RXRDY    ATMEL_I2SC_SR_RXRDY
0146 #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR
0147 #define ATMEL_I2SC_INT_TXRDY    ATMEL_I2SC_SR_TXRDY
0148 #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR
0149
0150 static const struct regmap_config atmel_i2s_regmap_config = {
0151     .reg_bits = 32,
0152     .reg_stride = 4,
0153     .val_bits = 32,
0154     .max_register = ATMEL_I2SC_VERSION,
0155 };
0156
0157 struct atmel_i2s_gck_param {
0158     int     fs;
0159     unsigned long   mck;
0160     int     imckdiv;
0161     int     imckfs;
0162 };
0163
0164 #define I2S_MCK_12M288      12288000UL
0165 #define I2S_MCK_11M2896     11289600UL
0166
0167 /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */
0168 static const struct atmel_i2s_gck_param gck_params[] = {
0169     /* mck = 12.288MHz */
0170     {  8000, I2S_MCK_12M288, 0, 47},    /* mck = 1536 fs */
0171     { 16000, I2S_MCK_12M288, 1, 47},    /* mck =  768 fs */
0172     { 24000, I2S_MCK_12M288, 3, 63},    /* mck =  512 fs */
0173     { 32000, I2S_MCK_12M288, 3, 47},    /* mck =  384 fs */
0174     { 48000, I2S_MCK_12M288, 7, 63},    /* mck =  256 fs */
0175     { 64000, I2S_MCK_12M288, 7, 47},    /* mck =  192 fs */
0176     { 96000, I2S_MCK_12M288, 7, 31},    /* mck =  128 fs */
0177     {192000, I2S_MCK_12M288, 7, 15},    /* mck =   64 fs */
0178
0179     /* mck = 11.2896MHz */
0180     { 11025, I2S_MCK_11M2896, 1, 63},   /* mck = 1024 fs */
0181     { 22050, I2S_MCK_11M2896, 3, 63},   /* mck =  512 fs */
0182     { 44100, I2S_MCK_11M2896, 7, 63},   /* mck =  256 fs */
0183     { 88200, I2S_MCK_11M2896, 7, 31},   /* mck =  128 fs */
0184     {176400, I2S_MCK_11M2896, 7, 15},   /* mck =   64 fs */
0185 };
0186
0187 struct atmel_i2s_dev;
0188
0189 struct atmel_i2s_caps {
0190     int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np);
0191 };
0192
0193 struct atmel_i2s_dev {
0194     struct device               *dev;
0195     struct regmap               *regmap;
0196     struct clk              *pclk;
0197     struct clk              *gclk;
0198     struct snd_dmaengine_dai_dma_data   playback;
0199     struct snd_dmaengine_dai_dma_data   capture;
0200     unsigned int                fmt;
0201     const struct atmel_i2s_gck_param    *gck_param;
0202     const struct atmel_i2s_caps     *caps;
0203     int                 clk_use_no;
0204 };
0205
0206 static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id)
0207 {
0208     struct atmel_i2s_dev *dev = dev_id;
0209     unsigned int sr, imr, pending, ch, mask;
0210     irqreturn_t ret = IRQ_NONE;
0211
0212     regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
0213     regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr);
0214     pending = sr & imr;
0215
0216     if (!pending)
0217         return IRQ_NONE;
0218
0219     if (pending & ATMEL_I2SC_INT_RXOR) {
0220         mask = ATMEL_I2SC_SR_RXOR;
0221
0222         for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
0223             if (sr & ATMEL_I2SC_SR_RXORCH(ch)) {
0224                 mask |= ATMEL_I2SC_SR_RXORCH(ch);
0225                 dev_err(dev->dev,
0226                     "RX overrun on channel %d\n", ch);
0227             }
0228         }
0229         regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
0230         ret = IRQ_HANDLED;
0231     }
0232
0233     if (pending & ATMEL_I2SC_INT_TXUR) {
0234         mask = ATMEL_I2SC_SR_TXUR;
0235
0236         for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
0237             if (sr & ATMEL_I2SC_SR_TXURCH(ch)) {
0238                 mask |= ATMEL_I2SC_SR_TXURCH(ch);
0239                 dev_err(dev->dev,
0240                     "TX underrun on channel %d\n", ch);
0241             }
0242         }
0243         regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
0244         ret = IRQ_HANDLED;
0245     }
0246
0247     return ret;
0248 }
0249
0250 #define ATMEL_I2S_RATES     SNDRV_PCM_RATE_8000_192000
0251
0252 #define ATMEL_I2S_FORMATS   (SNDRV_PCM_FMTBIT_S8 |      \
0253                  SNDRV_PCM_FMTBIT_S16_LE |  \
0254                  SNDRV_PCM_FMTBIT_S18_3LE | \
0255                  SNDRV_PCM_FMTBIT_S20_3LE | \
0256                  SNDRV_PCM_FMTBIT_S24_3LE | \
0257                  SNDRV_PCM_FMTBIT_S24_LE |  \
0258                  SNDRV_PCM_FMTBIT_S32_LE)
0259
0260 static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0261 {
0262     struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0263
0264     dev->fmt = fmt;
0265     return 0;
0266 }
0267
0268 static int atmel_i2s_prepare(struct snd_pcm_substream *substream,
0269                  struct snd_soc_dai *dai)
0270 {
0271     struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0272     bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0273     unsigned int rhr, sr = 0;
0274
0275     if (is_playback) {
0276         regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
0277         if (sr & ATMEL_I2SC_SR_RXRDY) {
0278             /*
0279              * The RX Ready flag should not be set. However if here,
0280              * we flush (read) the Receive Holding Register to start
0281              * from a clean state.
0282              */
0283             dev_dbg(dev->dev, "RXRDY is set\n");
0284             regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr);
0285         }
0286     }
0287
0288     return 0;
0289 }
0290
0291 static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs)
0292 {
0293     int i, best;
0294
0295     if (!dev->gclk) {
0296         dev_err(dev->dev, "cannot generate the I2S Master Clock\n");
0297         return -EINVAL;
0298     }
0299
0300     /*
0301      * Find the best possible settings to generate the I2S Master Clock
0302      * from the PLL Audio.
0303      */
0304     dev->gck_param = NULL;
0305     best = INT_MAX;
0306     for (i = 0; i < ARRAY_SIZE(gck_params); ++i) {
0307         const struct atmel_i2s_gck_param *gck_param = &gck_params[i];
0308         int val = abs(fs - gck_param->fs);
0309
0310         if (val < best) {
0311             best = val;
0312             dev->gck_param = gck_param;
0313         }
0314     }
0315
0316     return 0;
0317 }
0318
0319 static int atmel_i2s_hw_params(struct snd_pcm_substream *substream,
0320                    struct snd_pcm_hw_params *params,
0321                    struct snd_soc_dai *dai)
0322 {
0323     struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0324     bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0325     unsigned int mr = 0, mr_mask;
0326     int ret;
0327
0328     mr_mask = ATMEL_I2SC_MR_FORMAT_MASK | ATMEL_I2SC_MR_MODE_MASK |
0329         ATMEL_I2SC_MR_DATALENGTH_MASK;
0330     if (is_playback)
0331         mr_mask |= ATMEL_I2SC_MR_TXMONO;
0332     else
0333         mr_mask |= ATMEL_I2SC_MR_RXMONO;
0334
0335     switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0336     case SND_SOC_DAIFMT_I2S:
0337         mr |= ATMEL_I2SC_MR_FORMAT_I2S;
0338         break;
0339
0340     default:
0341         dev_err(dev->dev, "unsupported bus format\n");
0342         return -EINVAL;
0343     }
0344
0345     switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0346     case SND_SOC_DAIFMT_BP_FP:
0347         /* codec is slave, so cpu is master */
0348         mr |= ATMEL_I2SC_MR_MODE_MASTER;
0349         ret = atmel_i2s_get_gck_param(dev, params_rate(params));
0350         if (ret)
0351             return ret;
0352         break;
0353
0354     case SND_SOC_DAIFMT_BC_FC:
0355         /* codec is master, so cpu is slave */
0356         mr |= ATMEL_I2SC_MR_MODE_SLAVE;
0357         dev->gck_param = NULL;
0358         break;
0359
0360     default:
0361         dev_err(dev->dev, "unsupported master/slave mode\n");
0362         return -EINVAL;
0363     }
0364
0365     switch (params_channels(params)) {
0366     case 1:
0367         if (is_playback)
0368             mr |= ATMEL_I2SC_MR_TXMONO;
0369         else
0370             mr |= ATMEL_I2SC_MR_RXMONO;
0371         break;
0372     case 2:
0373         break;
0374     default:
0375         dev_err(dev->dev, "unsupported number of audio channels\n");
0376         return -EINVAL;
0377     }
0378
0379     switch (params_format(params)) {
0380     case SNDRV_PCM_FORMAT_S8:
0381         mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS;
0382         break;
0383
0384     case SNDRV_PCM_FORMAT_S16_LE:
0385         mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS;
0386         break;
0387
0388     case SNDRV_PCM_FORMAT_S18_3LE:
0389         mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS;
0390         break;
0391
0392     case SNDRV_PCM_FORMAT_S20_3LE:
0393         mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS;
0394         break;
0395
0396     case SNDRV_PCM_FORMAT_S24_3LE:
0397         mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS;
0398         break;
0399
0400     case SNDRV_PCM_FORMAT_S24_LE:
0401         mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS;
0402         break;
0403
0404     case SNDRV_PCM_FORMAT_S32_LE:
0405         mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS;
0406         break;
0407
0408     default:
0409         dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
0410         return -EINVAL;
0411     }
0412
0413     return regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
0414 }
0415
0416 static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev,
0417                       bool enabled)
0418 {
0419     unsigned int mr, mr_mask;
0420     unsigned long gclk_rate;
0421     int ret;
0422
0423     mr = 0;
0424     mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK |
0425            ATMEL_I2SC_MR_IMCKFS_MASK |
0426            ATMEL_I2SC_MR_IMCKMODE_MASK);
0427
0428     if (!enabled) {
0429         /* Disable the I2S Master Clock generator. */
0430         ret = regmap_write(dev->regmap, ATMEL_I2SC_CR,
0431                    ATMEL_I2SC_CR_CKDIS);
0432         if (ret)
0433             return ret;
0434
0435         /* Reset the I2S Master Clock generator settings. */
0436         ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR,
0437                      mr_mask, mr);
0438         if (ret)
0439             return ret;
0440
0441         /* Disable/unprepare the PMC generated clock. */
0442         clk_disable_unprepare(dev->gclk);
0443
0444         return 0;
0445     }
0446
0447     if (!dev->gck_param)
0448         return -EINVAL;
0449
0450     gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1);
0451
0452     ret = clk_set_rate(dev->gclk, gclk_rate);
0453     if (ret)
0454         return ret;
0455
0456     ret = clk_prepare_enable(dev->gclk);
0457     if (ret)
0458         return ret;
0459
0460     /* Update the Mode Register to generate the I2S Master Clock. */
0461     mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv);
0462     mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs);
0463     mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK;
0464     ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
0465     if (ret)
0466         return ret;
0467
0468     /* Finally enable the I2S Master Clock generator. */
0469     return regmap_write(dev->regmap, ATMEL_I2SC_CR,
0470                 ATMEL_I2SC_CR_CKEN);
0471 }
0472
0473 static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
0474                  struct snd_soc_dai *dai)
0475 {
0476     struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0477     bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0478     bool is_master, mck_enabled;
0479     unsigned int cr, mr;
0480     int err;
0481
0482     switch (cmd) {
0483     case SNDRV_PCM_TRIGGER_START:
0484     case SNDRV_PCM_TRIGGER_RESUME:
0485     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0486         cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN;
0487         mck_enabled = true;
0488         break;
0489     case SNDRV_PCM_TRIGGER_STOP:
0490     case SNDRV_PCM_TRIGGER_SUSPEND:
0491     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0492         cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS;
0493         mck_enabled = false;
0494         break;
0495     default:
0496         return -EINVAL;
0497     }
0498
0499     /* Read the Mode Register to retrieve the master/slave state. */
0500     err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr);
0501     if (err)
0502         return err;
0503     is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER;
0504
0505     /* If master starts, enable the audio clock. */
0506     if (is_master && mck_enabled) {
0507         if (!dev->clk_use_no) {
0508             err = atmel_i2s_switch_mck_generator(dev, true);
0509             if (err)
0510                 return err;
0511         }
0512         dev->clk_use_no++;
0513     }
0514
0515     err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr);
0516     if (err)
0517         return err;
0518
0519     /* If master stops, disable the audio clock. */
0520     if (is_master && !mck_enabled) {
0521         if (dev->clk_use_no == 1) {
0522             err = atmel_i2s_switch_mck_generator(dev, false);
0523             if (err)
0524                 return err;
0525         }
0526         dev->clk_use_no--;
0527     }
0528
0529     return err;
0530 }
0531
0532 static const struct snd_soc_dai_ops atmel_i2s_dai_ops = {
0533     .prepare    = atmel_i2s_prepare,
0534     .trigger    = atmel_i2s_trigger,
0535     .hw_params  = atmel_i2s_hw_params,
0536     .set_fmt    = atmel_i2s_set_dai_fmt,
0537 };
0538
0539 static int atmel_i2s_dai_probe(struct snd_soc_dai *dai)
0540 {
0541     struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0542
0543     snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
0544     return 0;
0545 }
0546
0547 static struct snd_soc_dai_driver atmel_i2s_dai = {
0548     .probe  = atmel_i2s_dai_probe,
0549     .playback = {
0550         .channels_min = 1,
0551         .channels_max = 2,
0552         .rates = ATMEL_I2S_RATES,
0553         .formats = ATMEL_I2S_FORMATS,
0554     },
0555     .capture = {
0556         .channels_min = 1,
0557         .channels_max = 2,
0558         .rates = ATMEL_I2S_RATES,
0559         .formats = ATMEL_I2S_FORMATS,
0560     },
0561     .ops = &atmel_i2s_dai_ops,
0562     .symmetric_rate = 1,
0563     .symmetric_sample_bits = 1,
0564 };
0565
0566 static const struct snd_soc_component_driver atmel_i2s_component = {
0567     .name           = "atmel-i2s",
0568     .legacy_dai_naming  = 1,
0569 };
0570
0571 static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev,
0572                       struct device_node *np)
0573 {
0574     struct clk *muxclk;
0575     int err;
0576
0577     if (!dev->gclk)
0578         return 0;
0579
0580     /* muxclk is optional, so we return error for probe defer only */
0581     muxclk = devm_clk_get(dev->dev, "muxclk");
0582     if (IS_ERR(muxclk)) {
0583         err = PTR_ERR(muxclk);
0584         if (err == -EPROBE_DEFER)
0585             return -EPROBE_DEFER;
0586         dev_dbg(dev->dev,
0587             "failed to get the I2S clock control: %d\n", err);
0588         return 0;
0589     }
0590
0591     return clk_set_parent(muxclk, dev->gclk);
0592 }
0593
0594 static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = {
0595     .mck_init = atmel_i2s_sama5d2_mck_init,
0596 };
0597
0598 static const struct of_device_id atmel_i2s_dt_ids[] = {
0599     {
0600         .compatible = "atmel,sama5d2-i2s",
0601         .data = (void *)&atmel_i2s_sama5d2_caps,
0602     },
0603
0604     { /* sentinel */ }
0605 };
0606
0607 MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids);
0608
0609 static int atmel_i2s_probe(struct platform_device *pdev)
0610 {
0611     struct device_node *np = pdev->dev.of_node;
0612     const struct of_device_id *match;
0613     struct atmel_i2s_dev *dev;
0614     struct resource *mem;
0615     struct regmap *regmap;
0616     void __iomem *base;
0617     int irq;
0618     int err;
0619     unsigned int pcm_flags = 0;
0620     unsigned int version;
0621
0622     /* Get memory for driver data. */
0623     dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
0624     if (!dev)
0625         return -ENOMEM;
0626
0627     /* Get hardware capabilities. */
0628     match = of_match_node(atmel_i2s_dt_ids, np);
0629     if (match)
0630         dev->caps = match->data;
0631
0632     /* Map I/O registers. */
0633     base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
0634     if (IS_ERR(base))
0635         return PTR_ERR(base);
0636
0637     regmap = devm_regmap_init_mmio(&pdev->dev, base,
0638                        &atmel_i2s_regmap_config);
0639     if (IS_ERR(regmap))
0640         return PTR_ERR(regmap);
0641
0642     /* Request IRQ. */
0643     irq = platform_get_irq(pdev, 0);
0644     if (irq < 0)
0645         return irq;
0646
0647     err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
0648                    dev_name(&pdev->dev), dev);
0649     if (err)
0650         return err;
0651
0652     /* Get the peripheral clock. */
0653     dev->pclk = devm_clk_get(&pdev->dev, "pclk");
0654     if (IS_ERR(dev->pclk)) {
0655         err = PTR_ERR(dev->pclk);
0656         dev_err(&pdev->dev,
0657             "failed to get the peripheral clock: %d\n", err);
0658         return err;
0659     }
0660
0661     /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */
0662     dev->gclk = devm_clk_get(&pdev->dev, "gclk");
0663     if (IS_ERR(dev->gclk)) {
0664         if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
0665             return -EPROBE_DEFER;
0666         /* Master Mode not supported */
0667         dev->gclk = NULL;
0668     }
0669     dev->dev = &pdev->dev;
0670     dev->regmap = regmap;
0671     platform_set_drvdata(pdev, dev);
0672
0673     /* Do hardware specific settings to initialize I2S_MCK generator */
0674     if (dev->caps && dev->caps->mck_init) {
0675         err = dev->caps->mck_init(dev, np);
0676         if (err)
0677             return err;
0678     }
0679
0680     /* Enable the peripheral clock. */
0681     err = clk_prepare_enable(dev->pclk);
0682     if (err)
0683         return err;
0684
0685     /* Get IP version. */
0686     regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version);
0687     dev_info(&pdev->dev, "hw version: %#x\n", version);
0688
0689     /* Enable error interrupts. */
0690     regmap_write(dev->regmap, ATMEL_I2SC_IER,
0691              ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR);
0692
0693     err = devm_snd_soc_register_component(&pdev->dev,
0694                           &atmel_i2s_component,
0695                           &atmel_i2s_dai, 1);
0696     if (err) {
0697         dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
0698         clk_disable_unprepare(dev->pclk);
0699         return err;
0700     }
0701
0702     /* Prepare DMA config. */
0703     dev->playback.addr  = (dma_addr_t)mem->start + ATMEL_I2SC_THR;
0704     dev->playback.maxburst  = 1;
0705     dev->capture.addr   = (dma_addr_t)mem->start + ATMEL_I2SC_RHR;
0706     dev->capture.maxburst   = 1;
0707
0708     if (of_property_match_string(np, "dma-names", "rx-tx") == 0)
0709         pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX;
0710     err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags);
0711     if (err) {
0712         dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
0713         clk_disable_unprepare(dev->pclk);
0714         return err;
0715     }
0716
0717     return 0;
0718 }
0719
0720 static int atmel_i2s_remove(struct platform_device *pdev)
0721 {
0722     struct atmel_i2s_dev *dev = platform_get_drvdata(pdev);
0723
0724     clk_disable_unprepare(dev->pclk);
0725
0726     return 0;
0727 }
0728
0729 static struct platform_driver atmel_i2s_driver = {
0730     .driver     = {
0731         .name   = "atmel_i2s",
0732         .of_match_table = of_match_ptr(atmel_i2s_dt_ids),
0733     },
0734     .probe      = atmel_i2s_probe,
0735     .remove     = atmel_i2s_remove,
0736 };
0737 module_platform_driver(atmel_i2s_driver);
0738
0739 MODULE_DESCRIPTION("Atmel I2S Controller driver");
0740 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
0741 MODULE_LICENSE("GPL v2");