amd/yc/acp6x.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * AMD ALSA SoC PDM Driver
0004  *
0005  * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
0006  */
0007
0008 #include "acp6x_chip_offset_byte.h"
0009
0010 #define ACP_DEVICE_ID 0x15E2
0011 #define ACP6x_PHY_BASE_ADDRESS 0x1240000
0012 #define ACP6x_REG_START     0x1240000
0013 #define ACP6x_REG_END       0x1250200
0014 #define ACP6x_DEVS      3
0015 #define ACP6x_PDM_MODE      1
0016
0017 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK   0x00010001
0018 #define ACP_PGFSM_CNTL_POWER_ON_MASK    1
0019 #define ACP_PGFSM_CNTL_POWER_OFF_MASK   0
0020 #define ACP_PGFSM_STATUS_MASK       3
0021 #define ACP_POWERED_ON          0
0022 #define ACP_POWER_ON_IN_PROGRESS    1
0023 #define ACP_POWERED_OFF         2
0024 #define ACP_POWER_OFF_IN_PROGRESS   3
0025
0026 #define ACP_ERROR_MASK 0x20000000
0027 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
0028 #define PDM_DMA_STAT 0x10
0029
0030 #define PDM_DMA_INTR_MASK   0x10000
0031 #define ACP_ERROR_STAT  29
0032 #define PDM_DECIMATION_FACTOR   2
0033 #define ACP_PDM_CLK_FREQ_MASK   7
0034 #define ACP_WOV_MISC_CTRL_MASK  0x10
0035 #define ACP_PDM_ENABLE      1
0036 #define ACP_PDM_DISABLE     0
0037 #define ACP_PDM_DMA_EN_STATUS   2
0038 #define TWO_CH      2
0039 #define DELAY_US    5
0040 #define ACP_COUNTER 20000
0041
0042 #define ACP_SRAM_PTE_OFFSET 0x03800000
0043 #define PAGE_SIZE_4K_ENABLE 2
0044 #define PDM_PTE_OFFSET      0
0045 #define PDM_MEM_WINDOW_START    0x4000000
0046
0047 #define CAPTURE_MIN_NUM_PERIODS     4
0048 #define CAPTURE_MAX_NUM_PERIODS     4
0049 #define CAPTURE_MAX_PERIOD_SIZE     8192
0050 #define CAPTURE_MIN_PERIOD_SIZE     4096
0051
0052 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
0053 #define MIN_BUFFER MAX_BUFFER
0054
0055 /* time in ms for runtime suspend delay */
0056 #define ACP_SUSPEND_DELAY_MS    2000
0057
0058 enum acp_config {
0059     ACP_CONFIG_0 = 0,
0060     ACP_CONFIG_1,
0061     ACP_CONFIG_2,
0062     ACP_CONFIG_3,
0063     ACP_CONFIG_4,
0064     ACP_CONFIG_5,
0065     ACP_CONFIG_6,
0066     ACP_CONFIG_7,
0067     ACP_CONFIG_8,
0068     ACP_CONFIG_9,
0069     ACP_CONFIG_10,
0070     ACP_CONFIG_11,
0071     ACP_CONFIG_12,
0072     ACP_CONFIG_13,
0073     ACP_CONFIG_14,
0074     ACP_CONFIG_15,
0075 };
0076
0077 struct pdm_dev_data {
0078     u32 pdm_irq;
0079     void __iomem *acp6x_base;
0080     struct snd_pcm_substream *capture_stream;
0081 };
0082
0083 struct pdm_stream_instance {
0084     u16 num_pages;
0085     u16 channels;
0086     dma_addr_t dma_addr;
0087     u64 bytescount;
0088     void __iomem *acp6x_base;
0089 };
0090
0091 union acp_pdm_dma_count {
0092     struct {
0093     u32 low;
0094     u32 high;
0095     } bcount;
0096     u64 bytescount;
0097 };
0098
0099 static inline u32 acp6x_readl(void __iomem *base_addr)
0100 {
0101     return readl(base_addr - ACP6x_PHY_BASE_ADDRESS);
0102 }
0103
0104 static inline void acp6x_writel(u32 val, void __iomem *base_addr)
0105 {
0106     writel(val, base_addr - ACP6x_PHY_BASE_ADDRESS);
0107 }