amd/vangogh/acp5x.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * AMD ALSA SoC PCM Driver
0004  *
0005  * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
0006  */
0007
0008 #include "vg_chip_offset_byte.h"
0009 #include <sound/pcm.h>
0010
0011 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
0012 #define ACP_DEVICE_ID 0x15E2
0013 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK   0x00010001
0014
0015 #define ACP_PGFSM_CNTL_POWER_ON_MASK    0x01
0016 #define ACP_PGFSM_CNTL_POWER_OFF_MASK   0x00
0017 #define ACP_PGFSM_STATUS_MASK       0x03
0018 #define ACP_POWERED_ON          0x00
0019 #define ACP_POWER_ON_IN_PROGRESS    0x01
0020 #define ACP_POWERED_OFF         0x02
0021 #define ACP_POWER_OFF_IN_PROGRESS   0x03
0022
0023 #define ACP_ERR_INTR_MASK   0x20000000
0024 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
0025
0026 #define ACP5x_DEVS 4
0027 #define ACP5x_REG_START 0x1240000
0028 #define ACP5x_REG_END   0x1250200
0029 #define ACP5x_I2STDM_REG_START  0x1242400
0030 #define ACP5x_I2STDM_REG_END    0x1242410
0031 #define ACP5x_HS_TDM_REG_START  0x1242814
0032 #define ACP5x_HS_TDM_REG_END    0x1242824
0033 #define I2S_MODE 0
0034 #define ACP5x_I2S_MODE 1
0035 #define ACP5x_RES 4
0036 #define I2S_RX_THRESHOLD 27
0037 #define I2S_TX_THRESHOLD 28
0038 #define HS_TX_THRESHOLD 24
0039 #define HS_RX_THRESHOLD 23
0040
0041 #define I2S_SP_INSTANCE                 1
0042 #define I2S_HS_INSTANCE                 2
0043
0044 #define ACP_SRAM_PTE_OFFSET 0x02050000
0045 #define ACP_SRAM_SP_PB_PTE_OFFSET   0x0
0046 #define ACP_SRAM_SP_CP_PTE_OFFSET   0x100
0047 #define ACP_SRAM_HS_PB_PTE_OFFSET   0x200
0048 #define ACP_SRAM_HS_CP_PTE_OFFSET   0x300
0049 #define PAGE_SIZE_4K_ENABLE 0x2
0050 #define I2S_SP_TX_MEM_WINDOW_START  0x4000000
0051 #define I2S_SP_RX_MEM_WINDOW_START  0x4020000
0052 #define I2S_HS_TX_MEM_WINDOW_START  0x4040000
0053 #define I2S_HS_RX_MEM_WINDOW_START  0x4060000
0054
0055 #define SP_PB_FIFO_ADDR_OFFSET      0x500
0056 #define SP_CAPT_FIFO_ADDR_OFFSET    0x700
0057 #define HS_PB_FIFO_ADDR_OFFSET      0x900
0058 #define HS_CAPT_FIFO_ADDR_OFFSET    0xB00
0059 #define PLAYBACK_MIN_NUM_PERIODS    2
0060 #define PLAYBACK_MAX_NUM_PERIODS    8
0061 #define PLAYBACK_MAX_PERIOD_SIZE    8192
0062 #define PLAYBACK_MIN_PERIOD_SIZE    1024
0063 #define CAPTURE_MIN_NUM_PERIODS     2
0064 #define CAPTURE_MAX_NUM_PERIODS     8
0065 #define CAPTURE_MAX_PERIOD_SIZE     8192
0066 #define CAPTURE_MIN_PERIOD_SIZE     1024
0067
0068 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
0069 #define MIN_BUFFER MAX_BUFFER
0070 #define FIFO_SIZE 0x100
0071 #define DMA_SIZE 0x40
0072 #define FRM_LEN 0x100
0073
0074 #define I2S_MASTER_MODE_ENABLE 1
0075 #define I2S_MASTER_MODE_DISABLE 0
0076
0077 #define SLOT_WIDTH_8 8
0078 #define SLOT_WIDTH_16 16
0079 #define SLOT_WIDTH_24 24
0080 #define SLOT_WIDTH_32 32
0081 #define TDM_ENABLE 1
0082 #define TDM_DISABLE 0
0083 #define ACP5x_ITER_IRER_SAMP_LEN_MASK   0x38
0084
0085 struct i2s_dev_data {
0086     bool tdm_mode;
0087     bool master_mode;
0088     int i2s_irq;
0089     u16 i2s_instance;
0090     u32 tdm_fmt;
0091     void __iomem *acp5x_base;
0092     struct snd_pcm_substream *play_stream;
0093     struct snd_pcm_substream *capture_stream;
0094     struct snd_pcm_substream *i2ssp_play_stream;
0095     struct snd_pcm_substream *i2ssp_capture_stream;
0096 };
0097
0098 struct i2s_stream_instance {
0099     u16 num_pages;
0100     u16 i2s_instance;
0101     u16 direction;
0102     u16 channels;
0103     u32 xfer_resolution;
0104     u32 val;
0105     dma_addr_t dma_addr;
0106     u64 bytescount;
0107     void __iomem *acp5x_base;
0108     u32 lrclk_div;
0109     u32 bclk_div;
0110 };
0111
0112 union acp_dma_count {
0113     struct {
0114         u32 low;
0115         u32 high;
0116     } bcount;
0117     u64 bytescount;
0118 };
0119
0120 struct acp5x_platform_info {
0121     u16 play_i2s_instance;
0122     u16 cap_i2s_instance;
0123 };
0124
0125 union acp_i2stdm_mstrclkgen {
0126     struct {
0127         u32 i2stdm_master_mode : 1;
0128         u32 i2stdm_format_mode : 1;
0129         u32 i2stdm_lrclk_div_val : 9;
0130         u32 i2stdm_bclk_div_val : 11;
0131         u32:10;
0132     } bitfields, bits;
0133     u32  u32_all;
0134 };
0135
0136 /* common header file uses exact offset rather than relative
0137  * offset which requires subtraction logic from base_addr
0138  * for accessing ACP5x MMIO space registers
0139  */
0140 static inline u32 acp_readl(void __iomem *base_addr)
0141 {
0142     return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
0143 }
0144
0145 static inline void acp_writel(u32 val, void __iomem *base_addr)
0146 {
0147     writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
0148 }
0149
0150 static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
0151                      int direction)
0152 {
0153     union acp_dma_count byte_count;
0154
0155     if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0156         switch (rtd->i2s_instance) {
0157         case I2S_HS_INSTANCE:
0158             byte_count.bcount.high =
0159                 acp_readl(rtd->acp5x_base +
0160                       ACP_HS_TX_LINEARPOSCNTR_HIGH);
0161             byte_count.bcount.low =
0162                 acp_readl(rtd->acp5x_base +
0163                       ACP_HS_TX_LINEARPOSCNTR_LOW);
0164             break;
0165         case I2S_SP_INSTANCE:
0166         default:
0167             byte_count.bcount.high =
0168                 acp_readl(rtd->acp5x_base +
0169                       ACP_I2S_TX_LINEARPOSCNTR_HIGH);
0170             byte_count.bcount.low =
0171                 acp_readl(rtd->acp5x_base +
0172                       ACP_I2S_TX_LINEARPOSCNTR_LOW);
0173         }
0174     } else {
0175         switch (rtd->i2s_instance) {
0176         case I2S_HS_INSTANCE:
0177             byte_count.bcount.high =
0178                 acp_readl(rtd->acp5x_base +
0179                       ACP_HS_RX_LINEARPOSCNTR_HIGH);
0180             byte_count.bcount.low =
0181                 acp_readl(rtd->acp5x_base +
0182                       ACP_HS_RX_LINEARPOSCNTR_LOW);
0183             break;
0184         case I2S_SP_INSTANCE:
0185         default:
0186             byte_count.bcount.high =
0187                 acp_readl(rtd->acp5x_base +
0188                       ACP_I2S_RX_LINEARPOSCNTR_HIGH);
0189             byte_count.bcount.low =
0190                 acp_readl(rtd->acp5x_base +
0191                       ACP_I2S_RX_LINEARPOSCNTR_LOW);
0192         }
0193     }
0194     return byte_count.bytescount;
0195 }
0196
0197 static inline void acp5x_set_i2s_clk(struct i2s_dev_data *adata,
0198                      struct i2s_stream_instance *rtd)
0199 {
0200     union acp_i2stdm_mstrclkgen mclkgen;
0201     u32 master_reg;
0202
0203     switch (rtd->i2s_instance) {
0204     case I2S_HS_INSTANCE:
0205         master_reg = ACP_I2STDM2_MSTRCLKGEN;
0206         break;
0207     case I2S_SP_INSTANCE:
0208     default:
0209         master_reg = ACP_I2STDM0_MSTRCLKGEN;
0210         break;
0211     }
0212
0213     mclkgen.bits.i2stdm_master_mode = 0x1;
0214     if (adata->tdm_mode)
0215         mclkgen.bits.i2stdm_format_mode = 0x01;
0216     else
0217         mclkgen.bits.i2stdm_format_mode = 0x00;
0218
0219     mclkgen.bits.i2stdm_bclk_div_val = rtd->bclk_div;
0220     mclkgen.bits.i2stdm_lrclk_div_val = rtd->lrclk_div;
0221     acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
0222 }