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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // AMD ALSA SoC PCM Driver
0004 //
0005 // Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
0006 
0007 #include <linux/platform_device.h>
0008 #include <linux/module.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/pm_runtime.h>
0012 #include <sound/pcm.h>
0013 #include <sound/pcm_params.h>
0014 #include <sound/soc.h>
0015 #include <sound/soc-dai.h>
0016 
0017 #include "acp5x.h"
0018 
0019 #define DRV_NAME "acp5x_i2s_dma"
0020 
0021 static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
0022     .info = SNDRV_PCM_INFO_INTERLEAVED |
0023         SNDRV_PCM_INFO_BLOCK_TRANSFER |
0024         SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
0025         SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
0026     .formats = SNDRV_PCM_FMTBIT_S16_LE |  SNDRV_PCM_FMTBIT_S8 |
0027            SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
0028     .channels_min = 2,
0029     .channels_max = 2,
0030     .rates = SNDRV_PCM_RATE_8000_96000,
0031     .rate_min = 8000,
0032     .rate_max = 96000,
0033     .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
0034     .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
0035     .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
0036     .periods_min = PLAYBACK_MIN_NUM_PERIODS,
0037     .periods_max = PLAYBACK_MAX_NUM_PERIODS,
0038 };
0039 
0040 static const struct snd_pcm_hardware acp5x_pcm_hardware_capture = {
0041     .info = SNDRV_PCM_INFO_INTERLEAVED |
0042         SNDRV_PCM_INFO_BLOCK_TRANSFER |
0043         SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
0044         SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
0045     .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
0046            SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
0047     .channels_min = 2,
0048     .channels_max = 2,
0049     .rates = SNDRV_PCM_RATE_8000_96000,
0050     .rate_min = 8000,
0051     .rate_max = 96000,
0052     .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
0053     .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
0054     .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
0055     .periods_min = CAPTURE_MIN_NUM_PERIODS,
0056     .periods_max = CAPTURE_MAX_NUM_PERIODS,
0057 };
0058 
0059 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
0060 {
0061     struct i2s_dev_data *vg_i2s_data;
0062     u16 irq_flag;
0063     u32 val;
0064 
0065     vg_i2s_data = dev_id;
0066     if (!vg_i2s_data)
0067         return IRQ_NONE;
0068 
0069     irq_flag = 0;
0070     val = acp_readl(vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
0071     if ((val & BIT(HS_TX_THRESHOLD)) && vg_i2s_data->play_stream) {
0072         acp_writel(BIT(HS_TX_THRESHOLD), vg_i2s_data->acp5x_base +
0073                ACP_EXTERNAL_INTR_STAT);
0074         snd_pcm_period_elapsed(vg_i2s_data->play_stream);
0075         irq_flag = 1;
0076     }
0077     if ((val & BIT(I2S_TX_THRESHOLD)) && vg_i2s_data->i2ssp_play_stream) {
0078         acp_writel(BIT(I2S_TX_THRESHOLD),
0079                vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
0080         snd_pcm_period_elapsed(vg_i2s_data->i2ssp_play_stream);
0081         irq_flag = 1;
0082     }
0083 
0084     if ((val & BIT(HS_RX_THRESHOLD)) && vg_i2s_data->capture_stream) {
0085         acp_writel(BIT(HS_RX_THRESHOLD), vg_i2s_data->acp5x_base +
0086                ACP_EXTERNAL_INTR_STAT);
0087         snd_pcm_period_elapsed(vg_i2s_data->capture_stream);
0088         irq_flag = 1;
0089     }
0090     if ((val & BIT(I2S_RX_THRESHOLD)) && vg_i2s_data->i2ssp_capture_stream) {
0091         acp_writel(BIT(I2S_RX_THRESHOLD),
0092                vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
0093         snd_pcm_period_elapsed(vg_i2s_data->i2ssp_capture_stream);
0094         irq_flag = 1;
0095     }
0096 
0097     if (irq_flag)
0098         return IRQ_HANDLED;
0099     else
0100         return IRQ_NONE;
0101 }
0102 
0103 static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
0104 {
0105     u16 page_idx;
0106     u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
0107     u32 reg_dma_size, reg_fifo_size;
0108     dma_addr_t addr;
0109 
0110     addr = rtd->dma_addr;
0111     if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0112         switch (rtd->i2s_instance) {
0113         case I2S_HS_INSTANCE:
0114             val = ACP_SRAM_HS_PB_PTE_OFFSET;
0115             break;
0116         case I2S_SP_INSTANCE:
0117         default:
0118             val = ACP_SRAM_SP_PB_PTE_OFFSET;
0119         }
0120     } else {
0121         switch (rtd->i2s_instance) {
0122         case I2S_HS_INSTANCE:
0123             val = ACP_SRAM_HS_CP_PTE_OFFSET;
0124             break;
0125         case I2S_SP_INSTANCE:
0126         default:
0127             val = ACP_SRAM_SP_CP_PTE_OFFSET;
0128         }
0129     }
0130     /* Group Enable */
0131     acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
0132            ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
0133     acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
0134            ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
0135 
0136     for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
0137         /* Load the low address of page int ACP SRAM through SRBM */
0138         low = lower_32_bits(addr);
0139         high = upper_32_bits(addr);
0140 
0141         acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
0142         high |= BIT(31);
0143         acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val + 4);
0144         /* Move to next physically contiguous page */
0145         val += 8;
0146         addr += PAGE_SIZE;
0147     }
0148 
0149     if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0150         switch (rtd->i2s_instance) {
0151         case I2S_HS_INSTANCE:
0152             reg_dma_size = ACP_HS_TX_DMA_SIZE;
0153             acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
0154                     HS_PB_FIFO_ADDR_OFFSET;
0155             reg_fifo_addr = ACP_HS_TX_FIFOADDR;
0156             reg_fifo_size = ACP_HS_TX_FIFOSIZE;
0157             acp_writel(I2S_HS_TX_MEM_WINDOW_START,
0158                    rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
0159             break;
0160 
0161         case I2S_SP_INSTANCE:
0162         default:
0163             reg_dma_size = ACP_I2S_TX_DMA_SIZE;
0164             acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
0165                     SP_PB_FIFO_ADDR_OFFSET;
0166             reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
0167             reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
0168             acp_writel(I2S_SP_TX_MEM_WINDOW_START,
0169                    rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
0170         }
0171     } else {
0172         switch (rtd->i2s_instance) {
0173         case I2S_HS_INSTANCE:
0174             reg_dma_size = ACP_HS_RX_DMA_SIZE;
0175             acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
0176                     HS_CAPT_FIFO_ADDR_OFFSET;
0177             reg_fifo_addr = ACP_HS_RX_FIFOADDR;
0178             reg_fifo_size = ACP_HS_RX_FIFOSIZE;
0179             acp_writel(I2S_HS_RX_MEM_WINDOW_START,
0180                    rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
0181             break;
0182 
0183         case I2S_SP_INSTANCE:
0184         default:
0185             reg_dma_size = ACP_I2S_RX_DMA_SIZE;
0186             acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
0187                     SP_CAPT_FIFO_ADDR_OFFSET;
0188             reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
0189             reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
0190             acp_writel(I2S_SP_RX_MEM_WINDOW_START,
0191                    rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
0192         }
0193     }
0194     acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
0195     acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
0196     acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
0197     acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
0198            | BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
0199            rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
0200 }
0201 
0202 static int acp5x_dma_open(struct snd_soc_component *component,
0203               struct snd_pcm_substream *substream)
0204 {
0205     struct snd_pcm_runtime *runtime;
0206     struct snd_soc_pcm_runtime *prtd;
0207     struct i2s_dev_data *adata;
0208     struct i2s_stream_instance *i2s_data;
0209     int ret;
0210 
0211     runtime = substream->runtime;
0212     prtd = asoc_substream_to_rtd(substream);
0213     component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
0214     adata = dev_get_drvdata(component->dev);
0215 
0216     i2s_data = kzalloc(sizeof(*i2s_data), GFP_KERNEL);
0217     if (!i2s_data)
0218         return -ENOMEM;
0219 
0220     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0221         runtime->hw = acp5x_pcm_hardware_playback;
0222     else
0223         runtime->hw = acp5x_pcm_hardware_capture;
0224 
0225     ret = snd_pcm_hw_constraint_integer(runtime,
0226                         SNDRV_PCM_HW_PARAM_PERIODS);
0227     if (ret < 0) {
0228         dev_err(component->dev, "set integer constraint failed\n");
0229         kfree(i2s_data);
0230         return ret;
0231     }
0232     i2s_data->acp5x_base = adata->acp5x_base;
0233     runtime->private_data = i2s_data;
0234     return ret;
0235 }
0236 
0237 static int acp5x_dma_hw_params(struct snd_soc_component *component,
0238                    struct snd_pcm_substream *substream,
0239                    struct snd_pcm_hw_params *params)
0240 {
0241     struct i2s_stream_instance *rtd;
0242     struct snd_soc_pcm_runtime *prtd;
0243     struct snd_soc_card *card;
0244     struct acp5x_platform_info *pinfo;
0245     struct i2s_dev_data *adata;
0246     u64 size;
0247 
0248     prtd = asoc_substream_to_rtd(substream);
0249     card = prtd->card;
0250     pinfo = snd_soc_card_get_drvdata(card);
0251     adata = dev_get_drvdata(component->dev);
0252     rtd = substream->runtime->private_data;
0253 
0254     if (!rtd)
0255         return -EINVAL;
0256 
0257     if (pinfo) {
0258         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0259             rtd->i2s_instance = pinfo->play_i2s_instance;
0260             switch (rtd->i2s_instance) {
0261             case I2S_HS_INSTANCE:
0262                 adata->play_stream = substream;
0263                 break;
0264             case I2S_SP_INSTANCE:
0265             default:
0266                 adata->i2ssp_play_stream = substream;
0267             }
0268         } else {
0269             rtd->i2s_instance = pinfo->cap_i2s_instance;
0270             switch (rtd->i2s_instance) {
0271             case I2S_HS_INSTANCE:
0272                 adata->capture_stream = substream;
0273                 break;
0274             case I2S_SP_INSTANCE:
0275             default:
0276                 adata->i2ssp_capture_stream = substream;
0277             }
0278         }
0279     } else {
0280         dev_err(component->dev, "pinfo failed\n");
0281         return -EINVAL;
0282     }
0283     size = params_buffer_bytes(params);
0284     rtd->dma_addr = substream->runtime->dma_addr;
0285     rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
0286     config_acp5x_dma(rtd, substream->stream);
0287     return 0;
0288 }
0289 
0290 static snd_pcm_uframes_t acp5x_dma_pointer(struct snd_soc_component *component,
0291                        struct snd_pcm_substream *substream)
0292 {
0293     struct i2s_stream_instance *rtd;
0294     u32 pos;
0295     u32 buffersize;
0296     u64 bytescount;
0297 
0298     rtd = substream->runtime->private_data;
0299     buffersize = frames_to_bytes(substream->runtime,
0300                      substream->runtime->buffer_size);
0301     bytescount = acp_get_byte_count(rtd, substream->stream);
0302     if (bytescount > rtd->bytescount)
0303         bytescount -= rtd->bytescount;
0304     pos = do_div(bytescount, buffersize);
0305     return bytes_to_frames(substream->runtime, pos);
0306 }
0307 
0308 static int acp5x_dma_new(struct snd_soc_component *component,
0309              struct snd_soc_pcm_runtime *rtd)
0310 {
0311     struct device *parent = component->dev->parent;
0312 
0313     snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
0314                        parent, MIN_BUFFER, MAX_BUFFER);
0315     return 0;
0316 }
0317 
0318 static int acp5x_dma_close(struct snd_soc_component *component,
0319                struct snd_pcm_substream *substream)
0320 {
0321     struct snd_soc_pcm_runtime *prtd;
0322     struct i2s_dev_data *adata;
0323     struct i2s_stream_instance *ins;
0324 
0325     prtd = asoc_substream_to_rtd(substream);
0326     component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
0327     adata = dev_get_drvdata(component->dev);
0328     ins = substream->runtime->private_data;
0329     if (!ins)
0330         return -EINVAL;
0331     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0332         switch (ins->i2s_instance) {
0333         case I2S_HS_INSTANCE:
0334             adata->play_stream = NULL;
0335             break;
0336         case I2S_SP_INSTANCE:
0337         default:
0338             adata->i2ssp_play_stream = NULL;
0339         }
0340     } else {
0341         switch (ins->i2s_instance) {
0342         case I2S_HS_INSTANCE:
0343             adata->capture_stream = NULL;
0344             break;
0345         case I2S_SP_INSTANCE:
0346         default:
0347             adata->i2ssp_capture_stream = NULL;
0348         }
0349     }
0350     kfree(ins);
0351     return 0;
0352 }
0353 
0354 static const struct snd_soc_component_driver acp5x_i2s_component = {
0355     .name       = DRV_NAME,
0356     .open       = acp5x_dma_open,
0357     .close      = acp5x_dma_close,
0358     .hw_params  = acp5x_dma_hw_params,
0359     .pointer    = acp5x_dma_pointer,
0360     .pcm_construct  = acp5x_dma_new,
0361 };
0362 
0363 static int acp5x_audio_probe(struct platform_device *pdev)
0364 {
0365     struct resource *res;
0366     struct i2s_dev_data *adata;
0367     unsigned int irqflags;
0368     int status;
0369 
0370     if (!pdev->dev.platform_data) {
0371         dev_err(&pdev->dev, "platform_data not retrieved\n");
0372         return -ENODEV;
0373     }
0374     irqflags = *((unsigned int *)(pdev->dev.platform_data));
0375 
0376     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0377     if (!res) {
0378         dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
0379         return -ENODEV;
0380     }
0381 
0382     adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
0383     if (!adata)
0384         return -ENOMEM;
0385 
0386     adata->acp5x_base = devm_ioremap(&pdev->dev, res->start,
0387                      resource_size(res));
0388     if (!adata->acp5x_base)
0389         return -ENOMEM;
0390 
0391     status = platform_get_irq(pdev, 0);
0392     if (status < 0)
0393         return status;
0394     adata->i2s_irq = status;
0395 
0396     dev_set_drvdata(&pdev->dev, adata);
0397     status = devm_snd_soc_register_component(&pdev->dev,
0398                          &acp5x_i2s_component,
0399                          NULL, 0);
0400     if (status) {
0401         dev_err(&pdev->dev, "Fail to register acp i2s component\n");
0402         return status;
0403     }
0404     status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
0405                   irqflags, "ACP5x_I2S_IRQ", adata);
0406     if (status) {
0407         dev_err(&pdev->dev, "ACP5x I2S IRQ request failed\n");
0408         return status;
0409     }
0410     pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
0411     pm_runtime_use_autosuspend(&pdev->dev);
0412     pm_runtime_enable(&pdev->dev);
0413     pm_runtime_allow(&pdev->dev);
0414 
0415     return 0;
0416 }
0417 
0418 static int acp5x_audio_remove(struct platform_device *pdev)
0419 {
0420     pm_runtime_disable(&pdev->dev);
0421     return 0;
0422 }
0423 
0424 static int __maybe_unused acp5x_pcm_resume(struct device *dev)
0425 {
0426     struct i2s_dev_data *adata;
0427     struct i2s_stream_instance *rtd;
0428     u32 val;
0429 
0430     adata = dev_get_drvdata(dev);
0431 
0432     if (adata->play_stream && adata->play_stream->runtime) {
0433         rtd = adata->play_stream->runtime->private_data;
0434         config_acp5x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
0435         acp_writel((rtd->xfer_resolution  << 3), rtd->acp5x_base + ACP_HSTDM_ITER);
0436         if (adata->tdm_mode == TDM_ENABLE) {
0437             acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_HSTDM_TXFRMT);
0438             val = acp_readl(adata->acp5x_base + ACP_HSTDM_ITER);
0439             acp_writel(val | 0x2, adata->acp5x_base + ACP_HSTDM_ITER);
0440         }
0441     }
0442     if (adata->i2ssp_play_stream && adata->i2ssp_play_stream->runtime) {
0443         rtd = adata->i2ssp_play_stream->runtime->private_data;
0444         config_acp5x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
0445         acp_writel((rtd->xfer_resolution  << 3), rtd->acp5x_base + ACP_I2STDM_ITER);
0446         if (adata->tdm_mode == TDM_ENABLE) {
0447             acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_I2STDM_TXFRMT);
0448             val = acp_readl(adata->acp5x_base + ACP_I2STDM_ITER);
0449             acp_writel(val | 0x2, adata->acp5x_base + ACP_I2STDM_ITER);
0450         }
0451     }
0452 
0453     if (adata->capture_stream && adata->capture_stream->runtime) {
0454         rtd = adata->capture_stream->runtime->private_data;
0455         config_acp5x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
0456         acp_writel((rtd->xfer_resolution  << 3), rtd->acp5x_base + ACP_HSTDM_IRER);
0457         if (adata->tdm_mode == TDM_ENABLE) {
0458             acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_HSTDM_RXFRMT);
0459             val = acp_readl(adata->acp5x_base + ACP_HSTDM_IRER);
0460             acp_writel(val | 0x2, adata->acp5x_base + ACP_HSTDM_IRER);
0461         }
0462     }
0463     if (adata->i2ssp_capture_stream && adata->i2ssp_capture_stream->runtime) {
0464         rtd = adata->i2ssp_capture_stream->runtime->private_data;
0465         config_acp5x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
0466         acp_writel((rtd->xfer_resolution  << 3), rtd->acp5x_base + ACP_I2STDM_IRER);
0467         if (adata->tdm_mode == TDM_ENABLE) {
0468             acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_I2STDM_RXFRMT);
0469             val = acp_readl(adata->acp5x_base + ACP_I2STDM_IRER);
0470             acp_writel(val | 0x2, adata->acp5x_base + ACP_I2STDM_IRER);
0471         }
0472     }
0473     acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
0474     return 0;
0475 }
0476 
0477 static int __maybe_unused acp5x_pcm_suspend(struct device *dev)
0478 {
0479     struct i2s_dev_data *adata;
0480 
0481     adata = dev_get_drvdata(dev);
0482     acp_writel(0, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
0483     return 0;
0484 }
0485 
0486 static int __maybe_unused acp5x_pcm_runtime_resume(struct device *dev)
0487 {
0488     struct i2s_dev_data *adata;
0489 
0490     adata = dev_get_drvdata(dev);
0491     acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
0492     return 0;
0493 }
0494 
0495 static const struct dev_pm_ops acp5x_pm_ops = {
0496     SET_RUNTIME_PM_OPS(acp5x_pcm_suspend,
0497                acp5x_pcm_runtime_resume, NULL)
0498     SET_SYSTEM_SLEEP_PM_OPS(acp5x_pcm_suspend, acp5x_pcm_resume)
0499 };
0500 
0501 static struct platform_driver acp5x_dma_driver = {
0502     .probe = acp5x_audio_probe,
0503     .remove = acp5x_audio_remove,
0504     .driver = {
0505         .name = "acp5x_i2s_dma",
0506         .pm = &acp5x_pm_ops,
0507     },
0508 };
0509 
0510 module_platform_driver(acp5x_dma_driver);
0511 
0512 MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
0513 MODULE_DESCRIPTION("AMD ACP 5.x PCM Driver");
0514 MODULE_LICENSE("GPL v2");
0515 MODULE_ALIAS("platform:" DRV_NAME);
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