amd/renoir/rn_acp3x.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * AMD ALSA SoC PDM Driver
0004  *
0005  * Copyright 2020 Advanced Micro Devices, Inc.
0006  */
0007
0008 #include "rn_chip_offset_byte.h"
0009
0010 #define ACP_DEVS        3
0011 #define ACP_PHY_BASE_ADDRESS 0x1240000
0012 #define ACP_REG_START   0x1240000
0013 #define ACP_REG_END 0x1250200
0014
0015 #define ACP_DEVICE_ID 0x15E2
0016 #define ACP_POWER_ON 0x00
0017 #define ACP_POWER_ON_IN_PROGRESS 0x01
0018 #define ACP_POWER_OFF 0x02
0019 #define ACP_POWER_OFF_IN_PROGRESS 0x03
0020 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK   0x00010001
0021
0022 #define ACP_PGFSM_CNTL_POWER_ON_MASK    0x01
0023 #define ACP_PGFSM_CNTL_POWER_OFF_MASK   0x00
0024 #define ACP_PGFSM_STATUS_MASK           0x03
0025 #define ACP_POWERED_ON                  0x00
0026 #define ACP_POWER_ON_IN_PROGRESS        0x01
0027 #define ACP_POWERED_OFF                 0x02
0028 #define ACP_POWER_OFF_IN_PROGRESS       0x03
0029
0030 #define ACP_ERROR_MASK 0x20000000
0031 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
0032 #define PDM_DMA_STAT 0x10
0033 #define PDM_DMA_INTR_MASK  0x10000
0034 #define ACP_ERROR_STAT 29
0035 #define PDM_DECIMATION_FACTOR 0x2
0036 #define ACP_PDM_CLK_FREQ_MASK 0x07
0037 #define ACP_WOV_MISC_CTRL_MASK 0x10
0038 #define ACP_PDM_ENABLE 0x01
0039 #define ACP_PDM_DISABLE 0x00
0040 #define ACP_PDM_DMA_EN_STATUS 0x02
0041 #define TWO_CH 0x02
0042 #define DELAY_US 5
0043 #define ACP_COUNTER 20000
0044 /* time in ms for runtime suspend delay */
0045 #define ACP_SUSPEND_DELAY_MS    2000
0046
0047 #define ACP_SRAM_PTE_OFFSET 0x02050000
0048 #define PAGE_SIZE_4K_ENABLE     0x2
0049 #define MEM_WINDOW_START    0x4000000
0050
0051 #define CAPTURE_MIN_NUM_PERIODS     4
0052 #define CAPTURE_MAX_NUM_PERIODS     4
0053 #define CAPTURE_MAX_PERIOD_SIZE     8192
0054 #define CAPTURE_MIN_PERIOD_SIZE     4096
0055
0056 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
0057 #define MIN_BUFFER MAX_BUFFER
0058 #define ACP_DMIC_AUTO   -1
0059
0060 struct pdm_dev_data {
0061     u32 pdm_irq;
0062     void __iomem *acp_base;
0063     struct snd_pcm_substream *capture_stream;
0064 };
0065
0066 struct pdm_stream_instance {
0067     u16 num_pages;
0068     u16 channels;
0069     dma_addr_t dma_addr;
0070     u64 bytescount;
0071     void __iomem *acp_base;
0072 };
0073
0074 union acp_pdm_dma_count {
0075     struct {
0076     u32 low;
0077     u32 high;
0078     } bcount;
0079     u64 bytescount;
0080 };
0081
0082 static inline u32 rn_readl(void __iomem *base_addr)
0083 {
0084     return readl(base_addr - ACP_PHY_BASE_ADDRESS);
0085 }
0086
0087 static inline void rn_writel(u32 val, void __iomem *base_addr)
0088 {
0089     writel(val, base_addr - ACP_PHY_BASE_ADDRESS);
0090 }
0091
0092 /* Machine configuration */
0093 int snd_amd_acp_find_config(struct pci_dev *pci);