amd/raven/acp3x.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * AMD ALSA SoC PCM Driver
0004  *
0005  * Copyright 2016 Advanced Micro Devices, Inc.
0006  */
0007
0008 #include "chip_offset_byte.h"
0009 #include <sound/pcm.h>
0010 #define I2S_SP_INSTANCE                 0x01
0011 #define I2S_BT_INSTANCE                 0x02
0012
0013 #define TDM_ENABLE 1
0014 #define TDM_DISABLE 0
0015
0016 #define ACP3x_DEVS      4
0017 #define ACP3x_PHY_BASE_ADDRESS 0x1240000
0018 #define ACP3x_I2S_MODE  0
0019 #define ACP3x_REG_START 0x1240000
0020 #define ACP3x_REG_END   0x1250200
0021 #define ACP3x_I2STDM_REG_START  0x1242400
0022 #define ACP3x_I2STDM_REG_END    0x1242410
0023 #define ACP3x_BT_TDM_REG_START  0x1242800
0024 #define ACP3x_BT_TDM_REG_END    0x1242810
0025 #define I2S_MODE    0x04
0026 #define I2S_RX_THRESHOLD    27
0027 #define I2S_TX_THRESHOLD    28
0028 #define BT_TX_THRESHOLD 26
0029 #define BT_RX_THRESHOLD 25
0030 #define ACP_ERR_INTR_MASK   29
0031 #define ACP3x_POWER_ON 0x00
0032 #define ACP3x_POWER_ON_IN_PROGRESS 0x01
0033 #define ACP3x_POWER_OFF 0x02
0034 #define ACP3x_POWER_OFF_IN_PROGRESS 0x03
0035 #define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001
0036
0037 #define ACP_SRAM_PTE_OFFSET 0x02050000
0038 #define ACP_SRAM_SP_PB_PTE_OFFSET   0x0
0039 #define ACP_SRAM_SP_CP_PTE_OFFSET   0x100
0040 #define ACP_SRAM_BT_PB_PTE_OFFSET   0x200
0041 #define ACP_SRAM_BT_CP_PTE_OFFSET   0x300
0042 #define PAGE_SIZE_4K_ENABLE 0x2
0043 #define I2S_SP_TX_MEM_WINDOW_START  0x4000000
0044 #define I2S_SP_RX_MEM_WINDOW_START  0x4020000
0045 #define I2S_BT_TX_MEM_WINDOW_START  0x4040000
0046 #define I2S_BT_RX_MEM_WINDOW_START  0x4060000
0047
0048 #define SP_PB_FIFO_ADDR_OFFSET      0x500
0049 #define SP_CAPT_FIFO_ADDR_OFFSET    0x700
0050 #define BT_PB_FIFO_ADDR_OFFSET      0x900
0051 #define BT_CAPT_FIFO_ADDR_OFFSET    0xB00
0052 #define PLAYBACK_MIN_NUM_PERIODS    2
0053 #define PLAYBACK_MAX_NUM_PERIODS    8
0054 #define PLAYBACK_MAX_PERIOD_SIZE    8192
0055 #define PLAYBACK_MIN_PERIOD_SIZE    1024
0056 #define CAPTURE_MIN_NUM_PERIODS     2
0057 #define CAPTURE_MAX_NUM_PERIODS     8
0058 #define CAPTURE_MAX_PERIOD_SIZE     8192
0059 #define CAPTURE_MIN_PERIOD_SIZE     1024
0060
0061 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
0062 #define MIN_BUFFER MAX_BUFFER
0063 #define FIFO_SIZE 0x100
0064 #define DMA_SIZE 0x40
0065 #define FRM_LEN 0x100
0066
0067 #define SLOT_WIDTH_8 0x08
0068 #define SLOT_WIDTH_16 0x10
0069 #define SLOT_WIDTH_24 0x18
0070 #define SLOT_WIDTH_32 0x20
0071 #define ACP_PGFSM_CNTL_POWER_ON_MASK    0x01
0072 #define ACP_PGFSM_CNTL_POWER_OFF_MASK   0x00
0073 #define ACP_PGFSM_STATUS_MASK       0x03
0074 #define ACP_POWERED_ON          0x00
0075 #define ACP_POWER_ON_IN_PROGRESS    0x01
0076 #define ACP_POWERED_OFF         0x02
0077 #define ACP_POWER_OFF_IN_PROGRESS   0x03
0078
0079 #define ACP3x_ITER_IRER_SAMP_LEN_MASK   0x38
0080 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
0081
0082 struct acp3x_platform_info {
0083     u16 play_i2s_instance;
0084     u16 cap_i2s_instance;
0085     u16 capture_channel;
0086 };
0087
0088 struct i2s_dev_data {
0089     bool tdm_mode;
0090     int i2s_irq;
0091     u16 i2s_instance;
0092     u32 tdm_fmt;
0093     u32 substream_type;
0094     void __iomem *acp3x_base;
0095     struct snd_pcm_substream *play_stream;
0096     struct snd_pcm_substream *capture_stream;
0097     struct snd_pcm_substream *i2ssp_play_stream;
0098     struct snd_pcm_substream *i2ssp_capture_stream;
0099 };
0100
0101 struct i2s_stream_instance {
0102     u16 num_pages;
0103     u16 i2s_instance;
0104     u16 capture_channel;
0105     u16 direction;
0106     u16 channels;
0107     u32 xfer_resolution;
0108     u32 val;
0109     dma_addr_t dma_addr;
0110     u64 bytescount;
0111     void __iomem *acp3x_base;
0112 };
0113
0114 static inline u32 rv_readl(void __iomem *base_addr)
0115 {
0116     return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);
0117 }
0118
0119 static inline void rv_writel(u32 val, void __iomem *base_addr)
0120 {
0121     writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);
0122 }
0123
0124 static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
0125                             int direction)
0126 {
0127     u64 byte_count;
0128
0129     if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0130         switch (rtd->i2s_instance) {
0131         case I2S_BT_INSTANCE:
0132             byte_count = rv_readl(rtd->acp3x_base +
0133                     mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
0134             byte_count |= rv_readl(rtd->acp3x_base +
0135                     mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);
0136             break;
0137         case I2S_SP_INSTANCE:
0138         default:
0139             byte_count = rv_readl(rtd->acp3x_base +
0140                     mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
0141             byte_count |= rv_readl(rtd->acp3x_base +
0142                     mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
0143         }
0144
0145     } else {
0146         switch (rtd->i2s_instance) {
0147         case I2S_BT_INSTANCE:
0148             byte_count = rv_readl(rtd->acp3x_base +
0149                     mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
0150             byte_count |= rv_readl(rtd->acp3x_base +
0151                     mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);
0152             break;
0153         case I2S_SP_INSTANCE:
0154         default:
0155             byte_count = rv_readl(rtd->acp3x_base +
0156                     mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
0157             byte_count |= rv_readl(rtd->acp3x_base +
0158                     mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
0159         }
0160     }
0161     return byte_count;
0162 }