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0024 #ifndef ACP_2_2_ENUM_H
0025 #define ACP_2_2_ENUM_H
0026
0027 typedef enum DebugBlockId {
0028 DBG_BLOCK_ID_RESERVED = 0x0,
0029 DBG_BLOCK_ID_DBG = 0x1,
0030 DBG_BLOCK_ID_VMC = 0x2,
0031 DBG_BLOCK_ID_PDMA = 0x3,
0032 DBG_BLOCK_ID_CG = 0x4,
0033 DBG_BLOCK_ID_SRBM = 0x5,
0034 DBG_BLOCK_ID_GRBM = 0x6,
0035 DBG_BLOCK_ID_RLC = 0x7,
0036 DBG_BLOCK_ID_CSC = 0x8,
0037 DBG_BLOCK_ID_SEM = 0x9,
0038 DBG_BLOCK_ID_IH = 0xa,
0039 DBG_BLOCK_ID_SC = 0xb,
0040 DBG_BLOCK_ID_SQ = 0xc,
0041 DBG_BLOCK_ID_UVDU = 0xd,
0042 DBG_BLOCK_ID_SQA = 0xe,
0043 DBG_BLOCK_ID_SDMA0 = 0xf,
0044 DBG_BLOCK_ID_SDMA1 = 0x10,
0045 DBG_BLOCK_ID_SPIM = 0x11,
0046 DBG_BLOCK_ID_GDS = 0x12,
0047 DBG_BLOCK_ID_VC0 = 0x13,
0048 DBG_BLOCK_ID_VC1 = 0x14,
0049 DBG_BLOCK_ID_PA0 = 0x15,
0050 DBG_BLOCK_ID_PA1 = 0x16,
0051 DBG_BLOCK_ID_CP0 = 0x17,
0052 DBG_BLOCK_ID_CP1 = 0x18,
0053 DBG_BLOCK_ID_CP2 = 0x19,
0054 DBG_BLOCK_ID_XBR = 0x1a,
0055 DBG_BLOCK_ID_UVDM = 0x1b,
0056 DBG_BLOCK_ID_VGT0 = 0x1c,
0057 DBG_BLOCK_ID_VGT1 = 0x1d,
0058 DBG_BLOCK_ID_IA = 0x1e,
0059 DBG_BLOCK_ID_SXM0 = 0x1f,
0060 DBG_BLOCK_ID_SXM1 = 0x20,
0061 DBG_BLOCK_ID_SCT0 = 0x21,
0062 DBG_BLOCK_ID_SCT1 = 0x22,
0063 DBG_BLOCK_ID_SPM0 = 0x23,
0064 DBG_BLOCK_ID_SPM1 = 0x24,
0065 DBG_BLOCK_ID_UNUSED0 = 0x25,
0066 DBG_BLOCK_ID_UNUSED1 = 0x26,
0067 DBG_BLOCK_ID_TCAA = 0x27,
0068 DBG_BLOCK_ID_TCAB = 0x28,
0069 DBG_BLOCK_ID_TCCA = 0x29,
0070 DBG_BLOCK_ID_TCCB = 0x2a,
0071 DBG_BLOCK_ID_MCC0 = 0x2b,
0072 DBG_BLOCK_ID_MCC1 = 0x2c,
0073 DBG_BLOCK_ID_MCC2 = 0x2d,
0074 DBG_BLOCK_ID_MCC3 = 0x2e,
0075 DBG_BLOCK_ID_SXS0 = 0x2f,
0076 DBG_BLOCK_ID_SXS1 = 0x30,
0077 DBG_BLOCK_ID_SXS2 = 0x31,
0078 DBG_BLOCK_ID_SXS3 = 0x32,
0079 DBG_BLOCK_ID_SXS4 = 0x33,
0080 DBG_BLOCK_ID_SXS5 = 0x34,
0081 DBG_BLOCK_ID_SXS6 = 0x35,
0082 DBG_BLOCK_ID_SXS7 = 0x36,
0083 DBG_BLOCK_ID_SXS8 = 0x37,
0084 DBG_BLOCK_ID_SXS9 = 0x38,
0085 DBG_BLOCK_ID_BCI0 = 0x39,
0086 DBG_BLOCK_ID_BCI1 = 0x3a,
0087 DBG_BLOCK_ID_BCI2 = 0x3b,
0088 DBG_BLOCK_ID_BCI3 = 0x3c,
0089 DBG_BLOCK_ID_MCB = 0x3d,
0090 DBG_BLOCK_ID_UNUSED6 = 0x3e,
0091 DBG_BLOCK_ID_SQA00 = 0x3f,
0092 DBG_BLOCK_ID_SQA01 = 0x40,
0093 DBG_BLOCK_ID_SQA02 = 0x41,
0094 DBG_BLOCK_ID_SQA10 = 0x42,
0095 DBG_BLOCK_ID_SQA11 = 0x43,
0096 DBG_BLOCK_ID_SQA12 = 0x44,
0097 DBG_BLOCK_ID_UNUSED7 = 0x45,
0098 DBG_BLOCK_ID_UNUSED8 = 0x46,
0099 DBG_BLOCK_ID_SQB00 = 0x47,
0100 DBG_BLOCK_ID_SQB01 = 0x48,
0101 DBG_BLOCK_ID_SQB10 = 0x49,
0102 DBG_BLOCK_ID_SQB11 = 0x4a,
0103 DBG_BLOCK_ID_SQ00 = 0x4b,
0104 DBG_BLOCK_ID_SQ01 = 0x4c,
0105 DBG_BLOCK_ID_SQ10 = 0x4d,
0106 DBG_BLOCK_ID_SQ11 = 0x4e,
0107 DBG_BLOCK_ID_CB00 = 0x4f,
0108 DBG_BLOCK_ID_CB01 = 0x50,
0109 DBG_BLOCK_ID_CB02 = 0x51,
0110 DBG_BLOCK_ID_CB03 = 0x52,
0111 DBG_BLOCK_ID_CB04 = 0x53,
0112 DBG_BLOCK_ID_UNUSED9 = 0x54,
0113 DBG_BLOCK_ID_UNUSED10 = 0x55,
0114 DBG_BLOCK_ID_UNUSED11 = 0x56,
0115 DBG_BLOCK_ID_CB10 = 0x57,
0116 DBG_BLOCK_ID_CB11 = 0x58,
0117 DBG_BLOCK_ID_CB12 = 0x59,
0118 DBG_BLOCK_ID_CB13 = 0x5a,
0119 DBG_BLOCK_ID_CB14 = 0x5b,
0120 DBG_BLOCK_ID_UNUSED12 = 0x5c,
0121 DBG_BLOCK_ID_UNUSED13 = 0x5d,
0122 DBG_BLOCK_ID_UNUSED14 = 0x5e,
0123 DBG_BLOCK_ID_TCP0 = 0x5f,
0124 DBG_BLOCK_ID_TCP1 = 0x60,
0125 DBG_BLOCK_ID_TCP2 = 0x61,
0126 DBG_BLOCK_ID_TCP3 = 0x62,
0127 DBG_BLOCK_ID_TCP4 = 0x63,
0128 DBG_BLOCK_ID_TCP5 = 0x64,
0129 DBG_BLOCK_ID_TCP6 = 0x65,
0130 DBG_BLOCK_ID_TCP7 = 0x66,
0131 DBG_BLOCK_ID_TCP8 = 0x67,
0132 DBG_BLOCK_ID_TCP9 = 0x68,
0133 DBG_BLOCK_ID_TCP10 = 0x69,
0134 DBG_BLOCK_ID_TCP11 = 0x6a,
0135 DBG_BLOCK_ID_TCP12 = 0x6b,
0136 DBG_BLOCK_ID_TCP13 = 0x6c,
0137 DBG_BLOCK_ID_TCP14 = 0x6d,
0138 DBG_BLOCK_ID_TCP15 = 0x6e,
0139 DBG_BLOCK_ID_TCP16 = 0x6f,
0140 DBG_BLOCK_ID_TCP17 = 0x70,
0141 DBG_BLOCK_ID_TCP18 = 0x71,
0142 DBG_BLOCK_ID_TCP19 = 0x72,
0143 DBG_BLOCK_ID_TCP20 = 0x73,
0144 DBG_BLOCK_ID_TCP21 = 0x74,
0145 DBG_BLOCK_ID_TCP22 = 0x75,
0146 DBG_BLOCK_ID_TCP23 = 0x76,
0147 DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
0148 DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
0149 DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
0150 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
0151 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
0152 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
0153 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
0154 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
0155 DBG_BLOCK_ID_DB00 = 0x7f,
0156 DBG_BLOCK_ID_DB01 = 0x80,
0157 DBG_BLOCK_ID_DB02 = 0x81,
0158 DBG_BLOCK_ID_DB03 = 0x82,
0159 DBG_BLOCK_ID_DB04 = 0x83,
0160 DBG_BLOCK_ID_UNUSED15 = 0x84,
0161 DBG_BLOCK_ID_UNUSED16 = 0x85,
0162 DBG_BLOCK_ID_UNUSED17 = 0x86,
0163 DBG_BLOCK_ID_DB10 = 0x87,
0164 DBG_BLOCK_ID_DB11 = 0x88,
0165 DBG_BLOCK_ID_DB12 = 0x89,
0166 DBG_BLOCK_ID_DB13 = 0x8a,
0167 DBG_BLOCK_ID_DB14 = 0x8b,
0168 DBG_BLOCK_ID_UNUSED18 = 0x8c,
0169 DBG_BLOCK_ID_UNUSED19 = 0x8d,
0170 DBG_BLOCK_ID_UNUSED20 = 0x8e,
0171 DBG_BLOCK_ID_TCC0 = 0x8f,
0172 DBG_BLOCK_ID_TCC1 = 0x90,
0173 DBG_BLOCK_ID_TCC2 = 0x91,
0174 DBG_BLOCK_ID_TCC3 = 0x92,
0175 DBG_BLOCK_ID_TCC4 = 0x93,
0176 DBG_BLOCK_ID_TCC5 = 0x94,
0177 DBG_BLOCK_ID_TCC6 = 0x95,
0178 DBG_BLOCK_ID_TCC7 = 0x96,
0179 DBG_BLOCK_ID_SPS00 = 0x97,
0180 DBG_BLOCK_ID_SPS01 = 0x98,
0181 DBG_BLOCK_ID_SPS02 = 0x99,
0182 DBG_BLOCK_ID_SPS10 = 0x9a,
0183 DBG_BLOCK_ID_SPS11 = 0x9b,
0184 DBG_BLOCK_ID_SPS12 = 0x9c,
0185 DBG_BLOCK_ID_UNUSED21 = 0x9d,
0186 DBG_BLOCK_ID_UNUSED22 = 0x9e,
0187 DBG_BLOCK_ID_TA00 = 0x9f,
0188 DBG_BLOCK_ID_TA01 = 0xa0,
0189 DBG_BLOCK_ID_TA02 = 0xa1,
0190 DBG_BLOCK_ID_TA03 = 0xa2,
0191 DBG_BLOCK_ID_TA04 = 0xa3,
0192 DBG_BLOCK_ID_TA05 = 0xa4,
0193 DBG_BLOCK_ID_TA06 = 0xa5,
0194 DBG_BLOCK_ID_TA07 = 0xa6,
0195 DBG_BLOCK_ID_TA08 = 0xa7,
0196 DBG_BLOCK_ID_TA09 = 0xa8,
0197 DBG_BLOCK_ID_TA0A = 0xa9,
0198 DBG_BLOCK_ID_TA0B = 0xaa,
0199 DBG_BLOCK_ID_UNUSED23 = 0xab,
0200 DBG_BLOCK_ID_UNUSED24 = 0xac,
0201 DBG_BLOCK_ID_UNUSED25 = 0xad,
0202 DBG_BLOCK_ID_UNUSED26 = 0xae,
0203 DBG_BLOCK_ID_TA10 = 0xaf,
0204 DBG_BLOCK_ID_TA11 = 0xb0,
0205 DBG_BLOCK_ID_TA12 = 0xb1,
0206 DBG_BLOCK_ID_TA13 = 0xb2,
0207 DBG_BLOCK_ID_TA14 = 0xb3,
0208 DBG_BLOCK_ID_TA15 = 0xb4,
0209 DBG_BLOCK_ID_TA16 = 0xb5,
0210 DBG_BLOCK_ID_TA17 = 0xb6,
0211 DBG_BLOCK_ID_TA18 = 0xb7,
0212 DBG_BLOCK_ID_TA19 = 0xb8,
0213 DBG_BLOCK_ID_TA1A = 0xb9,
0214 DBG_BLOCK_ID_TA1B = 0xba,
0215 DBG_BLOCK_ID_UNUSED27 = 0xbb,
0216 DBG_BLOCK_ID_UNUSED28 = 0xbc,
0217 DBG_BLOCK_ID_UNUSED29 = 0xbd,
0218 DBG_BLOCK_ID_UNUSED30 = 0xbe,
0219 DBG_BLOCK_ID_TD00 = 0xbf,
0220 DBG_BLOCK_ID_TD01 = 0xc0,
0221 DBG_BLOCK_ID_TD02 = 0xc1,
0222 DBG_BLOCK_ID_TD03 = 0xc2,
0223 DBG_BLOCK_ID_TD04 = 0xc3,
0224 DBG_BLOCK_ID_TD05 = 0xc4,
0225 DBG_BLOCK_ID_TD06 = 0xc5,
0226 DBG_BLOCK_ID_TD07 = 0xc6,
0227 DBG_BLOCK_ID_TD08 = 0xc7,
0228 DBG_BLOCK_ID_TD09 = 0xc8,
0229 DBG_BLOCK_ID_TD0A = 0xc9,
0230 DBG_BLOCK_ID_TD0B = 0xca,
0231 DBG_BLOCK_ID_UNUSED31 = 0xcb,
0232 DBG_BLOCK_ID_UNUSED32 = 0xcc,
0233 DBG_BLOCK_ID_UNUSED33 = 0xcd,
0234 DBG_BLOCK_ID_UNUSED34 = 0xce,
0235 DBG_BLOCK_ID_TD10 = 0xcf,
0236 DBG_BLOCK_ID_TD11 = 0xd0,
0237 DBG_BLOCK_ID_TD12 = 0xd1,
0238 DBG_BLOCK_ID_TD13 = 0xd2,
0239 DBG_BLOCK_ID_TD14 = 0xd3,
0240 DBG_BLOCK_ID_TD15 = 0xd4,
0241 DBG_BLOCK_ID_TD16 = 0xd5,
0242 DBG_BLOCK_ID_TD17 = 0xd6,
0243 DBG_BLOCK_ID_TD18 = 0xd7,
0244 DBG_BLOCK_ID_TD19 = 0xd8,
0245 DBG_BLOCK_ID_TD1A = 0xd9,
0246 DBG_BLOCK_ID_TD1B = 0xda,
0247 DBG_BLOCK_ID_UNUSED35 = 0xdb,
0248 DBG_BLOCK_ID_UNUSED36 = 0xdc,
0249 DBG_BLOCK_ID_UNUSED37 = 0xdd,
0250 DBG_BLOCK_ID_UNUSED38 = 0xde,
0251 DBG_BLOCK_ID_LDS00 = 0xdf,
0252 DBG_BLOCK_ID_LDS01 = 0xe0,
0253 DBG_BLOCK_ID_LDS02 = 0xe1,
0254 DBG_BLOCK_ID_LDS03 = 0xe2,
0255 DBG_BLOCK_ID_LDS04 = 0xe3,
0256 DBG_BLOCK_ID_LDS05 = 0xe4,
0257 DBG_BLOCK_ID_LDS06 = 0xe5,
0258 DBG_BLOCK_ID_LDS07 = 0xe6,
0259 DBG_BLOCK_ID_LDS08 = 0xe7,
0260 DBG_BLOCK_ID_LDS09 = 0xe8,
0261 DBG_BLOCK_ID_LDS0A = 0xe9,
0262 DBG_BLOCK_ID_LDS0B = 0xea,
0263 DBG_BLOCK_ID_UNUSED39 = 0xeb,
0264 DBG_BLOCK_ID_UNUSED40 = 0xec,
0265 DBG_BLOCK_ID_UNUSED41 = 0xed,
0266 DBG_BLOCK_ID_UNUSED42 = 0xee,
0267 DBG_BLOCK_ID_LDS10 = 0xef,
0268 DBG_BLOCK_ID_LDS11 = 0xf0,
0269 DBG_BLOCK_ID_LDS12 = 0xf1,
0270 DBG_BLOCK_ID_LDS13 = 0xf2,
0271 DBG_BLOCK_ID_LDS14 = 0xf3,
0272 DBG_BLOCK_ID_LDS15 = 0xf4,
0273 DBG_BLOCK_ID_LDS16 = 0xf5,
0274 DBG_BLOCK_ID_LDS17 = 0xf6,
0275 DBG_BLOCK_ID_LDS18 = 0xf7,
0276 DBG_BLOCK_ID_LDS19 = 0xf8,
0277 DBG_BLOCK_ID_LDS1A = 0xf9,
0278 DBG_BLOCK_ID_LDS1B = 0xfa,
0279 DBG_BLOCK_ID_UNUSED43 = 0xfb,
0280 DBG_BLOCK_ID_UNUSED44 = 0xfc,
0281 DBG_BLOCK_ID_UNUSED45 = 0xfd,
0282 DBG_BLOCK_ID_UNUSED46 = 0xfe,
0283 } DebugBlockId;
0284 typedef enum DebugBlockId_BY2 {
0285 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
0286 DBG_BLOCK_ID_VMC_BY2 = 0x1,
0287 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
0288 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
0289 DBG_BLOCK_ID_CSC_BY2 = 0x4,
0290 DBG_BLOCK_ID_IH_BY2 = 0x5,
0291 DBG_BLOCK_ID_SQ_BY2 = 0x6,
0292 DBG_BLOCK_ID_UVD_BY2 = 0x7,
0293 DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
0294 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
0295 DBG_BLOCK_ID_VC0_BY2 = 0xa,
0296 DBG_BLOCK_ID_PA_BY2 = 0xb,
0297 DBG_BLOCK_ID_CP0_BY2 = 0xc,
0298 DBG_BLOCK_ID_CP2_BY2 = 0xd,
0299 DBG_BLOCK_ID_PC0_BY2 = 0xe,
0300 DBG_BLOCK_ID_BCI0_BY2 = 0xf,
0301 DBG_BLOCK_ID_SXM0_BY2 = 0x10,
0302 DBG_BLOCK_ID_SCT0_BY2 = 0x11,
0303 DBG_BLOCK_ID_SPM0_BY2 = 0x12,
0304 DBG_BLOCK_ID_BCI2_BY2 = 0x13,
0305 DBG_BLOCK_ID_TCA_BY2 = 0x14,
0306 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
0307 DBG_BLOCK_ID_MCC_BY2 = 0x16,
0308 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
0309 DBG_BLOCK_ID_MCD_BY2 = 0x18,
0310 DBG_BLOCK_ID_MCD2_BY2 = 0x19,
0311 DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
0312 DBG_BLOCK_ID_MCB_BY2 = 0x1b,
0313 DBG_BLOCK_ID_SQA_BY2 = 0x1c,
0314 DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
0315 DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
0316 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
0317 DBG_BLOCK_ID_SQB_BY2 = 0x20,
0318 DBG_BLOCK_ID_SQB10_BY2 = 0x21,
0319 DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
0320 DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
0321 DBG_BLOCK_ID_CB_BY2 = 0x24,
0322 DBG_BLOCK_ID_CB02_BY2 = 0x25,
0323 DBG_BLOCK_ID_CB10_BY2 = 0x26,
0324 DBG_BLOCK_ID_CB12_BY2 = 0x27,
0325 DBG_BLOCK_ID_SXS_BY2 = 0x28,
0326 DBG_BLOCK_ID_SXS2_BY2 = 0x29,
0327 DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
0328 DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
0329 DBG_BLOCK_ID_DB_BY2 = 0x2c,
0330 DBG_BLOCK_ID_DB02_BY2 = 0x2d,
0331 DBG_BLOCK_ID_DB10_BY2 = 0x2e,
0332 DBG_BLOCK_ID_DB12_BY2 = 0x2f,
0333 DBG_BLOCK_ID_TCP_BY2 = 0x30,
0334 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
0335 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
0336 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
0337 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
0338 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
0339 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
0340 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
0341 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
0342 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
0343 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
0344 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
0345 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
0346 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
0347 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
0348 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
0349 DBG_BLOCK_ID_TCC_BY2 = 0x40,
0350 DBG_BLOCK_ID_TCC2_BY2 = 0x41,
0351 DBG_BLOCK_ID_TCC4_BY2 = 0x42,
0352 DBG_BLOCK_ID_TCC6_BY2 = 0x43,
0353 DBG_BLOCK_ID_SPS_BY2 = 0x44,
0354 DBG_BLOCK_ID_SPS02_BY2 = 0x45,
0355 DBG_BLOCK_ID_SPS11_BY2 = 0x46,
0356 DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
0357 DBG_BLOCK_ID_TA_BY2 = 0x48,
0358 DBG_BLOCK_ID_TA02_BY2 = 0x49,
0359 DBG_BLOCK_ID_TA04_BY2 = 0x4a,
0360 DBG_BLOCK_ID_TA06_BY2 = 0x4b,
0361 DBG_BLOCK_ID_TA08_BY2 = 0x4c,
0362 DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
0363 DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
0364 DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
0365 DBG_BLOCK_ID_TA10_BY2 = 0x50,
0366 DBG_BLOCK_ID_TA12_BY2 = 0x51,
0367 DBG_BLOCK_ID_TA14_BY2 = 0x52,
0368 DBG_BLOCK_ID_TA16_BY2 = 0x53,
0369 DBG_BLOCK_ID_TA18_BY2 = 0x54,
0370 DBG_BLOCK_ID_TA1A_BY2 = 0x55,
0371 DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
0372 DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
0373 DBG_BLOCK_ID_TD_BY2 = 0x58,
0374 DBG_BLOCK_ID_TD02_BY2 = 0x59,
0375 DBG_BLOCK_ID_TD04_BY2 = 0x5a,
0376 DBG_BLOCK_ID_TD06_BY2 = 0x5b,
0377 DBG_BLOCK_ID_TD08_BY2 = 0x5c,
0378 DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
0379 DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
0380 DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
0381 DBG_BLOCK_ID_TD10_BY2 = 0x60,
0382 DBG_BLOCK_ID_TD12_BY2 = 0x61,
0383 DBG_BLOCK_ID_TD14_BY2 = 0x62,
0384 DBG_BLOCK_ID_TD16_BY2 = 0x63,
0385 DBG_BLOCK_ID_TD18_BY2 = 0x64,
0386 DBG_BLOCK_ID_TD1A_BY2 = 0x65,
0387 DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
0388 DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
0389 DBG_BLOCK_ID_LDS_BY2 = 0x68,
0390 DBG_BLOCK_ID_LDS02_BY2 = 0x69,
0391 DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
0392 DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
0393 DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
0394 DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
0395 DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
0396 DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
0397 DBG_BLOCK_ID_LDS10_BY2 = 0x70,
0398 DBG_BLOCK_ID_LDS12_BY2 = 0x71,
0399 DBG_BLOCK_ID_LDS14_BY2 = 0x72,
0400 DBG_BLOCK_ID_LDS16_BY2 = 0x73,
0401 DBG_BLOCK_ID_LDS18_BY2 = 0x74,
0402 DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
0403 DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
0404 DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
0405 } DebugBlockId_BY2;
0406 typedef enum DebugBlockId_BY4 {
0407 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
0408 DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
0409 DBG_BLOCK_ID_CSC_BY4 = 0x2,
0410 DBG_BLOCK_ID_SQ_BY4 = 0x3,
0411 DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
0412 DBG_BLOCK_ID_VC0_BY4 = 0x5,
0413 DBG_BLOCK_ID_CP0_BY4 = 0x6,
0414 DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
0415 DBG_BLOCK_ID_SXM0_BY4 = 0x8,
0416 DBG_BLOCK_ID_SPM0_BY4 = 0x9,
0417 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
0418 DBG_BLOCK_ID_MCC_BY4 = 0xb,
0419 DBG_BLOCK_ID_MCD_BY4 = 0xc,
0420 DBG_BLOCK_ID_MCD4_BY4 = 0xd,
0421 DBG_BLOCK_ID_SQA_BY4 = 0xe,
0422 DBG_BLOCK_ID_SQA11_BY4 = 0xf,
0423 DBG_BLOCK_ID_SQB_BY4 = 0x10,
0424 DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
0425 DBG_BLOCK_ID_CB_BY4 = 0x12,
0426 DBG_BLOCK_ID_CB10_BY4 = 0x13,
0427 DBG_BLOCK_ID_SXS_BY4 = 0x14,
0428 DBG_BLOCK_ID_SXS4_BY4 = 0x15,
0429 DBG_BLOCK_ID_DB_BY4 = 0x16,
0430 DBG_BLOCK_ID_DB10_BY4 = 0x17,
0431 DBG_BLOCK_ID_TCP_BY4 = 0x18,
0432 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
0433 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
0434 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
0435 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
0436 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
0437 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
0438 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
0439 DBG_BLOCK_ID_TCC_BY4 = 0x20,
0440 DBG_BLOCK_ID_TCC4_BY4 = 0x21,
0441 DBG_BLOCK_ID_SPS_BY4 = 0x22,
0442 DBG_BLOCK_ID_SPS11_BY4 = 0x23,
0443 DBG_BLOCK_ID_TA_BY4 = 0x24,
0444 DBG_BLOCK_ID_TA04_BY4 = 0x25,
0445 DBG_BLOCK_ID_TA08_BY4 = 0x26,
0446 DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
0447 DBG_BLOCK_ID_TA10_BY4 = 0x28,
0448 DBG_BLOCK_ID_TA14_BY4 = 0x29,
0449 DBG_BLOCK_ID_TA18_BY4 = 0x2a,
0450 DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
0451 DBG_BLOCK_ID_TD_BY4 = 0x2c,
0452 DBG_BLOCK_ID_TD04_BY4 = 0x2d,
0453 DBG_BLOCK_ID_TD08_BY4 = 0x2e,
0454 DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
0455 DBG_BLOCK_ID_TD10_BY4 = 0x30,
0456 DBG_BLOCK_ID_TD14_BY4 = 0x31,
0457 DBG_BLOCK_ID_TD18_BY4 = 0x32,
0458 DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
0459 DBG_BLOCK_ID_LDS_BY4 = 0x34,
0460 DBG_BLOCK_ID_LDS04_BY4 = 0x35,
0461 DBG_BLOCK_ID_LDS08_BY4 = 0x36,
0462 DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
0463 DBG_BLOCK_ID_LDS10_BY4 = 0x38,
0464 DBG_BLOCK_ID_LDS14_BY4 = 0x39,
0465 DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
0466 DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
0467 } DebugBlockId_BY4;
0468 typedef enum DebugBlockId_BY8 {
0469 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
0470 DBG_BLOCK_ID_CSC_BY8 = 0x1,
0471 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
0472 DBG_BLOCK_ID_CP0_BY8 = 0x3,
0473 DBG_BLOCK_ID_SXM0_BY8 = 0x4,
0474 DBG_BLOCK_ID_TCA_BY8 = 0x5,
0475 DBG_BLOCK_ID_MCD_BY8 = 0x6,
0476 DBG_BLOCK_ID_SQA_BY8 = 0x7,
0477 DBG_BLOCK_ID_SQB_BY8 = 0x8,
0478 DBG_BLOCK_ID_CB_BY8 = 0x9,
0479 DBG_BLOCK_ID_SXS_BY8 = 0xa,
0480 DBG_BLOCK_ID_DB_BY8 = 0xb,
0481 DBG_BLOCK_ID_TCP_BY8 = 0xc,
0482 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
0483 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
0484 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
0485 DBG_BLOCK_ID_TCC_BY8 = 0x10,
0486 DBG_BLOCK_ID_SPS_BY8 = 0x11,
0487 DBG_BLOCK_ID_TA_BY8 = 0x12,
0488 DBG_BLOCK_ID_TA08_BY8 = 0x13,
0489 DBG_BLOCK_ID_TA10_BY8 = 0x14,
0490 DBG_BLOCK_ID_TA18_BY8 = 0x15,
0491 DBG_BLOCK_ID_TD_BY8 = 0x16,
0492 DBG_BLOCK_ID_TD08_BY8 = 0x17,
0493 DBG_BLOCK_ID_TD10_BY8 = 0x18,
0494 DBG_BLOCK_ID_TD18_BY8 = 0x19,
0495 DBG_BLOCK_ID_LDS_BY8 = 0x1a,
0496 DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
0497 DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
0498 DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
0499 } DebugBlockId_BY8;
0500 typedef enum DebugBlockId_BY16 {
0501 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
0502 DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
0503 DBG_BLOCK_ID_SXM_BY16 = 0x2,
0504 DBG_BLOCK_ID_MCD_BY16 = 0x3,
0505 DBG_BLOCK_ID_SQB_BY16 = 0x4,
0506 DBG_BLOCK_ID_SXS_BY16 = 0x5,
0507 DBG_BLOCK_ID_TCP_BY16 = 0x6,
0508 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
0509 DBG_BLOCK_ID_TCC_BY16 = 0x8,
0510 DBG_BLOCK_ID_TA_BY16 = 0x9,
0511 DBG_BLOCK_ID_TA10_BY16 = 0xa,
0512 DBG_BLOCK_ID_TD_BY16 = 0xb,
0513 DBG_BLOCK_ID_TD10_BY16 = 0xc,
0514 DBG_BLOCK_ID_LDS_BY16 = 0xd,
0515 DBG_BLOCK_ID_LDS10_BY16 = 0xe,
0516 } DebugBlockId_BY16;
0517 typedef enum SurfaceEndian {
0518 ENDIAN_NONE = 0x0,
0519 ENDIAN_8IN16 = 0x1,
0520 ENDIAN_8IN32 = 0x2,
0521 ENDIAN_8IN64 = 0x3,
0522 } SurfaceEndian;
0523 typedef enum ArrayMode {
0524 ARRAY_LINEAR_GENERAL = 0x0,
0525 ARRAY_LINEAR_ALIGNED = 0x1,
0526 ARRAY_1D_TILED_THIN1 = 0x2,
0527 ARRAY_1D_TILED_THICK = 0x3,
0528 ARRAY_2D_TILED_THIN1 = 0x4,
0529 ARRAY_PRT_TILED_THIN1 = 0x5,
0530 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
0531 ARRAY_2D_TILED_THICK = 0x7,
0532 ARRAY_2D_TILED_XTHICK = 0x8,
0533 ARRAY_PRT_TILED_THICK = 0x9,
0534 ARRAY_PRT_2D_TILED_THICK = 0xa,
0535 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
0536 ARRAY_3D_TILED_THIN1 = 0xc,
0537 ARRAY_3D_TILED_THICK = 0xd,
0538 ARRAY_3D_TILED_XTHICK = 0xe,
0539 ARRAY_PRT_3D_TILED_THICK = 0xf,
0540 } ArrayMode;
0541 typedef enum PipeTiling {
0542 CONFIG_1_PIPE = 0x0,
0543 CONFIG_2_PIPE = 0x1,
0544 CONFIG_4_PIPE = 0x2,
0545 CONFIG_8_PIPE = 0x3,
0546 } PipeTiling;
0547 typedef enum BankTiling {
0548 CONFIG_4_BANK = 0x0,
0549 CONFIG_8_BANK = 0x1,
0550 } BankTiling;
0551 typedef enum GroupInterleave {
0552 CONFIG_256B_GROUP = 0x0,
0553 CONFIG_512B_GROUP = 0x1,
0554 } GroupInterleave;
0555 typedef enum RowTiling {
0556 CONFIG_1KB_ROW = 0x0,
0557 CONFIG_2KB_ROW = 0x1,
0558 CONFIG_4KB_ROW = 0x2,
0559 CONFIG_8KB_ROW = 0x3,
0560 CONFIG_1KB_ROW_OPT = 0x4,
0561 CONFIG_2KB_ROW_OPT = 0x5,
0562 CONFIG_4KB_ROW_OPT = 0x6,
0563 CONFIG_8KB_ROW_OPT = 0x7,
0564 } RowTiling;
0565 typedef enum BankSwapBytes {
0566 CONFIG_128B_SWAPS = 0x0,
0567 CONFIG_256B_SWAPS = 0x1,
0568 CONFIG_512B_SWAPS = 0x2,
0569 CONFIG_1KB_SWAPS = 0x3,
0570 } BankSwapBytes;
0571 typedef enum SampleSplitBytes {
0572 CONFIG_1KB_SPLIT = 0x0,
0573 CONFIG_2KB_SPLIT = 0x1,
0574 CONFIG_4KB_SPLIT = 0x2,
0575 CONFIG_8KB_SPLIT = 0x3,
0576 } SampleSplitBytes;
0577 typedef enum NumPipes {
0578 ADDR_CONFIG_1_PIPE = 0x0,
0579 ADDR_CONFIG_2_PIPE = 0x1,
0580 ADDR_CONFIG_4_PIPE = 0x2,
0581 ADDR_CONFIG_8_PIPE = 0x3,
0582 } NumPipes;
0583 typedef enum PipeInterleaveSize {
0584 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
0585 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
0586 } PipeInterleaveSize;
0587 typedef enum BankInterleaveSize {
0588 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
0589 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
0590 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
0591 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
0592 } BankInterleaveSize;
0593 typedef enum NumShaderEngines {
0594 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
0595 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
0596 } NumShaderEngines;
0597 typedef enum ShaderEngineTileSize {
0598 ADDR_CONFIG_SE_TILE_16 = 0x0,
0599 ADDR_CONFIG_SE_TILE_32 = 0x1,
0600 } ShaderEngineTileSize;
0601 typedef enum NumGPUs {
0602 ADDR_CONFIG_1_GPU = 0x0,
0603 ADDR_CONFIG_2_GPU = 0x1,
0604 ADDR_CONFIG_4_GPU = 0x2,
0605 } NumGPUs;
0606 typedef enum MultiGPUTileSize {
0607 ADDR_CONFIG_GPU_TILE_16 = 0x0,
0608 ADDR_CONFIG_GPU_TILE_32 = 0x1,
0609 ADDR_CONFIG_GPU_TILE_64 = 0x2,
0610 ADDR_CONFIG_GPU_TILE_128 = 0x3,
0611 } MultiGPUTileSize;
0612 typedef enum RowSize {
0613 ADDR_CONFIG_1KB_ROW = 0x0,
0614 ADDR_CONFIG_2KB_ROW = 0x1,
0615 ADDR_CONFIG_4KB_ROW = 0x2,
0616 } RowSize;
0617 typedef enum NumLowerPipes {
0618 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
0619 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
0620 } NumLowerPipes;
0621 typedef enum ColorTransform {
0622 DCC_CT_AUTO = 0x0,
0623 DCC_CT_NONE = 0x1,
0624 ABGR_TO_A_BG_G_RB = 0x2,
0625 BGRA_TO_BG_G_RB_A = 0x3,
0626 } ColorTransform;
0627 typedef enum CompareRef {
0628 REF_NEVER = 0x0,
0629 REF_LESS = 0x1,
0630 REF_EQUAL = 0x2,
0631 REF_LEQUAL = 0x3,
0632 REF_GREATER = 0x4,
0633 REF_NOTEQUAL = 0x5,
0634 REF_GEQUAL = 0x6,
0635 REF_ALWAYS = 0x7,
0636 } CompareRef;
0637 typedef enum ReadSize {
0638 READ_256_BITS = 0x0,
0639 READ_512_BITS = 0x1,
0640 } ReadSize;
0641 typedef enum DepthFormat {
0642 DEPTH_INVALID = 0x0,
0643 DEPTH_16 = 0x1,
0644 DEPTH_X8_24 = 0x2,
0645 DEPTH_8_24 = 0x3,
0646 DEPTH_X8_24_FLOAT = 0x4,
0647 DEPTH_8_24_FLOAT = 0x5,
0648 DEPTH_32_FLOAT = 0x6,
0649 DEPTH_X24_8_32_FLOAT = 0x7,
0650 } DepthFormat;
0651 typedef enum ZFormat {
0652 Z_INVALID = 0x0,
0653 Z_16 = 0x1,
0654 Z_24 = 0x2,
0655 Z_32_FLOAT = 0x3,
0656 } ZFormat;
0657 typedef enum StencilFormat {
0658 STENCIL_INVALID = 0x0,
0659 STENCIL_8 = 0x1,
0660 } StencilFormat;
0661 typedef enum CmaskMode {
0662 CMASK_CLEAR_NONE = 0x0,
0663 CMASK_CLEAR_ONE = 0x1,
0664 CMASK_CLEAR_ALL = 0x2,
0665 CMASK_ANY_EXPANDED = 0x3,
0666 CMASK_ALPHA0_FRAG1 = 0x4,
0667 CMASK_ALPHA0_FRAG2 = 0x5,
0668 CMASK_ALPHA0_FRAG4 = 0x6,
0669 CMASK_ALPHA0_FRAGS = 0x7,
0670 CMASK_ALPHA1_FRAG1 = 0x8,
0671 CMASK_ALPHA1_FRAG2 = 0x9,
0672 CMASK_ALPHA1_FRAG4 = 0xa,
0673 CMASK_ALPHA1_FRAGS = 0xb,
0674 CMASK_ALPHAX_FRAG1 = 0xc,
0675 CMASK_ALPHAX_FRAG2 = 0xd,
0676 CMASK_ALPHAX_FRAG4 = 0xe,
0677 CMASK_ALPHAX_FRAGS = 0xf,
0678 } CmaskMode;
0679 typedef enum QuadExportFormat {
0680 EXPORT_UNUSED = 0x0,
0681 EXPORT_32_R = 0x1,
0682 EXPORT_32_GR = 0x2,
0683 EXPORT_32_AR = 0x3,
0684 EXPORT_FP16_ABGR = 0x4,
0685 EXPORT_UNSIGNED16_ABGR = 0x5,
0686 EXPORT_SIGNED16_ABGR = 0x6,
0687 EXPORT_32_ABGR = 0x7,
0688 } QuadExportFormat;
0689 typedef enum QuadExportFormatOld {
0690 EXPORT_4P_32BPC_ABGR = 0x0,
0691 EXPORT_4P_16BPC_ABGR = 0x1,
0692 EXPORT_4P_32BPC_GR = 0x2,
0693 EXPORT_4P_32BPC_AR = 0x3,
0694 EXPORT_2P_32BPC_ABGR = 0x4,
0695 EXPORT_8P_32BPC_R = 0x5,
0696 } QuadExportFormatOld;
0697 typedef enum ColorFormat {
0698 COLOR_INVALID = 0x0,
0699 COLOR_8 = 0x1,
0700 COLOR_16 = 0x2,
0701 COLOR_8_8 = 0x3,
0702 COLOR_32 = 0x4,
0703 COLOR_16_16 = 0x5,
0704 COLOR_10_11_11 = 0x6,
0705 COLOR_11_11_10 = 0x7,
0706 COLOR_10_10_10_2 = 0x8,
0707 COLOR_2_10_10_10 = 0x9,
0708 COLOR_8_8_8_8 = 0xa,
0709 COLOR_32_32 = 0xb,
0710 COLOR_16_16_16_16 = 0xc,
0711 COLOR_RESERVED_13 = 0xd,
0712 COLOR_32_32_32_32 = 0xe,
0713 COLOR_RESERVED_15 = 0xf,
0714 COLOR_5_6_5 = 0x10,
0715 COLOR_1_5_5_5 = 0x11,
0716 COLOR_5_5_5_1 = 0x12,
0717 COLOR_4_4_4_4 = 0x13,
0718 COLOR_8_24 = 0x14,
0719 COLOR_24_8 = 0x15,
0720 COLOR_X24_8_32_FLOAT = 0x16,
0721 COLOR_RESERVED_23 = 0x17,
0722 } ColorFormat;
0723 typedef enum SurfaceFormat {
0724 FMT_INVALID = 0x0,
0725 FMT_8 = 0x1,
0726 FMT_16 = 0x2,
0727 FMT_8_8 = 0x3,
0728 FMT_32 = 0x4,
0729 FMT_16_16 = 0x5,
0730 FMT_10_11_11 = 0x6,
0731 FMT_11_11_10 = 0x7,
0732 FMT_10_10_10_2 = 0x8,
0733 FMT_2_10_10_10 = 0x9,
0734 FMT_8_8_8_8 = 0xa,
0735 FMT_32_32 = 0xb,
0736 FMT_16_16_16_16 = 0xc,
0737 FMT_32_32_32 = 0xd,
0738 FMT_32_32_32_32 = 0xe,
0739 FMT_RESERVED_4 = 0xf,
0740 FMT_5_6_5 = 0x10,
0741 FMT_1_5_5_5 = 0x11,
0742 FMT_5_5_5_1 = 0x12,
0743 FMT_4_4_4_4 = 0x13,
0744 FMT_8_24 = 0x14,
0745 FMT_24_8 = 0x15,
0746 FMT_X24_8_32_FLOAT = 0x16,
0747 FMT_RESERVED_33 = 0x17,
0748 FMT_11_11_10_FLOAT = 0x18,
0749 FMT_16_FLOAT = 0x19,
0750 FMT_32_FLOAT = 0x1a,
0751 FMT_16_16_FLOAT = 0x1b,
0752 FMT_8_24_FLOAT = 0x1c,
0753 FMT_24_8_FLOAT = 0x1d,
0754 FMT_32_32_FLOAT = 0x1e,
0755 FMT_10_11_11_FLOAT = 0x1f,
0756 FMT_16_16_16_16_FLOAT = 0x20,
0757 FMT_3_3_2 = 0x21,
0758 FMT_6_5_5 = 0x22,
0759 FMT_32_32_32_32_FLOAT = 0x23,
0760 FMT_RESERVED_36 = 0x24,
0761 FMT_1 = 0x25,
0762 FMT_1_REVERSED = 0x26,
0763 FMT_GB_GR = 0x27,
0764 FMT_BG_RG = 0x28,
0765 FMT_32_AS_8 = 0x29,
0766 FMT_32_AS_8_8 = 0x2a,
0767 FMT_5_9_9_9_SHAREDEXP = 0x2b,
0768 FMT_8_8_8 = 0x2c,
0769 FMT_16_16_16 = 0x2d,
0770 FMT_16_16_16_FLOAT = 0x2e,
0771 FMT_4_4 = 0x2f,
0772 FMT_32_32_32_FLOAT = 0x30,
0773 FMT_BC1 = 0x31,
0774 FMT_BC2 = 0x32,
0775 FMT_BC3 = 0x33,
0776 FMT_BC4 = 0x34,
0777 FMT_BC5 = 0x35,
0778 FMT_BC6 = 0x36,
0779 FMT_BC7 = 0x37,
0780 FMT_32_AS_32_32_32_32 = 0x38,
0781 FMT_APC3 = 0x39,
0782 FMT_APC4 = 0x3a,
0783 FMT_APC5 = 0x3b,
0784 FMT_APC6 = 0x3c,
0785 FMT_APC7 = 0x3d,
0786 FMT_CTX1 = 0x3e,
0787 FMT_RESERVED_63 = 0x3f,
0788 } SurfaceFormat;
0789 typedef enum BUF_DATA_FORMAT {
0790 BUF_DATA_FORMAT_INVALID = 0x0,
0791 BUF_DATA_FORMAT_8 = 0x1,
0792 BUF_DATA_FORMAT_16 = 0x2,
0793 BUF_DATA_FORMAT_8_8 = 0x3,
0794 BUF_DATA_FORMAT_32 = 0x4,
0795 BUF_DATA_FORMAT_16_16 = 0x5,
0796 BUF_DATA_FORMAT_10_11_11 = 0x6,
0797 BUF_DATA_FORMAT_11_11_10 = 0x7,
0798 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
0799 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
0800 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
0801 BUF_DATA_FORMAT_32_32 = 0xb,
0802 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
0803 BUF_DATA_FORMAT_32_32_32 = 0xd,
0804 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
0805 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
0806 } BUF_DATA_FORMAT;
0807 typedef enum IMG_DATA_FORMAT {
0808 IMG_DATA_FORMAT_INVALID = 0x0,
0809 IMG_DATA_FORMAT_8 = 0x1,
0810 IMG_DATA_FORMAT_16 = 0x2,
0811 IMG_DATA_FORMAT_8_8 = 0x3,
0812 IMG_DATA_FORMAT_32 = 0x4,
0813 IMG_DATA_FORMAT_16_16 = 0x5,
0814 IMG_DATA_FORMAT_10_11_11 = 0x6,
0815 IMG_DATA_FORMAT_11_11_10 = 0x7,
0816 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
0817 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
0818 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
0819 IMG_DATA_FORMAT_32_32 = 0xb,
0820 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
0821 IMG_DATA_FORMAT_32_32_32 = 0xd,
0822 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
0823 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
0824 IMG_DATA_FORMAT_5_6_5 = 0x10,
0825 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
0826 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
0827 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
0828 IMG_DATA_FORMAT_8_24 = 0x14,
0829 IMG_DATA_FORMAT_24_8 = 0x15,
0830 IMG_DATA_FORMAT_X24_8_32 = 0x16,
0831 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
0832 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
0833 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
0834 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
0835 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
0836 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
0837 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
0838 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
0839 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
0840 IMG_DATA_FORMAT_GB_GR = 0x20,
0841 IMG_DATA_FORMAT_BG_RG = 0x21,
0842 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
0843 IMG_DATA_FORMAT_BC1 = 0x23,
0844 IMG_DATA_FORMAT_BC2 = 0x24,
0845 IMG_DATA_FORMAT_BC3 = 0x25,
0846 IMG_DATA_FORMAT_BC4 = 0x26,
0847 IMG_DATA_FORMAT_BC5 = 0x27,
0848 IMG_DATA_FORMAT_BC6 = 0x28,
0849 IMG_DATA_FORMAT_BC7 = 0x29,
0850 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
0851 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
0852 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
0853 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
0854 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
0855 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
0856 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
0857 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
0858 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
0859 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
0860 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
0861 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
0862 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
0863 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
0864 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
0865 IMG_DATA_FORMAT_4_4 = 0x39,
0866 IMG_DATA_FORMAT_6_5_5 = 0x3a,
0867 IMG_DATA_FORMAT_1 = 0x3b,
0868 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
0869 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
0870 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
0871 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
0872 } IMG_DATA_FORMAT;
0873 typedef enum BUF_NUM_FORMAT {
0874 BUF_NUM_FORMAT_UNORM = 0x0,
0875 BUF_NUM_FORMAT_SNORM = 0x1,
0876 BUF_NUM_FORMAT_USCALED = 0x2,
0877 BUF_NUM_FORMAT_SSCALED = 0x3,
0878 BUF_NUM_FORMAT_UINT = 0x4,
0879 BUF_NUM_FORMAT_SINT = 0x5,
0880 BUF_NUM_FORMAT_RESERVED_6 = 0x6,
0881 BUF_NUM_FORMAT_FLOAT = 0x7,
0882 } BUF_NUM_FORMAT;
0883 typedef enum IMG_NUM_FORMAT {
0884 IMG_NUM_FORMAT_UNORM = 0x0,
0885 IMG_NUM_FORMAT_SNORM = 0x1,
0886 IMG_NUM_FORMAT_USCALED = 0x2,
0887 IMG_NUM_FORMAT_SSCALED = 0x3,
0888 IMG_NUM_FORMAT_UINT = 0x4,
0889 IMG_NUM_FORMAT_SINT = 0x5,
0890 IMG_NUM_FORMAT_RESERVED_6 = 0x6,
0891 IMG_NUM_FORMAT_FLOAT = 0x7,
0892 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
0893 IMG_NUM_FORMAT_SRGB = 0x9,
0894 IMG_NUM_FORMAT_RESERVED_10 = 0xa,
0895 IMG_NUM_FORMAT_RESERVED_11 = 0xb,
0896 IMG_NUM_FORMAT_RESERVED_12 = 0xc,
0897 IMG_NUM_FORMAT_RESERVED_13 = 0xd,
0898 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
0899 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
0900 } IMG_NUM_FORMAT;
0901 typedef enum TileType {
0902 ARRAY_COLOR_TILE = 0x0,
0903 ARRAY_DEPTH_TILE = 0x1,
0904 } TileType;
0905 typedef enum NonDispTilingOrder {
0906 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
0907 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
0908 } NonDispTilingOrder;
0909 typedef enum MicroTileMode {
0910 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
0911 ADDR_SURF_THIN_MICRO_TILING = 0x1,
0912 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
0913 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
0914 ADDR_SURF_THICK_MICRO_TILING = 0x4,
0915 } MicroTileMode;
0916 typedef enum TileSplit {
0917 ADDR_SURF_TILE_SPLIT_64B = 0x0,
0918 ADDR_SURF_TILE_SPLIT_128B = 0x1,
0919 ADDR_SURF_TILE_SPLIT_256B = 0x2,
0920 ADDR_SURF_TILE_SPLIT_512B = 0x3,
0921 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
0922 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
0923 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
0924 } TileSplit;
0925 typedef enum SampleSplit {
0926 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
0927 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
0928 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
0929 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
0930 } SampleSplit;
0931 typedef enum PipeConfig {
0932 ADDR_SURF_P2 = 0x0,
0933 ADDR_SURF_P2_RESERVED0 = 0x1,
0934 ADDR_SURF_P2_RESERVED1 = 0x2,
0935 ADDR_SURF_P2_RESERVED2 = 0x3,
0936 ADDR_SURF_P4_8x16 = 0x4,
0937 ADDR_SURF_P4_16x16 = 0x5,
0938 ADDR_SURF_P4_16x32 = 0x6,
0939 ADDR_SURF_P4_32x32 = 0x7,
0940 ADDR_SURF_P8_16x16_8x16 = 0x8,
0941 ADDR_SURF_P8_16x32_8x16 = 0x9,
0942 ADDR_SURF_P8_32x32_8x16 = 0xa,
0943 ADDR_SURF_P8_16x32_16x16 = 0xb,
0944 ADDR_SURF_P8_32x32_16x16 = 0xc,
0945 ADDR_SURF_P8_32x32_16x32 = 0xd,
0946 ADDR_SURF_P8_32x64_32x32 = 0xe,
0947 ADDR_SURF_P8_RESERVED0 = 0xf,
0948 ADDR_SURF_P16_32x32_8x16 = 0x10,
0949 ADDR_SURF_P16_32x32_16x16 = 0x11,
0950 } PipeConfig;
0951 typedef enum NumBanks {
0952 ADDR_SURF_2_BANK = 0x0,
0953 ADDR_SURF_4_BANK = 0x1,
0954 ADDR_SURF_8_BANK = 0x2,
0955 ADDR_SURF_16_BANK = 0x3,
0956 } NumBanks;
0957 typedef enum BankWidth {
0958 ADDR_SURF_BANK_WIDTH_1 = 0x0,
0959 ADDR_SURF_BANK_WIDTH_2 = 0x1,
0960 ADDR_SURF_BANK_WIDTH_4 = 0x2,
0961 ADDR_SURF_BANK_WIDTH_8 = 0x3,
0962 } BankWidth;
0963 typedef enum BankHeight {
0964 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
0965 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
0966 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
0967 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
0968 } BankHeight;
0969 typedef enum BankWidthHeight {
0970 ADDR_SURF_BANK_WH_1 = 0x0,
0971 ADDR_SURF_BANK_WH_2 = 0x1,
0972 ADDR_SURF_BANK_WH_4 = 0x2,
0973 ADDR_SURF_BANK_WH_8 = 0x3,
0974 } BankWidthHeight;
0975 typedef enum MacroTileAspect {
0976 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
0977 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
0978 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
0979 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
0980 } MacroTileAspect;
0981 typedef enum GATCL1RequestType {
0982 GATCL1_TYPE_NORMAL = 0x0,
0983 GATCL1_TYPE_SHOOTDOWN = 0x1,
0984 GATCL1_TYPE_BYPASS = 0x2,
0985 } GATCL1RequestType;
0986 typedef enum TCC_CACHE_POLICIES {
0987 TCC_CACHE_POLICY_LRU = 0x0,
0988 TCC_CACHE_POLICY_STREAM = 0x1,
0989 } TCC_CACHE_POLICIES;
0990 typedef enum MTYPE {
0991 MTYPE_NC_NV = 0x0,
0992 MTYPE_NC = 0x1,
0993 MTYPE_CC = 0x2,
0994 MTYPE_UC = 0x3,
0995 } MTYPE;
0996 typedef enum PERFMON_COUNTER_MODE {
0997 PERFMON_COUNTER_MODE_ACCUM = 0x0,
0998 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
0999 PERFMON_COUNTER_MODE_MAX = 0x2,
1000 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1001 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1002 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1003 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1004 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1005 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1006 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1007 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1008 } PERFMON_COUNTER_MODE;
1009 typedef enum PERFMON_SPM_MODE {
1010 PERFMON_SPM_MODE_OFF = 0x0,
1011 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1012 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1013 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1014 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1015 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1016 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1017 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1018 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1019 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1020 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1021 } PERFMON_SPM_MODE;
1022 typedef enum SurfaceTiling {
1023 ARRAY_LINEAR = 0x0,
1024 ARRAY_TILED = 0x1,
1025 } SurfaceTiling;
1026 typedef enum SurfaceArray {
1027 ARRAY_1D = 0x0,
1028 ARRAY_2D = 0x1,
1029 ARRAY_3D = 0x2,
1030 ARRAY_3D_SLICE = 0x3,
1031 } SurfaceArray;
1032 typedef enum ColorArray {
1033 ARRAY_2D_ALT_COLOR = 0x0,
1034 ARRAY_2D_COLOR = 0x1,
1035 ARRAY_3D_SLICE_COLOR = 0x3,
1036 } ColorArray;
1037 typedef enum DepthArray {
1038 ARRAY_2D_ALT_DEPTH = 0x0,
1039 ARRAY_2D_DEPTH = 0x1,
1040 } DepthArray;
1041 typedef enum ENUM_NUM_SIMD_PER_CU {
1042 NUM_SIMD_PER_CU = 0x4,
1043 } ENUM_NUM_SIMD_PER_CU;
1044 typedef enum MEM_PWR_FORCE_CTRL {
1045 NO_FORCE_REQUEST = 0x0,
1046 FORCE_LIGHT_SLEEP_REQUEST = 0x1,
1047 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1048 FORCE_SHUT_DOWN_REQUEST = 0x3,
1049 } MEM_PWR_FORCE_CTRL;
1050 typedef enum MEM_PWR_FORCE_CTRL2 {
1051 NO_FORCE_REQ = 0x0,
1052 FORCE_LIGHT_SLEEP_REQ = 0x1,
1053 } MEM_PWR_FORCE_CTRL2;
1054 typedef enum MEM_PWR_DIS_CTRL {
1055 ENABLE_MEM_PWR_CTRL = 0x0,
1056 DISABLE_MEM_PWR_CTRL = 0x1,
1057 } MEM_PWR_DIS_CTRL;
1058 typedef enum MEM_PWR_SEL_CTRL {
1059 DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
1060 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
1061 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
1062 } MEM_PWR_SEL_CTRL;
1063 typedef enum MEM_PWR_SEL_CTRL2 {
1064 DYNAMIC_DEEP_SLEEP_EN = 0x0,
1065 DYNAMIC_LIGHT_SLEEP_EN = 0x1,
1066 } MEM_PWR_SEL_CTRL2;
1067
1068 #endif
