amd/acp/chip_offset_byte.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license. When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
0007  *
0008  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
0009  */
0010
0011 #ifndef _ACP_IP_OFFSET_HEADER
0012 #define _ACP_IP_OFFSET_HEADER
0013
0014 #define ACPAXI2AXI_ATU_CTRL                           0xC40
0015 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5                0xC20
0016 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5                0xC24
0017
0018 #define ACP_PGFSM_CONTROL           0x141C
0019 #define ACP_PGFSM_STATUS                        0x1420
0020 #define ACP_SOFT_RESET                          0x1000
0021 #define ACP_CONTROL                             0x1004
0022
0023 #define ACP_EXTERNAL_INTR_REG_ADDR(adata, offset, ctrl) \
0024     (adata->acp_base + adata->rsrc->irq_reg_offset + offset + (ctrl * 0x04))
0025
0026 #define ACP_EXTERNAL_INTR_ENB(adata) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x0, 0x0)
0027 #define ACP_EXTERNAL_INTR_CNTL(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x4, ctrl)
0028 #define ACP_EXTERNAL_INTR_STAT(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, \
0029     (0x4 + (adata->rsrc->no_of_ctrls * 0x04)), ctrl)
0030
0031 /* Registers from ACP_AUDIO_BUFFERS block */
0032
0033 #define ACP_I2S_RX_RINGBUFADDR                        0x2000
0034 #define ACP_I2S_RX_RINGBUFSIZE                        0x2004
0035 #define ACP_I2S_RX_LINKPOSITIONCNTR                   0x2008
0036 #define ACP_I2S_RX_FIFOADDR                           0x200C
0037 #define ACP_I2S_RX_FIFOSIZE                           0x2010
0038 #define ACP_I2S_RX_DMA_SIZE                           0x2014
0039 #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH            0x2018
0040 #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW             0x201C
0041 #define ACP_I2S_RX_INTR_WATERMARK_SIZE                0x2020
0042 #define ACP_I2S_TX_RINGBUFADDR                        0x2024
0043 #define ACP_I2S_TX_RINGBUFSIZE                        0x2028
0044 #define ACP_I2S_TX_LINKPOSITIONCNTR                   0x202C
0045 #define ACP_I2S_TX_FIFOADDR                           0x2030
0046 #define ACP_I2S_TX_FIFOSIZE                           0x2034
0047 #define ACP_I2S_TX_DMA_SIZE                           0x2038
0048 #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH            0x203C
0049 #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW             0x2040
0050 #define ACP_I2S_TX_INTR_WATERMARK_SIZE                0x2044
0051 #define ACP_BT_RX_RINGBUFADDR                         0x2048
0052 #define ACP_BT_RX_RINGBUFSIZE                         0x204C
0053 #define ACP_BT_RX_LINKPOSITIONCNTR                    0x2050
0054 #define ACP_BT_RX_FIFOADDR                            0x2054
0055 #define ACP_BT_RX_FIFOSIZE                            0x2058
0056 #define ACP_BT_RX_DMA_SIZE                            0x205C
0057 #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH             0x2060
0058 #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW              0x2064
0059 #define ACP_BT_RX_INTR_WATERMARK_SIZE                 0x2068
0060 #define ACP_BT_TX_RINGBUFADDR                         0x206C
0061 #define ACP_BT_TX_RINGBUFSIZE                         0x2070
0062 #define ACP_BT_TX_LINKPOSITIONCNTR                    0x2074
0063 #define ACP_BT_TX_FIFOADDR                            0x2078
0064 #define ACP_BT_TX_FIFOSIZE                            0x207C
0065 #define ACP_BT_TX_DMA_SIZE                            0x2080
0066 #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH             0x2084
0067 #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW              0x2088
0068 #define ACP_BT_TX_INTR_WATERMARK_SIZE                 0x208C
0069 #define ACP_HS_RX_RINGBUFADDR                 0x3A90
0070 #define ACP_HS_RX_RINGBUFSIZE                 0x3A94
0071 #define ACP_HS_RX_LINKPOSITIONCNTR            0x3A98
0072 #define ACP_HS_RX_FIFOADDR                0x3A9C
0073 #define ACP_HS_RX_FIFOSIZE                0x3AA0
0074 #define ACP_HS_RX_DMA_SIZE                0x3AA4
0075 #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH         0x3AA8
0076 #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW          0x3AAC
0077 #define ACP_HS_RX_INTR_WATERMARK_SIZE             0x3AB0
0078 #define ACP_HS_TX_RINGBUFADDR                 0x3AB4
0079 #define ACP_HS_TX_RINGBUFSIZE                 0x3AB8
0080 #define ACP_HS_TX_LINKPOSITIONCNTR            0x3ABC
0081 #define ACP_HS_TX_FIFOADDR                0x3AC0
0082 #define ACP_HS_TX_FIFOSIZE                0x3AC4
0083 #define ACP_HS_TX_DMA_SIZE                0x3AC8
0084 #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH         0x3ACC
0085 #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW          0x3AD0
0086 #define ACP_HS_TX_INTR_WATERMARK_SIZE             0x3AD4
0087
0088 #define ACP_I2STDM_IER                                0x2400
0089 #define ACP_I2STDM_IRER                               0x2404
0090 #define ACP_I2STDM_RXFRMT                             0x2408
0091 #define ACP_I2STDM_ITER                               0x240C
0092 #define ACP_I2STDM_TXFRMT                             0x2410
0093
0094 /* Registers from ACP_BT_TDM block */
0095
0096 #define ACP_BTTDM_IER                                 0x2800
0097 #define ACP_BTTDM_IRER                                0x2804
0098 #define ACP_BTTDM_RXFRMT                              0x2808
0099 #define ACP_BTTDM_ITER                                0x280C
0100 #define ACP_BTTDM_TXFRMT                              0x2810
0101
0102 /* Registers from ACP_HS_TDM block */
0103 #define ACP_HSTDM_IER                                 0x2814
0104 #define ACP_HSTDM_IRER                                0x2818
0105 #define ACP_HSTDM_RXFRMT                              0x281C
0106 #define ACP_HSTDM_ITER                                0x2820
0107 #define ACP_HSTDM_TXFRMT                              0x2824
0108
0109 /* Registers from ACP_WOV_PDM block */
0110
0111 #define ACP_WOV_PDM_ENABLE                            0x2C04
0112 #define ACP_WOV_PDM_DMA_ENABLE                        0x2C08
0113 #define ACP_WOV_RX_RINGBUFADDR                        0x2C0C
0114 #define ACP_WOV_RX_RINGBUFSIZE                        0x2C10
0115 #define ACP_WOV_RX_LINKPOSITIONCNTR                   0x2C14
0116 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH            0x2C18
0117 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW             0x2C1C
0118 #define ACP_WOV_RX_INTR_WATERMARK_SIZE                0x2C20
0119 #define ACP_WOV_PDM_FIFO_FLUSH                        0x2C24
0120 #define ACP_WOV_PDM_NO_OF_CHANNELS                    0x2C28
0121 #define ACP_WOV_PDM_DECIMATION_FACTOR                 0x2C2C
0122 #define ACP_WOV_PDM_VAD_CTRL                          0x2C30
0123 #define ACP_WOV_BUFFER_STATUS                         0x2C58
0124 #define ACP_WOV_MISC_CTRL                             0x2C5C
0125 #define ACP_WOV_CLK_CTRL                              0x2C60
0126 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN             0x2C64
0127 #define ACP_WOV_ERROR_STATUS_REGISTER                 0x2C68
0128
0129 #define ACP_I2STDM0_MSTRCLKGEN                0x2414
0130 #define ACP_I2STDM1_MSTRCLKGEN                0x2418
0131 #define ACP_I2STDM2_MSTRCLKGEN                0x241C
0132 #endif