amd/acp/acp-pdm.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // This file is provided under a dual BSD/GPLv2 license. When using or
0004 // redistributing this file, you may do so under either license.
0005 //
0006 // Copyright(c) 2022 Advanced Micro Devices, Inc.
0007 //
0008 // Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
0009 //      Vijendar Mukunda <Vijendar.Mukunda@amd.com>
0010 //
0011
0012 /*
0013  * Generic Hardware interface for ACP Audio PDM controller
0014  */
0015
0016 #include <linux/err.h>
0017 #include <linux/io.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/soc.h>
0022 #include <sound/soc-dai.h>
0023
0024 #include "amd.h"
0025
0026 #define DRV_NAME "acp-pdm"
0027
0028 #define PDM_DMA_STAT        0x10
0029 #define PDM_DMA_INTR_MASK   0x10000
0030 #define PDM_DEC_64      0x2
0031 #define PDM_CLK_FREQ_MASK   0x07
0032 #define PDM_MISC_CTRL_MASK  0x10
0033 #define PDM_ENABLE      0x01
0034 #define PDM_DISABLE     0x00
0035 #define DMA_EN_MASK     0x02
0036 #define DELAY_US        5
0037 #define PDM_TIMEOUT     1000
0038 #define ACP_REGION2_OFFSET  0x02000000
0039
0040 static int acp_dmic_prepare(struct snd_pcm_substream *substream,
0041                 struct snd_soc_dai *dai)
0042 {
0043     struct acp_stream *stream = substream->runtime->private_data;
0044     struct device *dev = dai->component->dev;
0045     struct acp_dev_data *adata = dev_get_drvdata(dev);
0046     u32 physical_addr, size_dmic, period_bytes;
0047     unsigned int dmic_ctrl;
0048
0049     /* Enable default DMIC clk */
0050     writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);
0051     dmic_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);
0052     dmic_ctrl |= PDM_MISC_CTRL_MASK;
0053     writel(dmic_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);
0054
0055     period_bytes = frames_to_bytes(substream->runtime,
0056             substream->runtime->period_size);
0057     size_dmic = frames_to_bytes(substream->runtime,
0058             substream->runtime->buffer_size);
0059
0060     physical_addr = stream->reg_offset + MEM_WINDOW_START;
0061
0062     /* Init DMIC Ring buffer */
0063     writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);
0064     writel(size_dmic, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);
0065     writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
0066     writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);
0067
0068     return 0;
0069 }
0070
0071 static int acp_dmic_dai_trigger(struct snd_pcm_substream *substream,
0072                 int cmd, struct snd_soc_dai *dai)
0073 {
0074     struct device *dev = dai->component->dev;
0075     struct acp_dev_data *adata = dev_get_drvdata(dev);
0076     unsigned int dma_enable;
0077     int ret = 0;
0078
0079     switch (cmd) {
0080     case SNDRV_PCM_TRIGGER_START:
0081     case SNDRV_PCM_TRIGGER_RESUME:
0082     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0083         dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
0084         if (!(dma_enable & DMA_EN_MASK)) {
0085             writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
0086             writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
0087         }
0088
0089         ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
0090                         dma_enable, (dma_enable & DMA_EN_MASK),
0091                         DELAY_US, PDM_TIMEOUT);
0092         break;
0093     case SNDRV_PCM_TRIGGER_STOP:
0094     case SNDRV_PCM_TRIGGER_SUSPEND:
0095     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0096         dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
0097         if ((dma_enable & DMA_EN_MASK)) {
0098             writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
0099             writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
0100
0101         }
0102
0103         ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
0104                         dma_enable, !(dma_enable & DMA_EN_MASK),
0105                         DELAY_US, PDM_TIMEOUT);
0106         break;
0107     default:
0108         ret = -EINVAL;
0109         break;
0110     }
0111
0112     return ret;
0113 }
0114
0115 static int acp_dmic_hwparams(struct snd_pcm_substream *substream,
0116                  struct snd_pcm_hw_params *hwparams, struct snd_soc_dai *dai)
0117 {
0118     struct device *dev = dai->component->dev;
0119     struct acp_dev_data *adata = dev_get_drvdata(dev);
0120     unsigned int channels, ch_mask;
0121
0122     channels = params_channels(hwparams);
0123     switch (channels) {
0124     case 2:
0125         ch_mask = 0;
0126         break;
0127     case 4:
0128         ch_mask = 1;
0129         break;
0130     case 6:
0131         ch_mask = 2;
0132         break;
0133     default:
0134         dev_err(dev, "Invalid channels %d\n", channels);
0135         return -EINVAL;
0136     }
0137
0138     if (params_format(hwparams) != SNDRV_PCM_FORMAT_S32_LE) {
0139         dev_err(dai->dev, "Invalid format:%d\n", params_format(hwparams));
0140         return -EINVAL;
0141     }
0142
0143     writel(ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
0144     writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);
0145
0146     return 0;
0147 }
0148
0149 static int acp_dmic_dai_startup(struct snd_pcm_substream *substream,
0150                 struct snd_soc_dai *dai)
0151 {
0152     struct acp_stream *stream = substream->runtime->private_data;
0153     struct device *dev = dai->component->dev;
0154     struct acp_dev_data *adata = dev_get_drvdata(dev);
0155     u32 ext_int_ctrl;
0156
0157     stream->dai_id = DMIC_INSTANCE;
0158     stream->irq_bit = BIT(PDM_DMA_STAT);
0159     stream->pte_offset = ACP_SRAM_PDM_PTE_OFFSET;
0160     stream->reg_offset = ACP_REGION2_OFFSET;
0161
0162     /* Enable DMIC Interrupts */
0163     ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
0164     ext_int_ctrl |= PDM_DMA_INTR_MASK;
0165     writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
0166
0167     return 0;
0168 }
0169
0170 static void acp_dmic_dai_shutdown(struct snd_pcm_substream *substream,
0171                   struct snd_soc_dai *dai)
0172 {
0173     struct device *dev = dai->component->dev;
0174     struct acp_dev_data *adata = dev_get_drvdata(dev);
0175     u32 ext_int_ctrl;
0176
0177     /* Disable DMIC interrupts */
0178     ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
0179     ext_int_ctrl |= ~PDM_DMA_INTR_MASK;
0180     writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
0181 }
0182
0183 const struct snd_soc_dai_ops acp_dmic_dai_ops = {
0184     .prepare    = acp_dmic_prepare,
0185     .hw_params  = acp_dmic_hwparams,
0186     .trigger    = acp_dmic_dai_trigger,
0187     .startup    = acp_dmic_dai_startup,
0188     .shutdown   = acp_dmic_dai_shutdown,
0189 };
0190 EXPORT_SYMBOL_NS_GPL(acp_dmic_dai_ops, SND_SOC_ACP_COMMON);
0191
0192 MODULE_LICENSE("Dual BSD/GPL");
0193 MODULE_ALIAS(DRV_NAME);