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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AMD ALSA SoC PCM Driver for ACP 2.x
0004  *
0005  * Copyright 2014-2015 Advanced Micro Devices, Inc.
0006  */
0007 
0008 #include <linux/module.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/sizes.h>
0013 #include <linux/pm_runtime.h>
0014 
0015 #include <sound/soc.h>
0016 #include <drm/amd_asic_type.h>
0017 #include "acp.h"
0018 
0019 #define DRV_NAME "acp_audio_dma"
0020 
0021 #define PLAYBACK_MIN_NUM_PERIODS    2
0022 #define PLAYBACK_MAX_NUM_PERIODS    2
0023 #define PLAYBACK_MAX_PERIOD_SIZE    16384
0024 #define PLAYBACK_MIN_PERIOD_SIZE    1024
0025 #define CAPTURE_MIN_NUM_PERIODS     2
0026 #define CAPTURE_MAX_NUM_PERIODS     2
0027 #define CAPTURE_MAX_PERIOD_SIZE     16384
0028 #define CAPTURE_MIN_PERIOD_SIZE     1024
0029 
0030 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
0031 #define MIN_BUFFER MAX_BUFFER
0032 
0033 #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
0034 #define ST_CAPTURE_MAX_PERIOD_SIZE  ST_PLAYBACK_MAX_PERIOD_SIZE
0035 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
0036 #define ST_MIN_BUFFER ST_MAX_BUFFER
0037 
0038 #define DRV_NAME "acp_audio_dma"
0039 bool acp_bt_uart_enable = true;
0040 EXPORT_SYMBOL(acp_bt_uart_enable);
0041 
0042 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
0043     .info = SNDRV_PCM_INFO_INTERLEAVED |
0044         SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
0045         SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
0046         SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
0047     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0048         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0049     .channels_min = 1,
0050     .channels_max = 8,
0051     .rates = SNDRV_PCM_RATE_8000_96000,
0052     .rate_min = 8000,
0053     .rate_max = 96000,
0054     .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
0055     .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
0056     .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
0057     .periods_min = PLAYBACK_MIN_NUM_PERIODS,
0058     .periods_max = PLAYBACK_MAX_NUM_PERIODS,
0059 };
0060 
0061 static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
0062     .info = SNDRV_PCM_INFO_INTERLEAVED |
0063         SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
0064         SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
0065         SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
0066     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0067         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0068     .channels_min = 1,
0069     .channels_max = 2,
0070     .rates = SNDRV_PCM_RATE_8000_48000,
0071     .rate_min = 8000,
0072     .rate_max = 48000,
0073     .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
0074     .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
0075     .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
0076     .periods_min = CAPTURE_MIN_NUM_PERIODS,
0077     .periods_max = CAPTURE_MAX_NUM_PERIODS,
0078 };
0079 
0080 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
0081     .info = SNDRV_PCM_INFO_INTERLEAVED |
0082         SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
0083         SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
0084         SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
0085     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0086         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0087     .channels_min = 1,
0088     .channels_max = 8,
0089     .rates = SNDRV_PCM_RATE_8000_96000,
0090     .rate_min = 8000,
0091     .rate_max = 96000,
0092     .buffer_bytes_max = ST_MAX_BUFFER,
0093     .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
0094     .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
0095     .periods_min = PLAYBACK_MIN_NUM_PERIODS,
0096     .periods_max = PLAYBACK_MAX_NUM_PERIODS,
0097 };
0098 
0099 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
0100     .info = SNDRV_PCM_INFO_INTERLEAVED |
0101         SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
0102         SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
0103         SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
0104     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0105         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0106     .channels_min = 1,
0107     .channels_max = 2,
0108     .rates = SNDRV_PCM_RATE_8000_48000,
0109     .rate_min = 8000,
0110     .rate_max = 48000,
0111     .buffer_bytes_max = ST_MAX_BUFFER,
0112     .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
0113     .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
0114     .periods_min = CAPTURE_MIN_NUM_PERIODS,
0115     .periods_max = CAPTURE_MAX_NUM_PERIODS,
0116 };
0117 
0118 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
0119 {
0120     return readl(acp_mmio + (reg * 4));
0121 }
0122 
0123 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
0124 {
0125     writel(val, acp_mmio + (reg * 4));
0126 }
0127 
0128 /*
0129  * Configure a given dma channel parameters - enable/disable,
0130  * number of descriptors, priority
0131  */
0132 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
0133                    u16 dscr_strt_idx, u16 num_dscrs,
0134                    enum acp_dma_priority_level priority_level)
0135 {
0136     u32 dma_ctrl;
0137 
0138     /* disable the channel run field */
0139     dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0140     dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
0141     acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0142 
0143     /* program a DMA channel with first descriptor to be processed. */
0144     acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
0145             & dscr_strt_idx),
0146             acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
0147 
0148     /*
0149      * program a DMA channel with the number of descriptors to be
0150      * processed in the transfer
0151      */
0152     acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
0153               acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
0154 
0155     /* set DMA channel priority */
0156     acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
0157 }
0158 
0159 /* Initialize a dma descriptor in SRAM based on descriptor information passed */
0160 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
0161                       u16 descr_idx,
0162                       acp_dma_dscr_transfer_t *descr_info)
0163 {
0164     u32 sram_offset;
0165 
0166     sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
0167 
0168     /* program the source base address. */
0169     acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
0170     acp_reg_write(descr_info->src,  acp_mmio, mmACP_SRBM_Targ_Idx_Data);
0171     /* program the destination base address. */
0172     acp_reg_write(sram_offset + 4,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
0173     acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
0174 
0175     /* program the number of bytes to be transferred for this descriptor. */
0176     acp_reg_write(sram_offset + 8,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
0177     acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
0178 }
0179 
0180 static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)
0181 {
0182     u32 dma_ctrl;
0183     int ret;
0184 
0185     /* clear the reset bit */
0186     dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0187     dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
0188     acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0189     /* check the reset bit before programming configuration registers */
0190     ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),
0191                  dma_ctrl,
0192                  !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK),
0193                  100, ACP_DMA_RESET_TIME);
0194     if (ret < 0)
0195         pr_err("Failed to clear reset of channel : %d\n", ch_num);
0196 }
0197 
0198 /*
0199  * Initialize the DMA descriptor information for transfer between
0200  * system memory <-> ACP SRAM
0201  */
0202 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
0203                        u32 size, int direction,
0204                        u32 pte_offset, u16 ch,
0205                        u32 sram_bank, u16 dma_dscr_idx,
0206                        u32 asic_type)
0207 {
0208     u16 i;
0209     acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
0210 
0211     for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
0212         dmadscr[i].xfer_val = 0;
0213         if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0214             dma_dscr_idx = dma_dscr_idx + i;
0215             dmadscr[i].dest = sram_bank + (i * (size / 2));
0216             dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
0217                 + (pte_offset * SZ_4K) + (i * (size / 2));
0218             switch (asic_type) {
0219             case CHIP_STONEY:
0220                 dmadscr[i].xfer_val |=
0221                 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM  << 16) |
0222                 (size / 2);
0223                 break;
0224             default:
0225                 dmadscr[i].xfer_val |=
0226                 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM  << 16) |
0227                 (size / 2);
0228             }
0229         } else {
0230             dma_dscr_idx = dma_dscr_idx + i;
0231             dmadscr[i].src = sram_bank + (i * (size / 2));
0232             dmadscr[i].dest =
0233             ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
0234             (pte_offset * SZ_4K) + (i * (size / 2));
0235             switch (asic_type) {
0236             case CHIP_STONEY:
0237                 dmadscr[i].xfer_val |=
0238                 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
0239                 (size / 2);
0240                 break;
0241             default:
0242                 dmadscr[i].xfer_val |=
0243                 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
0244                 (size / 2);
0245             }
0246         }
0247         config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
0248                           &dmadscr[i]);
0249     }
0250     pre_config_reset(acp_mmio, ch);
0251     config_acp_dma_channel(acp_mmio, ch,
0252                    dma_dscr_idx - 1,
0253                    NUM_DSCRS_PER_CHANNEL,
0254                    ACP_DMA_PRIORITY_LEVEL_NORMAL);
0255 }
0256 
0257 /*
0258  * Initialize the DMA descriptor information for transfer between
0259  * ACP SRAM <-> I2S
0260  */
0261 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
0262                        int direction, u32 sram_bank,
0263                        u16 destination, u16 ch,
0264                        u16 dma_dscr_idx, u32 asic_type)
0265 {
0266     u16 i;
0267     acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
0268 
0269     for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
0270         dmadscr[i].xfer_val = 0;
0271         if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0272             dma_dscr_idx = dma_dscr_idx + i;
0273             dmadscr[i].src = sram_bank  + (i * (size / 2));
0274             /* dmadscr[i].dest is unused by hardware. */
0275             dmadscr[i].dest = 0;
0276             dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
0277                         (size / 2);
0278         } else {
0279             dma_dscr_idx = dma_dscr_idx + i;
0280             /* dmadscr[i].src is unused by hardware. */
0281             dmadscr[i].src = 0;
0282             dmadscr[i].dest =
0283                  sram_bank + (i * (size / 2));
0284             dmadscr[i].xfer_val |= BIT(22) |
0285                 (destination << 16) | (size / 2);
0286         }
0287         config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
0288                           &dmadscr[i]);
0289     }
0290     pre_config_reset(acp_mmio, ch);
0291     /* Configure the DMA channel with the above descriptor */
0292     config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
0293                    NUM_DSCRS_PER_CHANNEL,
0294                    ACP_DMA_PRIORITY_LEVEL_NORMAL);
0295 }
0296 
0297 /* Create page table entries in ACP SRAM for the allocated memory */
0298 static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,
0299                u16 num_of_pages, u32 pte_offset)
0300 {
0301     u16 page_idx;
0302     u32 low;
0303     u32 high;
0304     u32 offset;
0305 
0306     offset  = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
0307     for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
0308         /* Load the low address of page int ACP SRAM through SRBM */
0309         acp_reg_write((offset + (page_idx * 8)),
0310                   acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
0311 
0312         low = lower_32_bits(addr);
0313         high = upper_32_bits(addr);
0314 
0315         acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
0316 
0317         /* Load the High address of page int ACP SRAM through SRBM */
0318         acp_reg_write((offset + (page_idx * 8) + 4),
0319                   acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
0320 
0321         /* page enable in ACP */
0322         high |= BIT(31);
0323         acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
0324 
0325         /* Move to next physically contiguous page */
0326         addr += PAGE_SIZE;
0327     }
0328 }
0329 
0330 static void config_acp_dma(void __iomem *acp_mmio,
0331                struct audio_substream_data *rtd,
0332                u32 asic_type)
0333 {
0334     u16 ch_acp_sysmem, ch_acp_i2s;
0335 
0336     acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages,
0337                rtd->pte_offset);
0338 
0339     if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
0340         ch_acp_sysmem = rtd->ch1;
0341         ch_acp_i2s = rtd->ch2;
0342     } else {
0343         ch_acp_i2s = rtd->ch1;
0344         ch_acp_sysmem = rtd->ch2;
0345     }
0346     /* Configure System memory <-> ACP SRAM DMA descriptors */
0347     set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
0348                        rtd->direction, rtd->pte_offset,
0349                        ch_acp_sysmem, rtd->sram_bank,
0350                        rtd->dma_dscr_idx_1, asic_type);
0351     /* Configure ACP SRAM <-> I2S DMA descriptors */
0352     set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
0353                        rtd->direction, rtd->sram_bank,
0354                        rtd->destination, ch_acp_i2s,
0355                        rtd->dma_dscr_idx_2, asic_type);
0356 }
0357 
0358 static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
0359                        u16 cap_channel)
0360 {
0361     u32 val, ch_reg, imr_reg, res_reg;
0362 
0363     switch (cap_channel) {
0364     case CAP_CHANNEL1:
0365         ch_reg = mmACP_I2SMICSP_RER1;
0366         res_reg = mmACP_I2SMICSP_RCR1;
0367         imr_reg = mmACP_I2SMICSP_IMR1;
0368         break;
0369     case CAP_CHANNEL0:
0370     default:
0371         ch_reg = mmACP_I2SMICSP_RER0;
0372         res_reg = mmACP_I2SMICSP_RCR0;
0373         imr_reg = mmACP_I2SMICSP_IMR0;
0374         break;
0375     }
0376     val = acp_reg_read(acp_mmio,
0377                mmACP_I2S_16BIT_RESOLUTION_EN);
0378     if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {
0379         acp_reg_write(0x0, acp_mmio, ch_reg);
0380         /* Set 16bit resolution on capture */
0381         acp_reg_write(0x2, acp_mmio, res_reg);
0382     }
0383     val = acp_reg_read(acp_mmio, imr_reg);
0384     val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
0385     val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
0386     acp_reg_write(val, acp_mmio, imr_reg);
0387     acp_reg_write(0x1, acp_mmio, ch_reg);
0388 }
0389 
0390 static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
0391                     u16 cap_channel)
0392 {
0393     u32 val, ch_reg, imr_reg;
0394 
0395     switch (cap_channel) {
0396     case CAP_CHANNEL1:
0397         imr_reg = mmACP_I2SMICSP_IMR1;
0398         ch_reg = mmACP_I2SMICSP_RER1;
0399         break;
0400     case CAP_CHANNEL0:
0401     default:
0402         imr_reg = mmACP_I2SMICSP_IMR0;
0403         ch_reg = mmACP_I2SMICSP_RER0;
0404         break;
0405     }
0406     val = acp_reg_read(acp_mmio, imr_reg);
0407     val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
0408     val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
0409     acp_reg_write(val, acp_mmio, imr_reg);
0410     acp_reg_write(0x0, acp_mmio, ch_reg);
0411 }
0412 
0413 /* Start a given DMA channel transfer */
0414 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)
0415 {
0416     u32 dma_ctrl;
0417 
0418     /* read the dma control register and disable the channel run field */
0419     dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0420 
0421     /* Invalidating the DAGB cache */
0422     acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
0423 
0424     /*
0425      * configure the DMA channel and start the DMA transfer
0426      * set dmachrun bit to start the transfer and enable the
0427      * interrupt on completion of the dma transfer
0428      */
0429     dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
0430 
0431     switch (ch_num) {
0432     case ACP_TO_I2S_DMA_CH_NUM:
0433     case I2S_TO_ACP_DMA_CH_NUM:
0434     case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
0435     case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
0436     case ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM:
0437         dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
0438         break;
0439     default:
0440         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
0441         break;
0442     }
0443 
0444     /* enable for ACP to SRAM DMA channel */
0445     if (is_circular == true)
0446         dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
0447     else
0448         dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
0449 
0450     acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0451 }
0452 
0453 /* Stop a given DMA channel transfer */
0454 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
0455 {
0456     u32 dma_ctrl;
0457     u32 dma_ch_sts;
0458     u32 count = ACP_DMA_RESET_TIME;
0459 
0460     dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0461 
0462     /*
0463      * clear the dma control register fields before writing zero
0464      * in reset bit
0465      */
0466     dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
0467     dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
0468 
0469     acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0470     dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
0471 
0472     if (dma_ch_sts & BIT(ch_num)) {
0473         /*
0474          * set the reset bit for this channel to stop the dma
0475          *  transfer
0476          */
0477         dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
0478         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
0479     }
0480 
0481     /* check the channel status bit for some time and return the status */
0482     while (true) {
0483         dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
0484         if (!(dma_ch_sts & BIT(ch_num))) {
0485             /*
0486              * clear the reset flag after successfully stopping
0487              * the dma transfer and break from the loop
0488              */
0489             dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
0490 
0491             acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
0492                       + ch_num);
0493             break;
0494         }
0495         if (--count == 0) {
0496             pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
0497             return -ETIMEDOUT;
0498         }
0499         udelay(100);
0500     }
0501     return 0;
0502 }
0503 
0504 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
0505                     bool power_on)
0506 {
0507     u32 val, req_reg, sts_reg, sts_reg_mask;
0508     u32 loops = 1000;
0509 
0510     if (bank < 32) {
0511         req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
0512         sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
0513         sts_reg_mask = 0xFFFFFFFF;
0514 
0515     } else {
0516         bank -= 32;
0517         req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
0518         sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
0519         sts_reg_mask = 0x0000FFFF;
0520     }
0521 
0522     val = acp_reg_read(acp_mmio, req_reg);
0523     if (val & (1 << bank)) {
0524         /* bank is in off state */
0525         if (power_on == true)
0526             /* request to on */
0527             val &= ~(1 << bank);
0528         else
0529             /* request to off */
0530             return;
0531     } else {
0532         /* bank is in on state */
0533         if (power_on == false)
0534             /* request to off */
0535             val |= 1 << bank;
0536         else
0537             /* request to on */
0538             return;
0539     }
0540     acp_reg_write(val, acp_mmio, req_reg);
0541 
0542     while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
0543         if (!loops--) {
0544             pr_err("ACP SRAM bank %d state change failed\n", bank);
0545             break;
0546         }
0547         cpu_relax();
0548     }
0549 }
0550 
0551 /* Initialize and bring ACP hardware to default state. */
0552 static int acp_init(void __iomem *acp_mmio, u32 asic_type)
0553 {
0554     u16 bank;
0555     u32 val, count, sram_pte_offset;
0556 
0557     /* Assert Soft reset of ACP */
0558     val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
0559 
0560     val |= ACP_SOFT_RESET__SoftResetAud_MASK;
0561     acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
0562 
0563     count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
0564     while (true) {
0565         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
0566         if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
0567             (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
0568             break;
0569         if (--count == 0) {
0570             pr_err("Failed to reset ACP\n");
0571             return -ETIMEDOUT;
0572         }
0573         udelay(100);
0574     }
0575 
0576     /* Enable clock to ACP and wait until the clock is enabled */
0577     val = acp_reg_read(acp_mmio, mmACP_CONTROL);
0578     val = val | ACP_CONTROL__ClkEn_MASK;
0579     acp_reg_write(val, acp_mmio, mmACP_CONTROL);
0580 
0581     count = ACP_CLOCK_EN_TIME_OUT_VALUE;
0582 
0583     while (true) {
0584         val = acp_reg_read(acp_mmio, mmACP_STATUS);
0585         if (val & (u32)0x1)
0586             break;
0587         if (--count == 0) {
0588             pr_err("Failed to reset ACP\n");
0589             return -ETIMEDOUT;
0590         }
0591         udelay(100);
0592     }
0593 
0594     /* Deassert the SOFT RESET flags */
0595     val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
0596     val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
0597     acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
0598 
0599     /* For BT instance change pins from UART to BT */
0600     if (!acp_bt_uart_enable) {
0601         val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
0602         val |= ACP_BT_UART_PAD_SELECT_MASK;
0603         acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
0604     }
0605 
0606     /* initialize Onion control DAGB register */
0607     acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
0608               mmACP_AXI2DAGB_ONION_CNTL);
0609 
0610     /* initialize Garlic control DAGB registers */
0611     acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
0612               mmACP_AXI2DAGB_GARLIC_CNTL);
0613 
0614     sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
0615             ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
0616             ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
0617             ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
0618     acp_reg_write(sram_pte_offset,  acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
0619     acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
0620               mmACP_DAGB_PAGE_SIZE_GRP_1);
0621 
0622     acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
0623               mmACP_DMA_DESC_BASE_ADDR);
0624 
0625     /* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */
0626     acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
0627     acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
0628               acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
0629 
0630        /*
0631     * When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
0632     * Now, turn off all of them. This can't be done in 'poweron' of
0633     * ACP pm domain, as this requires ACP to be initialized.
0634     * For Stoney, Memory gating is disabled,i.e SRAM Banks
0635     * won't be turned off. The default state for SRAM banks is ON.
0636     * Setting SRAM bank state code skipped for STONEY platform.
0637     */
0638     if (asic_type != CHIP_STONEY) {
0639         for (bank = 1; bank < 48; bank++)
0640             acp_set_sram_bank_state(acp_mmio, bank, false);
0641     }
0642     return 0;
0643 }
0644 
0645 /* Deinitialize ACP */
0646 static int acp_deinit(void __iomem *acp_mmio)
0647 {
0648     u32 val;
0649     u32 count;
0650 
0651     /* Assert Soft reset of ACP */
0652     val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
0653 
0654     val |= ACP_SOFT_RESET__SoftResetAud_MASK;
0655     acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
0656 
0657     count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
0658     while (true) {
0659         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
0660         if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
0661             (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
0662             break;
0663         if (--count == 0) {
0664             pr_err("Failed to reset ACP\n");
0665             return -ETIMEDOUT;
0666         }
0667         udelay(100);
0668     }
0669     /* Disable ACP clock */
0670     val = acp_reg_read(acp_mmio, mmACP_CONTROL);
0671     val &= ~ACP_CONTROL__ClkEn_MASK;
0672     acp_reg_write(val, acp_mmio, mmACP_CONTROL);
0673 
0674     count = ACP_CLOCK_EN_TIME_OUT_VALUE;
0675 
0676     while (true) {
0677         val = acp_reg_read(acp_mmio, mmACP_STATUS);
0678         if (!(val & (u32)0x1))
0679             break;
0680         if (--count == 0) {
0681             pr_err("Failed to reset ACP\n");
0682             return -ETIMEDOUT;
0683         }
0684         udelay(100);
0685     }
0686     return 0;
0687 }
0688 
0689 /* ACP DMA irq handler routine for playback, capture usecases */
0690 static irqreturn_t dma_irq_handler(int irq, void *arg)
0691 {
0692     u16 dscr_idx;
0693     u32 intr_flag, ext_intr_status;
0694     struct audio_drv_data *irq_data;
0695     void __iomem *acp_mmio;
0696     struct device *dev = arg;
0697     bool valid_irq = false;
0698 
0699     irq_data = dev_get_drvdata(dev);
0700     acp_mmio = irq_data->acp_mmio;
0701 
0702     ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
0703     intr_flag = (((ext_intr_status &
0704               ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
0705              ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
0706 
0707     if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
0708         valid_irq = true;
0709         snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
0710         acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
0711                   acp_mmio, mmACP_EXTERNAL_INTR_STAT);
0712     }
0713 
0714     if ((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) != 0) {
0715         valid_irq = true;
0716         snd_pcm_period_elapsed(irq_data->play_i2s_micsp_stream);
0717         acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) << 16,
0718                   acp_mmio, mmACP_EXTERNAL_INTR_STAT);
0719     }
0720 
0721     if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
0722         valid_irq = true;
0723         snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
0724         acp_reg_write((intr_flag &
0725                   BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
0726                   acp_mmio, mmACP_EXTERNAL_INTR_STAT);
0727     }
0728 
0729     if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
0730         valid_irq = true;
0731         if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==
0732                 CAPTURE_START_DMA_DESCR_CH15)
0733             dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
0734         else
0735             dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
0736         config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
0737                        1, 0);
0738         acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
0739 
0740         snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
0741         acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
0742                   acp_mmio, mmACP_EXTERNAL_INTR_STAT);
0743     }
0744 
0745     if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
0746         valid_irq = true;
0747         if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==
0748             CAPTURE_START_DMA_DESCR_CH11)
0749             dscr_idx = CAPTURE_END_DMA_DESCR_CH10;
0750         else
0751             dscr_idx = CAPTURE_START_DMA_DESCR_CH10;
0752         config_acp_dma_channel(acp_mmio,
0753                        ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
0754                        dscr_idx, 1, 0);
0755         acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
0756                   false);
0757 
0758         snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
0759         acp_reg_write((intr_flag &
0760                   BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
0761                   acp_mmio, mmACP_EXTERNAL_INTR_STAT);
0762     }
0763 
0764     if (valid_irq)
0765         return IRQ_HANDLED;
0766     else
0767         return IRQ_NONE;
0768 }
0769 
0770 static int acp_dma_open(struct snd_soc_component *component,
0771             struct snd_pcm_substream *substream)
0772 {
0773     u16 bank;
0774     int ret = 0;
0775     struct snd_pcm_runtime *runtime = substream->runtime;
0776     struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
0777     struct audio_substream_data *adata =
0778         kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
0779     if (!adata)
0780         return -ENOMEM;
0781 
0782     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0783         switch (intr_data->asic_type) {
0784         case CHIP_STONEY:
0785             runtime->hw = acp_st_pcm_hardware_playback;
0786             break;
0787         default:
0788             runtime->hw = acp_pcm_hardware_playback;
0789         }
0790     } else {
0791         switch (intr_data->asic_type) {
0792         case CHIP_STONEY:
0793             runtime->hw = acp_st_pcm_hardware_capture;
0794             break;
0795         default:
0796             runtime->hw = acp_pcm_hardware_capture;
0797         }
0798     }
0799 
0800     ret = snd_pcm_hw_constraint_integer(runtime,
0801                         SNDRV_PCM_HW_PARAM_PERIODS);
0802     if (ret < 0) {
0803         dev_err(component->dev, "set integer constraint failed\n");
0804         kfree(adata);
0805         return ret;
0806     }
0807 
0808     adata->acp_mmio = intr_data->acp_mmio;
0809     runtime->private_data = adata;
0810 
0811     /*
0812      * Enable ACP irq, when neither playback or capture streams are
0813      * active by the time when a new stream is being opened.
0814      * This enablement is not required for another stream, if current
0815      * stream is not closed
0816      */
0817     if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
0818         !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream &&
0819         !intr_data->play_i2s_micsp_stream)
0820         acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
0821 
0822     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0823         /*
0824          * For Stoney, Memory gating is disabled,i.e SRAM Banks
0825          * won't be turned off. The default state for SRAM banks is ON.
0826          * Setting SRAM bank state code skipped for STONEY platform.
0827          */
0828         if (intr_data->asic_type != CHIP_STONEY) {
0829             for (bank = 1; bank <= 4; bank++)
0830                 acp_set_sram_bank_state(intr_data->acp_mmio,
0831                             bank, true);
0832         }
0833     } else {
0834         if (intr_data->asic_type != CHIP_STONEY) {
0835             for (bank = 5; bank <= 8; bank++)
0836                 acp_set_sram_bank_state(intr_data->acp_mmio,
0837                             bank, true);
0838         }
0839     }
0840 
0841     return 0;
0842 }
0843 
0844 static int acp_dma_hw_params(struct snd_soc_component *component,
0845                  struct snd_pcm_substream *substream,
0846                  struct snd_pcm_hw_params *params)
0847 {
0848     uint64_t size;
0849     u32 val = 0;
0850     struct snd_pcm_runtime *runtime;
0851     struct audio_substream_data *rtd;
0852     struct snd_soc_pcm_runtime *prtd = asoc_substream_to_rtd(substream);
0853     struct audio_drv_data *adata = dev_get_drvdata(component->dev);
0854     struct snd_soc_card *card = prtd->card;
0855     struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
0856 
0857     runtime = substream->runtime;
0858     rtd = runtime->private_data;
0859 
0860     if (WARN_ON(!rtd))
0861         return -EINVAL;
0862 
0863     if (pinfo) {
0864         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0865             rtd->i2s_instance = pinfo->play_i2s_instance;
0866         } else {
0867             rtd->i2s_instance = pinfo->cap_i2s_instance;
0868             rtd->capture_channel = pinfo->capture_channel;
0869         }
0870     }
0871     if (adata->asic_type == CHIP_STONEY) {
0872         val = acp_reg_read(adata->acp_mmio,
0873                    mmACP_I2S_16BIT_RESOLUTION_EN);
0874         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0875             switch (rtd->i2s_instance) {
0876             case I2S_BT_INSTANCE:
0877                 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
0878                 break;
0879             case I2S_MICSP_INSTANCE:
0880                 val |= ACP_I2S_MICSP_16BIT_RESOLUTION_EN;
0881                 break;
0882             case I2S_SP_INSTANCE:
0883             default:
0884                 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
0885             }
0886         } else {
0887             switch (rtd->i2s_instance) {
0888             case I2S_BT_INSTANCE:
0889                 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
0890                 break;
0891             case I2S_MICSP_INSTANCE:
0892             case I2S_SP_INSTANCE:
0893             default:
0894                 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
0895             }
0896         }
0897         acp_reg_write(val, adata->acp_mmio,
0898                   mmACP_I2S_16BIT_RESOLUTION_EN);
0899     }
0900 
0901     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0902         switch (rtd->i2s_instance) {
0903         case I2S_BT_INSTANCE:
0904             rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
0905             rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
0906             rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
0907             rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
0908             rtd->destination = TO_BLUETOOTH;
0909             rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
0910             rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
0911             rtd->byte_cnt_high_reg_offset =
0912                     mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
0913             rtd->byte_cnt_low_reg_offset =
0914                     mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
0915             adata->play_i2sbt_stream = substream;
0916             break;
0917         case I2S_MICSP_INSTANCE:
0918             switch (adata->asic_type) {
0919             case CHIP_STONEY:
0920                 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
0921                 break;
0922             default:
0923                 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
0924             }
0925             rtd->ch1 = SYSRAM_TO_ACP_MICSP_INSTANCE_CH_NUM;
0926             rtd->ch2 = ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM;
0927             rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
0928             rtd->destination = TO_ACP_I2S_2;
0929             rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH4;
0930             rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH5;
0931             rtd->byte_cnt_high_reg_offset =
0932                     mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH;
0933             rtd->byte_cnt_low_reg_offset =
0934                     mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW;
0935 
0936             adata->play_i2s_micsp_stream = substream;
0937             break;
0938         case I2S_SP_INSTANCE:
0939         default:
0940             switch (adata->asic_type) {
0941             case CHIP_STONEY:
0942                 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
0943                 break;
0944             default:
0945                 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
0946             }
0947             rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
0948             rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
0949             rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
0950             rtd->destination = TO_ACP_I2S_1;
0951             rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
0952             rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
0953             rtd->byte_cnt_high_reg_offset =
0954                     mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
0955             rtd->byte_cnt_low_reg_offset =
0956                     mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
0957             adata->play_i2ssp_stream = substream;
0958         }
0959     } else {
0960         switch (rtd->i2s_instance) {
0961         case I2S_BT_INSTANCE:
0962             rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
0963             rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
0964             rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
0965             rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
0966             rtd->destination = FROM_BLUETOOTH;
0967             rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
0968             rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
0969             rtd->byte_cnt_high_reg_offset =
0970                     mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
0971             rtd->byte_cnt_low_reg_offset =
0972                     mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
0973             rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11;
0974             adata->capture_i2sbt_stream = substream;
0975             break;
0976         case I2S_MICSP_INSTANCE:
0977         case I2S_SP_INSTANCE:
0978         default:
0979             rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
0980             rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM;
0981             rtd->ch2 = ACP_TO_SYSRAM_CH_NUM;
0982             switch (adata->asic_type) {
0983             case CHIP_STONEY:
0984                 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
0985                 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
0986                 break;
0987             default:
0988                 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
0989                 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
0990             }
0991             rtd->destination = FROM_ACP_I2S_1;
0992             rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
0993             rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
0994             rtd->byte_cnt_high_reg_offset =
0995                     mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
0996             rtd->byte_cnt_low_reg_offset =
0997                     mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
0998             rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15;
0999             adata->capture_i2ssp_stream = substream;
1000         }
1001     }
1002 
1003     size = params_buffer_bytes(params);
1004 
1005     acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
1006     /* Save for runtime private data */
1007     rtd->dma_addr = runtime->dma_addr;
1008     rtd->order = get_order(size);
1009 
1010     /* Fill the page table entries in ACP SRAM */
1011     rtd->size = size;
1012     rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1013     rtd->direction = substream->stream;
1014 
1015     config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
1016     return 0;
1017 }
1018 
1019 static u64 acp_get_byte_count(struct audio_substream_data *rtd)
1020 {
1021     union acp_dma_count byte_count;
1022 
1023     byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
1024                           rtd->byte_cnt_high_reg_offset);
1025     byte_count.bcount.low  = acp_reg_read(rtd->acp_mmio,
1026                           rtd->byte_cnt_low_reg_offset);
1027     return byte_count.bytescount;
1028 }
1029 
1030 static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component,
1031                      struct snd_pcm_substream *substream)
1032 {
1033     u32 buffersize;
1034     u32 pos = 0;
1035     u64 bytescount = 0;
1036     u16 dscr;
1037     u32 period_bytes, delay;
1038 
1039     struct snd_pcm_runtime *runtime = substream->runtime;
1040     struct audio_substream_data *rtd = runtime->private_data;
1041     struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1042 
1043     if (!rtd)
1044         return -EINVAL;
1045 
1046     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1047         period_bytes = frames_to_bytes(runtime, runtime->period_size);
1048         bytescount = acp_get_byte_count(rtd);
1049         if (bytescount >= rtd->bytescount)
1050             bytescount -= rtd->bytescount;
1051         if (bytescount < period_bytes) {
1052             pos = 0;
1053         } else {
1054             dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr);
1055             if (dscr == rtd->dma_dscr_idx_1)
1056                 pos = period_bytes;
1057             else
1058                 pos = 0;
1059         }
1060         if (bytescount > 0) {
1061             delay = do_div(bytescount, period_bytes);
1062             adata->delay += bytes_to_frames(runtime, delay);
1063         }
1064     } else {
1065         buffersize = frames_to_bytes(runtime, runtime->buffer_size);
1066         bytescount = acp_get_byte_count(rtd);
1067         if (bytescount > rtd->bytescount)
1068             bytescount -= rtd->bytescount;
1069         pos = do_div(bytescount, buffersize);
1070     }
1071     return bytes_to_frames(runtime, pos);
1072 }
1073 
1074 static snd_pcm_sframes_t acp_dma_delay(struct snd_soc_component *component,
1075                        struct snd_pcm_substream *substream)
1076 {
1077     struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1078     snd_pcm_sframes_t delay = adata->delay;
1079 
1080     adata->delay = 0;
1081 
1082     return delay;
1083 }
1084 
1085 static int acp_dma_prepare(struct snd_soc_component *component,
1086                struct snd_pcm_substream *substream)
1087 {
1088     struct snd_pcm_runtime *runtime = substream->runtime;
1089     struct audio_substream_data *rtd = runtime->private_data;
1090     u16 ch_acp_sysmem, ch_acp_i2s;
1091 
1092     if (!rtd)
1093         return -EINVAL;
1094 
1095     if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
1096         ch_acp_sysmem = rtd->ch1;
1097         ch_acp_i2s = rtd->ch2;
1098     } else {
1099         ch_acp_i2s = rtd->ch1;
1100         ch_acp_sysmem = rtd->ch2;
1101     }
1102     config_acp_dma_channel(rtd->acp_mmio,
1103                    ch_acp_sysmem,
1104                    rtd->dma_dscr_idx_1,
1105                    NUM_DSCRS_PER_CHANNEL, 0);
1106     config_acp_dma_channel(rtd->acp_mmio,
1107                    ch_acp_i2s,
1108                    rtd->dma_dscr_idx_2,
1109                    NUM_DSCRS_PER_CHANNEL, 0);
1110     return 0;
1111 }
1112 
1113 static int acp_dma_trigger(struct snd_soc_component *component,
1114                struct snd_pcm_substream *substream, int cmd)
1115 {
1116     int ret;
1117 
1118     struct snd_pcm_runtime *runtime = substream->runtime;
1119     struct audio_substream_data *rtd = runtime->private_data;
1120 
1121     if (!rtd)
1122         return -EINVAL;
1123     switch (cmd) {
1124     case SNDRV_PCM_TRIGGER_START:
1125     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1126     case SNDRV_PCM_TRIGGER_RESUME:
1127         rtd->bytescount = acp_get_byte_count(rtd);
1128         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1129             if (rtd->capture_channel == CAP_CHANNEL0) {
1130                 acp_dma_cap_channel_disable(rtd->acp_mmio,
1131                                 CAP_CHANNEL1);
1132                 acp_dma_cap_channel_enable(rtd->acp_mmio,
1133                                CAP_CHANNEL0);
1134             }
1135             if (rtd->capture_channel == CAP_CHANNEL1) {
1136                 acp_dma_cap_channel_disable(rtd->acp_mmio,
1137                                 CAP_CHANNEL0);
1138                 acp_dma_cap_channel_enable(rtd->acp_mmio,
1139                                CAP_CHANNEL1);
1140             }
1141             acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1142         } else {
1143             acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1144             acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
1145         }
1146         ret = 0;
1147         break;
1148     case SNDRV_PCM_TRIGGER_STOP:
1149     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1150     case SNDRV_PCM_TRIGGER_SUSPEND:
1151         acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1152         ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1153         break;
1154     default:
1155         ret = -EINVAL;
1156     }
1157     return ret;
1158 }
1159 
1160 static int acp_dma_new(struct snd_soc_component *component,
1161                struct snd_soc_pcm_runtime *rtd)
1162 {
1163     struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1164     struct device *parent = component->dev->parent;
1165 
1166     switch (adata->asic_type) {
1167     case CHIP_STONEY:
1168         snd_pcm_set_managed_buffer_all(rtd->pcm,
1169                            SNDRV_DMA_TYPE_DEV,
1170                            parent,
1171                            ST_MIN_BUFFER,
1172                            ST_MAX_BUFFER);
1173         break;
1174     default:
1175         snd_pcm_set_managed_buffer_all(rtd->pcm,
1176                            SNDRV_DMA_TYPE_DEV,
1177                            parent,
1178                            MIN_BUFFER,
1179                            MAX_BUFFER);
1180         break;
1181     }
1182     return 0;
1183 }
1184 
1185 static int acp_dma_close(struct snd_soc_component *component,
1186              struct snd_pcm_substream *substream)
1187 {
1188     u16 bank;
1189     struct snd_pcm_runtime *runtime = substream->runtime;
1190     struct audio_substream_data *rtd = runtime->private_data;
1191     struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1192 
1193     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1194         switch (rtd->i2s_instance) {
1195         case I2S_BT_INSTANCE:
1196             adata->play_i2sbt_stream = NULL;
1197             break;
1198         case I2S_MICSP_INSTANCE:
1199             adata->play_i2s_micsp_stream = NULL;
1200             break;
1201         case I2S_SP_INSTANCE:
1202         default:
1203             adata->play_i2ssp_stream = NULL;
1204             /*
1205              * For Stoney, Memory gating is disabled,i.e SRAM Banks
1206              * won't be turned off. The default state for SRAM banks
1207              * is ON.Setting SRAM bank state code skipped for STONEY
1208              * platform. Added condition checks for Carrizo platform
1209              * only.
1210              */
1211             if (adata->asic_type != CHIP_STONEY) {
1212                 for (bank = 1; bank <= 4; bank++)
1213                     acp_set_sram_bank_state(adata->acp_mmio,
1214                                 bank, false);
1215             }
1216         }
1217     } else  {
1218         switch (rtd->i2s_instance) {
1219         case I2S_BT_INSTANCE:
1220             adata->capture_i2sbt_stream = NULL;
1221             break;
1222         case I2S_MICSP_INSTANCE:
1223         case I2S_SP_INSTANCE:
1224         default:
1225             adata->capture_i2ssp_stream = NULL;
1226             if (adata->asic_type != CHIP_STONEY) {
1227                 for (bank = 5; bank <= 8; bank++)
1228                     acp_set_sram_bank_state(adata->acp_mmio,
1229                                 bank, false);
1230             }
1231         }
1232     }
1233 
1234     /*
1235      * Disable ACP irq, when the current stream is being closed and
1236      * another stream is also not active.
1237      */
1238     if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
1239         !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream &&
1240         !adata->play_i2s_micsp_stream)
1241         acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1242     kfree(rtd);
1243     return 0;
1244 }
1245 
1246 static const struct snd_soc_component_driver acp_asoc_platform = {
1247     .name       = DRV_NAME,
1248     .open       = acp_dma_open,
1249     .close      = acp_dma_close,
1250     .hw_params  = acp_dma_hw_params,
1251     .trigger    = acp_dma_trigger,
1252     .pointer    = acp_dma_pointer,
1253     .delay      = acp_dma_delay,
1254     .prepare    = acp_dma_prepare,
1255     .pcm_construct  = acp_dma_new,
1256 };
1257 
1258 static int acp_audio_probe(struct platform_device *pdev)
1259 {
1260     int status, irq;
1261     struct audio_drv_data *audio_drv_data;
1262     const u32 *pdata = pdev->dev.platform_data;
1263 
1264     if (!pdata) {
1265         dev_err(&pdev->dev, "Missing platform data\n");
1266         return -ENODEV;
1267     }
1268 
1269     audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
1270                       GFP_KERNEL);
1271     if (!audio_drv_data)
1272         return -ENOMEM;
1273 
1274     audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0);
1275     if (IS_ERR(audio_drv_data->acp_mmio))
1276         return PTR_ERR(audio_drv_data->acp_mmio);
1277 
1278     /*
1279      * The following members gets populated in device 'open'
1280      * function. Till then interrupts are disabled in 'acp_init'
1281      * and device doesn't generate any interrupts.
1282      */
1283 
1284     audio_drv_data->play_i2ssp_stream = NULL;
1285     audio_drv_data->capture_i2ssp_stream = NULL;
1286     audio_drv_data->play_i2sbt_stream = NULL;
1287     audio_drv_data->capture_i2sbt_stream = NULL;
1288     audio_drv_data->play_i2s_micsp_stream = NULL;
1289 
1290     audio_drv_data->asic_type =  *pdata;
1291 
1292     irq = platform_get_irq(pdev, 0);
1293     if (irq < 0)
1294         return -ENODEV;
1295 
1296     status = devm_request_irq(&pdev->dev, irq, dma_irq_handler,
1297                   0, "ACP_IRQ", &pdev->dev);
1298     if (status) {
1299         dev_err(&pdev->dev, "ACP IRQ request failed\n");
1300         return status;
1301     }
1302 
1303     dev_set_drvdata(&pdev->dev, audio_drv_data);
1304 
1305     /* Initialize the ACP */
1306     status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
1307     if (status) {
1308         dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
1309         return status;
1310     }
1311 
1312     status = devm_snd_soc_register_component(&pdev->dev,
1313                          &acp_asoc_platform, NULL, 0);
1314     if (status != 0) {
1315         dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
1316         return status;
1317     }
1318 
1319     pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
1320     pm_runtime_use_autosuspend(&pdev->dev);
1321     pm_runtime_enable(&pdev->dev);
1322 
1323     return status;
1324 }
1325 
1326 static int acp_audio_remove(struct platform_device *pdev)
1327 {
1328     int status;
1329     struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
1330 
1331     status = acp_deinit(adata->acp_mmio);
1332     if (status)
1333         dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
1334     pm_runtime_disable(&pdev->dev);
1335 
1336     return 0;
1337 }
1338 
1339 static int acp_pcm_resume(struct device *dev)
1340 {
1341     u16 bank;
1342     int status;
1343     struct audio_substream_data *rtd;
1344     struct audio_drv_data *adata = dev_get_drvdata(dev);
1345 
1346     status = acp_init(adata->acp_mmio, adata->asic_type);
1347     if (status) {
1348         dev_err(dev, "ACP Init failed status:%d\n", status);
1349         return status;
1350     }
1351 
1352     if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
1353         /*
1354          * For Stoney, Memory gating is disabled,i.e SRAM Banks
1355          * won't be turned off. The default state for SRAM banks is ON.
1356          * Setting SRAM bank state code skipped for STONEY platform.
1357          */
1358         if (adata->asic_type != CHIP_STONEY) {
1359             for (bank = 1; bank <= 4; bank++)
1360                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1361                             true);
1362         }
1363         rtd = adata->play_i2ssp_stream->runtime->private_data;
1364         config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1365     }
1366     if (adata->capture_i2ssp_stream &&
1367         adata->capture_i2ssp_stream->runtime) {
1368         if (adata->asic_type != CHIP_STONEY) {
1369             for (bank = 5; bank <= 8; bank++)
1370                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1371                             true);
1372         }
1373         rtd =  adata->capture_i2ssp_stream->runtime->private_data;
1374         config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1375     }
1376     if (adata->asic_type != CHIP_CARRIZO) {
1377         if (adata->play_i2s_micsp_stream &&
1378             adata->play_i2s_micsp_stream->runtime) {
1379             rtd = adata->play_i2s_micsp_stream->runtime->private_data;
1380             config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1381         }
1382         if (adata->play_i2sbt_stream &&
1383             adata->play_i2sbt_stream->runtime) {
1384             rtd = adata->play_i2sbt_stream->runtime->private_data;
1385             config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1386         }
1387         if (adata->capture_i2sbt_stream &&
1388             adata->capture_i2sbt_stream->runtime) {
1389             rtd = adata->capture_i2sbt_stream->runtime->private_data;
1390             config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1391         }
1392     }
1393     acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1394     return 0;
1395 }
1396 
1397 static int acp_pcm_runtime_suspend(struct device *dev)
1398 {
1399     int status;
1400     struct audio_drv_data *adata = dev_get_drvdata(dev);
1401 
1402     status = acp_deinit(adata->acp_mmio);
1403     if (status)
1404         dev_err(dev, "ACP Deinit failed status:%d\n", status);
1405     acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1406     return 0;
1407 }
1408 
1409 static int acp_pcm_runtime_resume(struct device *dev)
1410 {
1411     int status;
1412     struct audio_drv_data *adata = dev_get_drvdata(dev);
1413 
1414     status = acp_init(adata->acp_mmio, adata->asic_type);
1415     if (status) {
1416         dev_err(dev, "ACP Init failed status:%d\n", status);
1417         return status;
1418     }
1419     acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1420     return 0;
1421 }
1422 
1423 static const struct dev_pm_ops acp_pm_ops = {
1424     .resume = acp_pcm_resume,
1425     .runtime_suspend = acp_pcm_runtime_suspend,
1426     .runtime_resume = acp_pcm_runtime_resume,
1427 };
1428 
1429 static struct platform_driver acp_dma_driver = {
1430     .probe = acp_audio_probe,
1431     .remove = acp_audio_remove,
1432     .driver = {
1433         .name = DRV_NAME,
1434         .pm = &acp_pm_ops,
1435     },
1436 };
1437 
1438 module_platform_driver(acp_dma_driver);
1439 
1440 MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1441 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
1442 MODULE_DESCRIPTION("AMD ACP PCM Driver");
1443 MODULE_LICENSE("GPL v2");
1444 MODULE_ALIAS("platform:"DRV_NAME);
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