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0011 #define G2_FIFO 0xa05f688c
0012 #define SPU_MEMORY_BASE 0xA0800000
0013 #define ARM_RESET_REGISTER 0xA0702C00
0014 #define SPU_REGISTER_BASE 0xA0700000
0015
0016
0017 #define AICA_CONTROL_POINT 0xA0810000
0018 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
0019 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
0020
0021
0022 #define AICA_CMD_KICK 0x80000000
0023 #define AICA_CMD_NONE 0
0024 #define AICA_CMD_START 1
0025 #define AICA_CMD_STOP 2
0026 #define AICA_CMD_VOL 3
0027
0028
0029 #define SM_8BIT 1
0030 #define SM_16BIT 0
0031 #define SM_ADPCM 2
0032
0033
0034 #define AICA_BUFFER_SIZE 0x8000
0035 #define AICA_PERIOD_SIZE 0x800
0036 #define AICA_PERIOD_NUMBER 16
0037
0038 #define AICA_CHANNEL0_OFFSET 0x11000
0039 #define AICA_CHANNEL1_OFFSET 0x21000
0040 #define CHANNEL_OFFSET 0x10000
0041
0042 #define AICA_DMA_CHANNEL 5
0043 #define AICA_DMA_MODE 5
0044
0045 #define SND_AICA_DRIVER "AICA"
0046
0047 struct aica_channel {
0048 uint32_t cmd;
0049 uint32_t pos;
0050 uint32_t length;
0051 uint32_t freq;
0052 uint32_t vol;
0053 uint32_t pan;
0054 uint32_t sfmt;
0055 uint32_t flags;
0056 };
0057
0058 struct snd_card_aica {
0059 struct work_struct spu_dma_work;
0060 struct snd_card *card;
0061 struct aica_channel *channel;
0062 struct snd_pcm_substream *substream;
0063 int clicks;
0064 int current_period;
0065 struct timer_list timer;
0066 int master_volume;
0067 int dma_check;
0068 };