sound/ppc/snd_ps3_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Audio support for PS3
0004  * Copyright (C) 2007 Sony Computer Entertainment Inc.
0005  * Copyright 2006, 2007 Sony Corporation
0006  * All rights reserved.
0007  */
0008
0009 /*
0010  * interrupt / configure registers
0011  */
0012
0013 #define PS3_AUDIO_INTR_0                 (0x00000100)
0014 #define PS3_AUDIO_INTR_EN_0              (0x00000140)
0015 #define PS3_AUDIO_CONFIG                 (0x00000200)
0016
0017 /*
0018  * DMAC registers
0019  * n:0..9
0020  */
0021 #define PS3_AUDIO_DMAC_REGBASE(x)         (0x0000210 + 0x20 * (x))
0022
0023 #define PS3_AUDIO_KICK(n)                 (PS3_AUDIO_DMAC_REGBASE(n) + 0x00)
0024 #define PS3_AUDIO_SOURCE(n)               (PS3_AUDIO_DMAC_REGBASE(n) + 0x04)
0025 #define PS3_AUDIO_DEST(n)                 (PS3_AUDIO_DMAC_REGBASE(n) + 0x08)
0026 #define PS3_AUDIO_DMASIZE(n)              (PS3_AUDIO_DMAC_REGBASE(n) + 0x0C)
0027
0028 /*
0029  * mute control
0030  */
0031 #define PS3_AUDIO_AX_MCTRL                (0x00004000)
0032 #define PS3_AUDIO_AX_ISBP                 (0x00004004)
0033 #define PS3_AUDIO_AX_AOBP                 (0x00004008)
0034 #define PS3_AUDIO_AX_IC                   (0x00004010)
0035 #define PS3_AUDIO_AX_IE                   (0x00004014)
0036 #define PS3_AUDIO_AX_IS                   (0x00004018)
0037
0038 /*
0039  * three wire serial
0040  * n:0..3
0041  */
0042 #define PS3_AUDIO_AO_MCTRL                (0x00006000)
0043 #define PS3_AUDIO_AO_3WMCTRL              (0x00006004)
0044
0045 #define PS3_AUDIO_AO_3WCTRL(n)            (0x00006200 + 0x200 * (n))
0046
0047 /*
0048  * S/PDIF
0049  * n:0..1
0050  * x:0..11
0051  * y:0..5
0052  */
0053 #define PS3_AUDIO_AO_SPD_REGBASE(n)       (0x00007200 + 0x200 * (n))
0054
0055 #define PS3_AUDIO_AO_SPDCTRL(n) \
0056     (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x00)
0057 #define PS3_AUDIO_AO_SPDUB(n, x) \
0058     (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x04 + 0x04 * (x))
0059 #define PS3_AUDIO_AO_SPDCS(n, y) \
0060     (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x34 + 0x04 * (y))
0061
0062
0063 /*
0064   PS3_AUDIO_INTR_0 register tells an interrupt handler which audio
0065   DMA channel triggered the interrupt.  The interrupt status for a channel
0066   can be cleared by writing a '1' to the corresponding bit.  A new interrupt
0067   cannot be generated until the previous interrupt has been cleared.
0068
0069   Note that the status reported by PS3_AUDIO_INTR_0 is independent of the
0070   value of PS3_AUDIO_INTR_EN_0.
0071
0072  31            24 23           16 15            8 7             0
0073  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0074  |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_0
0075  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0076 */
0077 #define PS3_AUDIO_INTR_0_CHAN(n)    (1 << ((n) * 2))
0078 #define PS3_AUDIO_INTR_0_CHAN9     PS3_AUDIO_INTR_0_CHAN(9)
0079 #define PS3_AUDIO_INTR_0_CHAN8     PS3_AUDIO_INTR_0_CHAN(8)
0080 #define PS3_AUDIO_INTR_0_CHAN7     PS3_AUDIO_INTR_0_CHAN(7)
0081 #define PS3_AUDIO_INTR_0_CHAN6     PS3_AUDIO_INTR_0_CHAN(6)
0082 #define PS3_AUDIO_INTR_0_CHAN5     PS3_AUDIO_INTR_0_CHAN(5)
0083 #define PS3_AUDIO_INTR_0_CHAN4     PS3_AUDIO_INTR_0_CHAN(4)
0084 #define PS3_AUDIO_INTR_0_CHAN3     PS3_AUDIO_INTR_0_CHAN(3)
0085 #define PS3_AUDIO_INTR_0_CHAN2     PS3_AUDIO_INTR_0_CHAN(2)
0086 #define PS3_AUDIO_INTR_0_CHAN1     PS3_AUDIO_INTR_0_CHAN(1)
0087 #define PS3_AUDIO_INTR_0_CHAN0     PS3_AUDIO_INTR_0_CHAN(0)
0088
0089 /*
0090   The PS3_AUDIO_INTR_EN_0 register specifies which DMA channels can generate
0091   an interrupt to the PU.  Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the
0092   corresponding bit in PS3_AUDIO_INTR_0.  The resulting bits are OR'd together
0093   to generate the Audio interrupt.
0094
0095  31            24 23           16 15            8 7             0
0096  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0097  |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_EN_0
0098  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0099
0100   Bit assignments are same as PS3_AUDIO_INTR_0
0101 */
0102
0103 /*
0104   PS3_AUDIO_CONFIG
0105   31            24 23           16 15            8 7             0
0106  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0107  |0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 C|0 0 0 0 0 0 0 0| CONFIG
0108  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0109
0110 */
0111
0112 /* The CLEAR field cancels all pending transfers, and stops any running DMA
0113    transfers.  Any interrupts associated with the canceled transfers
0114    will occur as if the transfer had finished.
0115    Since this bit is designed to recover from DMA related issues
0116    which are caused by unpredictable situations, it is preferred to wait
0117    for normal DMA transfer end without using this bit.
0118 */
0119 #define PS3_AUDIO_CONFIG_CLEAR          (1 << 8)  /* RWIVF */
0120
0121 /*
0122   PS3_AUDIO_AX_MCTRL: Audio Port Mute Control Register
0123
0124  31            24 23           16 15            8 7             0
0125  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0126  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|A|A|0 0 0 0 0 0 0|S|S|A|A|A|A| AX_MCTRL
0127  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0128 */
0129
0130 /* 3 Wire Audio Serial Output Channel Mutes (0..3)  */
0131 #define PS3_AUDIO_AX_MCTRL_ASOMT(n)     (1 << (3 - (n)))  /* RWIVF */
0132 #define PS3_AUDIO_AX_MCTRL_ASO3MT       (1 << 0)          /* RWIVF */
0133 #define PS3_AUDIO_AX_MCTRL_ASO2MT       (1 << 1)          /* RWIVF */
0134 #define PS3_AUDIO_AX_MCTRL_ASO1MT       (1 << 2)          /* RWIVF */
0135 #define PS3_AUDIO_AX_MCTRL_ASO0MT       (1 << 3)          /* RWIVF */
0136
0137 /* S/PDIF mutes (0,1)*/
0138 #define PS3_AUDIO_AX_MCTRL_SPOMT(n)     (1 << (5 - (n)))  /* RWIVF */
0139 #define PS3_AUDIO_AX_MCTRL_SPO1MT       (1 << 4)          /* RWIVF */
0140 #define PS3_AUDIO_AX_MCTRL_SPO0MT       (1 << 5)          /* RWIVF */
0141
0142 /* All 3 Wire Serial Outputs Mute */
0143 #define PS3_AUDIO_AX_MCTRL_AASOMT       (1 << 13)         /* RWIVF */
0144
0145 /* All S/PDIF Mute */
0146 #define PS3_AUDIO_AX_MCTRL_ASPOMT       (1 << 14)         /* RWIVF */
0147
0148 /* All Audio Outputs Mute */
0149 #define PS3_AUDIO_AX_MCTRL_AAOMT        (1 << 15)         /* RWIVF */
0150
0151 /*
0152   S/PDIF Outputs Buffer Read/Write Pointer Register
0153
0154  31            24 23           16 15            8 7             0
0155  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0156  |0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B| AX_ISBP
0157  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0158
0159 */
0160 /*
0161  S/PDIF Output Channel Read Buffer Numbers
0162  Buffer number is  value of field.
0163  Indicates current read access buffer ID from Audio Data
0164  Transfer controller of S/PDIF Output
0165 */
0166
0167 #define PS3_AUDIO_AX_ISBP_SPOBRN_MASK(n) (0x7 << 4 * (1 - (n))) /* R-IUF */
0168 #define PS3_AUDIO_AX_ISBP_SPO1BRN_MASK      (0x7 << 0) /* R-IUF */
0169 #define PS3_AUDIO_AX_ISBP_SPO0BRN_MASK      (0x7 << 4) /* R-IUF */
0170
0171 /*
0172 S/PDIF Output Channel Buffer Write Numbers
0173 Indicates current write access buffer ID from bus master.
0174 */
0175 #define PS3_AUDIO_AX_ISBP_SPOBWN_MASK(n) (0x7 <<  4 * (5 - (n))) /* R-IUF */
0176 #define PS3_AUDIO_AX_ISBP_SPO1BWN_MASK      (0x7 << 16) /* R-IUF */
0177 #define PS3_AUDIO_AX_ISBP_SPO0BWN_MASK      (0x7 << 20) /* R-IUF */
0178
0179 /*
0180   3 Wire Audio Serial Outputs Buffer Read/Write
0181   Pointer Register
0182   Buffer number is  value of field
0183
0184  31            24 23           16 15            8 7             0
0185  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0186  |0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B| AX_AOBP
0187  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0188 */
0189
0190 /*
0191 3 Wire Audio Serial Output Channel Buffer Read Numbers
0192 Indicates current read access buffer Id from Audio Data Transfer
0193 Controller of 3 Wire Audio Serial Output Channels
0194 */
0195 #define PS3_AUDIO_AX_AOBP_ASOBRN_MASK(n) (0x7 << 4 * (3 - (n))) /* R-IUF */
0196
0197 #define PS3_AUDIO_AX_AOBP_ASO3BRN_MASK  (0x7 << 0) /* R-IUF */
0198 #define PS3_AUDIO_AX_AOBP_ASO2BRN_MASK  (0x7 << 4) /* R-IUF */
0199 #define PS3_AUDIO_AX_AOBP_ASO1BRN_MASK  (0x7 << 8) /* R-IUF */
0200 #define PS3_AUDIO_AX_AOBP_ASO0BRN_MASK  (0x7 << 12) /* R-IUF */
0201
0202 /*
0203 3 Wire Audio Serial Output Channel Buffer Write Numbers
0204 Indicates current write access buffer ID from bus master.
0205 */
0206 #define PS3_AUDIO_AX_AOBP_ASOBWN_MASK(n) (0x7 << 4 * (7 - (n))) /* R-IUF */
0207
0208 #define PS3_AUDIO_AX_AOBP_ASO3BWN_MASK        (0x7 << 16) /* R-IUF */
0209 #define PS3_AUDIO_AX_AOBP_ASO2BWN_MASK        (0x7 << 20) /* R-IUF */
0210 #define PS3_AUDIO_AX_AOBP_ASO1BWN_MASK        (0x7 << 24) /* R-IUF */
0211 #define PS3_AUDIO_AX_AOBP_ASO0BWN_MASK        (0x7 << 28) /* R-IUF */
0212
0213
0214
0215 /*
0216 Audio Port Interrupt Condition Register
0217 For the fields in this register, the following values apply:
0218 0 = Interrupt is generated every interrupt event.
0219 1 = Interrupt is generated every 2 interrupt events.
0220 2 = Interrupt is generated every 4 interrupt events.
0221 3 = Reserved
0222
0223
0224  31            24 23           16 15            8 7             0
0225  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0226  |0 0 0 0 0 0 0 0|0 0|SPO|0 0|SPO|0 0|AAS|0 0 0 0 0 0 0 0 0 0 0 0| AX_IC
0227  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0228 */
0229 /*
0230 All 3-Wire Audio Serial Outputs Interrupt Mode
0231 Configures the Interrupt and Signal Notification
0232 condition of all 3-wire Audio Serial Outputs.
0233 */
0234 #define PS3_AUDIO_AX_IC_AASOIMD_MASK          (0x3 << 12) /* RWIVF */
0235 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1        (0x0 << 12) /* RWI-V */
0236 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2        (0x1 << 12) /* RW--V */
0237 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY4        (0x2 << 12) /* RW--V */
0238
0239 /*
0240 S/PDIF Output Channel Interrupt Modes
0241 Configures the Interrupt and signal Notification
0242 conditions of S/PDIF output channels.
0243 */
0244 #define PS3_AUDIO_AX_IC_SPO1IMD_MASK          (0x3 << 16) /* RWIVF */
0245 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY1        (0x0 << 16) /* RWI-V */
0246 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2        (0x1 << 16) /* RW--V */
0247 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY4        (0x2 << 16) /* RW--V */
0248
0249 #define PS3_AUDIO_AX_IC_SPO0IMD_MASK          (0x3 << 20) /* RWIVF */
0250 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY1        (0x0 << 20) /* RWI-V */
0251 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2        (0x1 << 20) /* RW--V */
0252 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY4        (0x2 << 20) /* RW--V */
0253
0254 /*
0255 Audio Port interrupt Enable Register
0256 Configures whether to enable or disable each Interrupt Generation.
0257
0258
0259  31            24 23           16 15            8 7             0
0260  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0261  |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IE
0262  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0263
0264 */
0265
0266 /*
0267 3 Wire Audio Serial Output Channel Buffer Underflow
0268 Interrupt Enables
0269 Select enable/disable of Buffer Underflow Interrupts for
0270 3-Wire Audio Serial Output Channels
0271 DISABLED=Interrupt generation disabled.
0272 */
0273 #define PS3_AUDIO_AX_IE_ASOBUIE(n)      (1 << (3 - (n))) /* RWIVF */
0274 #define PS3_AUDIO_AX_IE_ASO3BUIE        (1 << 0) /* RWIVF */
0275 #define PS3_AUDIO_AX_IE_ASO2BUIE        (1 << 1) /* RWIVF */
0276 #define PS3_AUDIO_AX_IE_ASO1BUIE        (1 << 2) /* RWIVF */
0277 #define PS3_AUDIO_AX_IE_ASO0BUIE        (1 << 3) /* RWIVF */
0278
0279 /* S/PDIF Output Channel Buffer Underflow Interrupt Enables */
0280
0281 #define PS3_AUDIO_AX_IE_SPOBUIE(n)      (1 << (7 - (n))) /* RWIVF */
0282 #define PS3_AUDIO_AX_IE_SPO1BUIE        (1 << 6) /* RWIVF */
0283 #define PS3_AUDIO_AX_IE_SPO0BUIE        (1 << 7) /* RWIVF */
0284
0285 /* S/PDIF Output Channel One Block Transfer Completion Interrupt Enables */
0286
0287 #define PS3_AUDIO_AX_IE_SPOBTCIE(n)     (1 << (11 - (n))) /* RWIVF */
0288 #define PS3_AUDIO_AX_IE_SPO1BTCIE       (1 << 10) /* RWIVF */
0289 #define PS3_AUDIO_AX_IE_SPO0BTCIE       (1 << 11) /* RWIVF */
0290
0291 /* 3-Wire Audio Serial Output Channel Buffer Empty Interrupt Enables */
0292
0293 #define PS3_AUDIO_AX_IE_ASOBEIE(n)      (1 << (19 - (n))) /* RWIVF */
0294 #define PS3_AUDIO_AX_IE_ASO3BEIE        (1 << 16) /* RWIVF */
0295 #define PS3_AUDIO_AX_IE_ASO2BEIE        (1 << 17) /* RWIVF */
0296 #define PS3_AUDIO_AX_IE_ASO1BEIE        (1 << 18) /* RWIVF */
0297 #define PS3_AUDIO_AX_IE_ASO0BEIE        (1 << 19) /* RWIVF */
0298
0299 /* S/PDIF Output Channel Buffer Empty Interrupt Enables */
0300
0301 #define PS3_AUDIO_AX_IE_SPOBEIE(n)      (1 << (23 - (n))) /* RWIVF */
0302 #define PS3_AUDIO_AX_IE_SPO1BEIE        (1 << 22) /* RWIVF */
0303 #define PS3_AUDIO_AX_IE_SPO0BEIE        (1 << 23) /* RWIVF */
0304
0305 /*
0306 Audio Port Interrupt Status Register
0307 Indicates Interrupt status, which interrupt has occurred, and can clear
0308 each interrupt in this register.
0309 Writing 1b to a field containing 1b clears field and de-asserts interrupt.
0310 Writing 0b to a field has no effect.
0311 Field values are the following:
0312 0 - Interrupt hasn't occurred.
0313 1 - Interrupt has occurred.
0314
0315
0316  31            24 23           16 15            8 7             0
0317  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0318  |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IS
0319  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0320
0321  Bit assignment are same as AX_IE
0322 */
0323
0324 /*
0325 Audio Output Master Control Register
0326 Configures Master Clock and other master Audio Output Settings
0327
0328
0329  31            24 23           16 15            8 7             0
0330  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0331  |0|SCKSE|0|SCKSE|  MR0  |  MR1  |MCL|MCL|0 0 0 0|0 0 0 0 0 0 0 0| AO_MCTRL
0332  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0333 */
0334
0335 /*
0336 MCLK Output Control
0337 Controls mclko[1] output.
0338 0 - Disable output (fixed at High)
0339 1 - Output clock produced by clock selected
0340 with scksel1 by mr1
0341 2 - Reserved
0342 3 - Reserved
0343 */
0344
0345 #define PS3_AUDIO_AO_MCTRL_MCLKC1_MASK      (0x3 << 12) /* RWIVF */
0346 #define PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED  (0x0 << 12) /* RWI-V */
0347 #define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED   (0x1 << 12) /* RW--V */
0348 #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2    (0x2 << 12) /* RW--V */
0349 #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3    (0x3 << 12) /* RW--V */
0350
0351 /*
0352 MCLK Output Control
0353 Controls mclko[0] output.
0354 0 - Disable output (fixed at High)
0355 1 - Output clock produced by clock selected
0356 with SCKSEL0 by MR0
0357 2 - Reserved
0358 3 - Reserved
0359 */
0360 #define PS3_AUDIO_AO_MCTRL_MCLKC0_MASK      (0x3 << 14) /* RWIVF */
0361 #define PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED  (0x0 << 14) /* RWI-V */
0362 #define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED   (0x1 << 14) /* RW--V */
0363 #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2    (0x2 << 14) /* RW--V */
0364 #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3    (0x3 << 14) /* RW--V */
0365 /*
0366 Master Clock Rate 1
0367 Sets the divide ration of Master Clock1 (clock output from
0368 mclko[1] for the input clock selected by scksel1.
0369 */
0370 #define PS3_AUDIO_AO_MCTRL_MR1_MASK (0xf << 16)
0371 #define PS3_AUDIO_AO_MCTRL_MR1_DEFAULT  (0x0 << 16) /* RWI-V */
0372 /*
0373 Master Clock Rate 0
0374 Sets the divide ratio of Master Clock0 (clock output from
0375 mclko[0] for the input clock selected by scksel0).
0376 */
0377 #define PS3_AUDIO_AO_MCTRL_MR0_MASK (0xf << 20) /* RWIVF */
0378 #define PS3_AUDIO_AO_MCTRL_MR0_DEFAULT  (0x0 << 20) /* RWI-V */
0379 /*
0380 System Clock Select 0/1
0381 Selects the system clock to be used as Master Clock 0/1
0382 Input the system clock that is appropriate for the sampling
0383 rate.
0384 */
0385 #define PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK     (0x7 << 24) /* RWIVF */
0386 #define PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT  (0x2 << 24) /* RWI-V */
0387
0388 #define PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK     (0x7 << 28) /* RWIVF */
0389 #define PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT  (0x2 << 28) /* RWI-V */
0390
0391
0392 /*
0393 3-Wire Audio Output Master Control Register
0394 Configures clock, 3-Wire Audio Serial Output Enable, and
0395 other 3-Wire Audio Serial Output Master Settings
0396
0397
0398  31            24 23           16 15            8 7             0
0399  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0400  |A|A|A|A|0 0 0|A| ASOSR |0 0 0 0|A|A|A|A|A|A|0|1|0 0 0 0 0 0 0 0| AO_3WMCTRL
0401  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0402 */
0403
0404
0405 /*
0406 LRCKO Polarity
0407 0 - Reserved
0408 1 - default
0409 */
0410 #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK       (1 << 8) /* RWIVF */
0411 #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT   (1 << 8) /* RW--V */
0412
0413 /* LRCK Output Disable */
0414
0415 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD       (1 << 10) /* RWIVF */
0416 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED   (0 << 10) /* RW--V */
0417 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED  (1 << 10) /* RWI-V */
0418
0419 /* Bit Clock Output Disable */
0420
0421 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD       (1 << 11) /* RWIVF */
0422 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED   (0 << 11) /* RW--V */
0423 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED  (1 << 11) /* RWI-V */
0424
0425 /*
0426 3-Wire Audio Serial Output Channel 0-3 Operational
0427 Status.  Each bit becomes 1 after each 3-Wire Audio
0428 Serial Output Channel N is in action by setting 1 to
0429 asoen.
0430 Each bit becomes 0 after each 3-Wire Audio Serial Output
0431 Channel N is out of action by setting 0 to asoen.
0432 */
0433 #define PS3_AUDIO_AO_3WMCTRL_ASORUN(n)      (1 << (15 - (n))) /* R-IVF */
0434 #define PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(n)  (0 << (15 - (n))) /* R-I-V */
0435 #define PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(n)  (1 << (15 - (n))) /* R---V */
0436 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0        \
0437     PS3_AUDIO_AO_3WMCTRL_ASORUN(0)
0438 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED    \
0439     PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(0)
0440 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING    \
0441     PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(0)
0442 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1        \
0443     PS3_AUDIO_AO_3WMCTRL_ASORUN(1)
0444 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED    \
0445     PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(1)
0446 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING    \
0447     PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(1)
0448 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2        \
0449     PS3_AUDIO_AO_3WMCTRL_ASORUN(2)
0450 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED    \
0451     PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(2)
0452 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING    \
0453     PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(2)
0454 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3        \
0455     PS3_AUDIO_AO_3WMCTRL_ASORUN(3)
0456 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED    \
0457     PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(3)
0458 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING    \
0459     PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(3)
0460
0461 /*
0462 Sampling Rate
0463 Specifies the divide ratio of the bit clock (clock output
0464 from bclko) used by the 3-wire Audio Output Clock, which
0465 is applied to the master clock selected by mcksel.
0466 Data output is synchronized with this clock.
0467 */
0468 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK     (0xf << 20) /* RWIVF */
0469 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2     (0x1 << 20) /* RWI-V */
0470 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4     (0x2 << 20) /* RW--V */
0471 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8     (0x4 << 20) /* RW--V */
0472 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12    (0x6 << 20) /* RW--V */
0473
0474 /*
0475 Master Clock Select
0476 0 - Master Clock 0
0477 1 - Master Clock 1
0478 */
0479 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL      (1 << 24) /* RWIVF */
0480 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0 (0 << 24) /* RWI-V */
0481 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1 (1 << 24) /* RW--V */
0482
0483 /*
0484 Enables and disables 4ch 3-Wire Audio Serial Output
0485 operation.  Each Bit from 0 to 3 corresponds to an
0486 output channel, which means that each output channel
0487 can be enabled or disabled individually.  When
0488 multiple channels are enabled at the same time, output
0489 operations are performed in synchronization.
0490 Bit 0 - Output Channel 0 (SDOUT[0])
0491 Bit 1 - Output Channel 1 (SDOUT[1])
0492 Bit 2 - Output Channel 2 (SDOUT[2])
0493 Bit 3 - Output Channel 3 (SDOUT[3])
0494 */
0495 #define PS3_AUDIO_AO_3WMCTRL_ASOEN(n)       (1 << (31 - (n))) /* RWIVF */
0496 #define PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(n)  (0 << (31 - (n))) /* RWI-V */
0497 #define PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(n)   (1 << (31 - (n))) /* RW--V */
0498
0499 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0 \
0500     PS3_AUDIO_AO_3WMCTRL_ASOEN(0) /* RWIVF */
0501 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED \
0502     PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(0) /* RWI-V */
0503 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED \
0504     PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(0) /* RW--V */
0505 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0 \
0506     PS3_AUDIO_AO_3WMCTRL_ASOEN(1) /* RWIVF */
0507 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED \
0508     PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(1) /* RWI-V */
0509 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED \
0510     PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(1) /* RW--V */
0511 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0 \
0512     PS3_AUDIO_AO_3WMCTRL_ASOEN(2) /* RWIVF */
0513 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED \
0514     PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(2) /* RWI-V */
0515 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED \
0516     PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(2) /* RW--V */
0517 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0 \
0518     PS3_AUDIO_AO_3WMCTRL_ASOEN(3) /* RWIVF */
0519 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED \
0520     PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(3) /* RWI-V */
0521 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED \
0522     PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(3) /* RW--V */
0523
0524 /*
0525 3-Wire Audio Serial output Channel 0-3 Control Register
0526 Configures settings for 3-Wire Serial Audio Output Channel 0-3
0527
0528
0529  31            24 23           16 15            8 7             0
0530  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0531  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|0 0 0 0|A|0|ASO|0 0 0|0|0|0|0|0| AO_3WCTRL
0532  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0533
0534 */
0535 /*
0536 Data Bit Mode
0537 Specifies the number of data bits
0538 0 - 16 bits
0539 1 - reserved
0540 2 - 20 bits
0541 3 - 24 bits
0542 */
0543 #define PS3_AUDIO_AO_3WCTRL_ASODB_MASK  (0x3 << 8) /* RWIVF */
0544 #define PS3_AUDIO_AO_3WCTRL_ASODB_16BIT (0x0 << 8) /* RWI-V */
0545 #define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */
0546 #define PS3_AUDIO_AO_3WCTRL_ASODB_20BIT (0x2 << 8) /* RW--V */
0547 #define PS3_AUDIO_AO_3WCTRL_ASODB_24BIT (0x3 << 8) /* RW--V */
0548 /*
0549 Data Format Mode
0550 Specifies the data format where (LSB side or MSB) the data(in 20 bit
0551 or 24 bit resolution mode) is put in a 32 bit field.
0552 0 - Data put on LSB side
0553 1 - Data put on MSB side
0554 */
0555 #define PS3_AUDIO_AO_3WCTRL_ASODF   (1 << 11) /* RWIVF */
0556 #define PS3_AUDIO_AO_3WCTRL_ASODF_LSB   (0 << 11) /* RWI-V */
0557 #define PS3_AUDIO_AO_3WCTRL_ASODF_MSB   (1 << 11) /* RW--V */
0558 /*
0559 Buffer Reset
0560 Performs buffer reset.  Writing 1 to this bit initializes the
0561 corresponding 3-Wire Audio Output buffers(both L and R).
0562 */
0563 #define PS3_AUDIO_AO_3WCTRL_ASOBRST         (1 << 16) /* CWIVF */
0564 #define PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE    (0 << 16) /* -WI-V */
0565 #define PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET   (1 << 16) /* -W--T */
0566
0567 /*
0568 S/PDIF Audio Output Channel 0/1 Control Register
0569 Configures settings for S/PDIF Audio Output Channel 0/1.
0570
0571  31            24 23           16 15            8 7             0
0572  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0573  |S|0 0 0|S|0 0|S| SPOSR |0 0|SPO|0 0 0 0|S|0|SPO|0 0 0 0 0 0 0|S| AO_SPDCTRL
0574  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0575 */
0576 /*
0577 Buffer reset.  Writing 1 to this bit initializes the
0578 corresponding S/PDIF output buffer pointer.
0579 */
0580 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST        (1 << 0) /* CWIVF */
0581 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE   (0 << 0) /* -WI-V */
0582 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET  (1 << 0) /* -W--T */
0583
0584 /*
0585 Data Bit Mode
0586 Specifies number of data bits
0587 0 - 16 bits
0588 1 - Reserved
0589 2 - 20 bits
0590 3 - 24 bits
0591 */
0592 #define PS3_AUDIO_AO_SPDCTRL_SPODB_MASK     (0x3 << 8) /* RWIVF */
0593 #define PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT    (0x0 << 8) /* RWI-V */
0594 #define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD    (0x1 << 8) /* RW--V */
0595 #define PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT    (0x2 << 8) /* RW--V */
0596 #define PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT    (0x3 << 8) /* RW--V */
0597 /*
0598 Data format Mode
0599 Specifies the data format, where (LSB side or MSB)
0600 the data(in 20 or 24 bit resolution) is put in the
0601 32 bit field.
0602 0 - LSB Side
0603 1 - MSB Side
0604 */
0605 #define PS3_AUDIO_AO_SPDCTRL_SPODF  (1 << 11) /* RWIVF */
0606 #define PS3_AUDIO_AO_SPDCTRL_SPODF_LSB  (0 << 11) /* RWI-V */
0607 #define PS3_AUDIO_AO_SPDCTRL_SPODF_MSB  (1 << 11) /* RW--V */
0608 /*
0609 Source Select
0610 Specifies the source of the S/PDIF output.  When 0, output
0611 operation is controlled by 3wen[0] of AO_3WMCTRL register.
0612 The SR must have the same setting as the a0_3wmctrl reg.
0613 0 - 3-Wire Audio OUT Ch0 Buffer
0614 1 - S/PDIF buffer
0615 */
0616 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK     (0x3 << 16) /* RWIVF */
0617 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN     (0x0 << 16) /* RWI-V */
0618 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF    (0x1 << 16) /* RW--V */
0619 /*
0620 Sampling Rate
0621 Specifies the divide ratio of the bit clock (clock output
0622 from bclko) used by the S/PDIF Output Clock, which
0623 is applied to the master clock selected by mcksel.
0624 */
0625 #define PS3_AUDIO_AO_SPDCTRL_SPOSR      (0xf << 20) /* RWIVF */
0626 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2     (0x1 << 20) /* RWI-V */
0627 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4     (0x2 << 20) /* RW--V */
0628 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8     (0x4 << 20) /* RW--V */
0629 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12    (0x6 << 20) /* RW--V */
0630 /*
0631 Master Clock Select
0632 0 - Master Clock 0
0633 1 - Master Clock 1
0634 */
0635 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL      (1 << 24) /* RWIVF */
0636 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0 (0 << 24) /* RWI-V */
0637 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1 (1 << 24) /* RW--V */
0638
0639 /*
0640 S/PDIF Output Channel Operational Status
0641 This bit becomes 1 after S/PDIF Output Channel is in
0642 action by setting 1 to spoen.  This bit becomes 0
0643 after S/PDIF Output Channel is out of action by setting
0644 0 to spoen.
0645 */
0646 #define PS3_AUDIO_AO_SPDCTRL_SPORUN     (1 << 27) /* R-IVF */
0647 #define PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED (0 << 27) /* R-I-V */
0648 #define PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING (1 << 27) /* R---V */
0649
0650 /*
0651 S/PDIF Audio Output Channel Output Enable
0652 Enables and disables output operation.  This bit is used
0653 only when sposs = 1
0654 */
0655 #define PS3_AUDIO_AO_SPDCTRL_SPOEN      (1 << 31) /* RWIVF */
0656 #define PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED (0 << 31) /* RWI-V */
0657 #define PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED  (1 << 31) /* RW--V */
0658
0659 /*
0660 S/PDIF Audio Output Channel Channel Status
0661 Setting Registers.
0662 Configures channel status bit settings for each block
0663 (192 bits).
0664 Output is performed from the MSB(AO_SPDCS0 register bit 31).
0665 The same value is added for subframes within the same frame.
0666  31            24 23           16 15            8 7             0
0667  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0668  |                             SPOCS                             | AO_SPDCS
0669  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0670
0671 S/PDIF Audio Output Channel User Bit Setting
0672 Configures user bit settings for each block (384 bits).
0673 Output is performed from the MSB(ao_spdub0 register bit 31).
0674
0675
0676  31            24 23           16 15            8 7             0
0677  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0678  |                             SPOUB                             | AO_SPDUB
0679  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0680 */
0681 /*****************************************************************************
0682  *
0683  * DMAC register
0684  *
0685  *****************************************************************************/
0686 /*
0687 The PS3_AUDIO_KICK register is used to initiate a DMA transfer and monitor
0688 its status
0689
0690  31            24 23           16 15            8 7             0
0691  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0692  |0 0 0 0 0|STATU|0 0 0|  EVENT  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|R| KICK
0693  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0694 */
0695 /*
0696 The REQUEST field is written to ACTIVE to initiate a DMA request when EVENT
0697 occurs.
0698 It will return to the DONE state when the request is completed.
0699 The registers for a DMA channel should only be written if REQUEST is IDLE.
0700 */
0701
0702 #define PS3_AUDIO_KICK_REQUEST                (1 << 0) /* RWIVF */
0703 #define PS3_AUDIO_KICK_REQUEST_IDLE           (0 << 0) /* RWI-V */
0704 #define PS3_AUDIO_KICK_REQUEST_ACTIVE         (1 << 0) /* -W--T */
0705
0706 /*
0707  *The EVENT field is used to set the event in which
0708  *the DMA request becomes active.
0709  */
0710 #define PS3_AUDIO_KICK_EVENT_MASK             (0x1f << 16) /* RWIVF */
0711 #define PS3_AUDIO_KICK_EVENT_ALWAYS           (0x00 << 16) /* RWI-V */
0712 #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY (0x01 << 16) /* RW--V */
0713 #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW   (0x02 << 16) /* RW--V */
0714 #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY       (0x03 << 16) /* RW--V */
0715 #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW   (0x04 << 16) /* RW--V */
0716 #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY       (0x05 << 16) /* RW--V */
0717 #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW   (0x06 << 16) /* RW--V */
0718 #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY       (0x07 << 16) /* RW--V */
0719 #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW   (0x08 << 16) /* RW--V */
0720 #define PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE \
0721     (0x09 << 16) /* RW--V */
0722 #define PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW       (0x0A << 16) /* RW--V */
0723 #define PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY       (0x0B << 16) /* RW--V */
0724 #define PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE \
0725     (0x0C << 16) /* RW--V */
0726 #define PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW       (0x0D << 16) /* RW--V */
0727 #define PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY       (0x0E << 16) /* RW--V */
0728
0729 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA(n) \
0730     ((0x13 + (n)) << 16) /* RW--V */
0731 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA0         (0x13 << 16) /* RW--V */
0732 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA1         (0x14 << 16) /* RW--V */
0733 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA2         (0x15 << 16) /* RW--V */
0734 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA3         (0x16 << 16) /* RW--V */
0735 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA4         (0x17 << 16) /* RW--V */
0736 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA5         (0x18 << 16) /* RW--V */
0737 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA6         (0x19 << 16) /* RW--V */
0738 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA7         (0x1A << 16) /* RW--V */
0739 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA8         (0x1B << 16) /* RW--V */
0740 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA9         (0x1C << 16) /* RW--V */
0741
0742 /*
0743 The STATUS field can be used to monitor the progress of a DMA request.
0744 DONE indicates the previous request has completed.
0745 EVENT indicates that the DMA engine is waiting for the EVENT to occur.
0746 PENDING indicates that the DMA engine has not started processing this
0747 request, but the EVENT has occurred.
0748 DMA indicates that the data transfer is in progress.
0749 NOTIFY indicates that the notifier signalling end of transfer is being written.
0750 CLEAR indicated that the previous transfer was cleared.
0751 ERROR indicates the previous transfer requested an unsupported
0752 source/destination combination.
0753 */
0754
0755 #define PS3_AUDIO_KICK_STATUS_MASK  (0x7 << 24) /* R-IVF */
0756 #define PS3_AUDIO_KICK_STATUS_DONE  (0x0 << 24) /* R-I-V */
0757 #define PS3_AUDIO_KICK_STATUS_EVENT (0x1 << 24) /* R---V */
0758 #define PS3_AUDIO_KICK_STATUS_PENDING   (0x2 << 24) /* R---V */
0759 #define PS3_AUDIO_KICK_STATUS_DMA   (0x3 << 24) /* R---V */
0760 #define PS3_AUDIO_KICK_STATUS_NOTIFY    (0x4 << 24) /* R---V */
0761 #define PS3_AUDIO_KICK_STATUS_CLEAR (0x5 << 24) /* R---V */
0762 #define PS3_AUDIO_KICK_STATUS_ERROR (0x6 << 24) /* R---V */
0763
0764 /*
0765 The PS3_AUDIO_SOURCE register specifies the source address for transfers.
0766
0767
0768  31            24 23           16 15            8 7             0
0769  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0770  |                      START                      |0 0 0 0 0|TAR| SOURCE
0771  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0772 */
0773
0774 /*
0775 The Audio DMA engine uses 128-byte transfers, thus the address must be aligned
0776 to a 128 byte boundary.  The low seven bits are assumed to be 0.
0777 */
0778
0779 #define PS3_AUDIO_SOURCE_START_MASK (0x01FFFFFF << 7) /* RWIUF */
0780
0781 /*
0782 The TARGET field specifies the memory space containing the source address.
0783 */
0784
0785 #define PS3_AUDIO_SOURCE_TARGET_MASK        (3 << 0) /* RWIVF */
0786 #define PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY   (2 << 0) /* RW--V */
0787
0788 /*
0789 The PS3_AUDIO_DEST register specifies the destination address for transfers.
0790
0791
0792  31            24 23           16 15            8 7             0
0793  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0794  |                      START                      |0 0 0 0 0|TAR| DEST
0795  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0796 */
0797
0798 /*
0799 The Audio DMA engine uses 128-byte transfers, thus the address must be aligned
0800 to a 128 byte boundary.  The low seven bits are assumed to be 0.
0801 */
0802
0803 #define PS3_AUDIO_DEST_START_MASK   (0x01FFFFFF << 7) /* RWIUF */
0804
0805 /*
0806 The TARGET field specifies the memory space containing the destination address
0807 AUDIOFIFO = Audio WriteData FIFO,
0808 */
0809
0810 #define PS3_AUDIO_DEST_TARGET_MASK      (3 << 0) /* RWIVF */
0811 #define PS3_AUDIO_DEST_TARGET_AUDIOFIFO     (1 << 0) /* RW--V */
0812
0813 /*
0814 PS3_AUDIO_DMASIZE specifies the number of 128-byte blocks + 1 to transfer.
0815 So a value of 0 means 128-bytes will get transferred.
0816
0817
0818  31            24 23           16 15            8 7             0
0819  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0820  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|   BLOCKS    | DMASIZE
0821  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
0822 */
0823
0824
0825 #define PS3_AUDIO_DMASIZE_BLOCKS_MASK   (0x7f << 0) /* RWIUF */
0826
0827 /*
0828  * source/destination address for internal fifos
0829  */
0830 #define PS3_AUDIO_AO_3W_LDATA(n)    (0x1000 + (0x100 * (n)))
0831 #define PS3_AUDIO_AO_3W_RDATA(n)    (0x1080 + (0x100 * (n)))
0832
0833 #define PS3_AUDIO_AO_SPD_DATA(n)    (0x2000 + (0x400 * (n)))
0834
0835
0836 /*
0837  * field attiribute
0838  *
0839  *  Read
0840  *    ' ' = Other Information
0841  *    '-' = Field is part of a write-only register
0842  *    'C' = Value read is always the same, constant value line follows (C)
0843  *    'R' = Value is read
0844  *
0845  *  Write
0846  *    ' ' = Other Information
0847  *    '-' = Must not be written (D), value ignored when written (R,A,F)
0848  *    'W' = Can be written
0849  *
0850  *  Internal State
0851  *    ' ' = Other Information
0852  *    '-' = No internal state
0853  *    'X' = Internal state, initial value is unknown
0854  *    'I' = Internal state, initial value is known and follows (I)
0855  *
0856  *  Declaration/Size
0857  *    ' ' = Other Information
0858  *    '-' = Does Not Apply
0859  *    'V' = Type is void
0860  *    'U' = Type is unsigned integer
0861  *    'S' = Type is signed integer
0862  *    'F' = Type is IEEE floating point
0863  *    '1' = Byte size (008)
0864  *    '2' = Short size (016)
0865  *    '3' = Three byte size (024)
0866  *    '4' = Word size (032)
0867  *    '8' = Double size (064)
0868  *
0869  *  Define Indicator
0870  *    ' ' = Other Information
0871  *    'D' = Device
0872  *    'M' = Memory
0873  *    'R' = Register
0874  *    'A' = Array of Registers
0875  *    'F' = Field
0876  *    'V' = Value
0877  *    'T' = Task
0878  */
0879