sound/ppc/awacs.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Driver for PowerMac AWACS onboard soundchips
0004  * Copyright (c) 2001 by Takashi Iwai <tiwai@suse.de>
0005  *   based on dmasound.c.
0006  */
0007
0008
0009 #ifndef __AWACS_H
0010 #define __AWACS_H
0011
0012 /*******************************/
0013 /* AWACs Audio Register Layout */
0014 /*******************************/
0015
0016 struct awacs_regs {
0017     unsigned    control;    /* Audio control register */
0018     unsigned    pad0[3];
0019     unsigned    codec_ctrl; /* Codec control register */
0020     unsigned    pad1[3];
0021     unsigned    codec_stat; /* Codec status register */
0022     unsigned    pad2[3];
0023     unsigned    clip_count; /* Clipping count register */
0024     unsigned    pad3[3];
0025     unsigned    byteswap;   /* Data is little-endian if 1 */
0026 };
0027
0028 /*******************/
0029 /* Audio Bit Masks */
0030 /*******************/
0031
0032 /* Audio Control Reg Bit Masks */
0033 /* ----- ------- --- --- ----- */
0034 #define MASK_ISFSEL (0xf)       /* Input SubFrame Select */
0035 #define MASK_OSFSEL (0xf << 4)  /* Output SubFrame Select */
0036 #define MASK_RATE   (0x7 << 8)  /* Sound Rate */
0037 #define MASK_CNTLERR    (0x1 << 11) /* Error */
0038 #define MASK_PORTCHG    (0x1 << 12) /* Port Change */
0039 #define MASK_IEE    (0x1 << 13) /* Enable Interrupt on Error */
0040 #define MASK_IEPC   (0x1 << 14) /* Enable Interrupt on Port Change */
0041 #define MASK_SSFSEL (0x3 << 15) /* Status SubFrame Select */
0042
0043 /* Audio Codec Control Reg Bit Masks */
0044 /* ----- ----- ------- --- --- ----- */
0045 #define MASK_NEWECMD    (0x1 << 24) /* Lock: don't write to reg when 1 */
0046 #define MASK_EMODESEL   (0x3 << 22) /* Send info out on which frame? */
0047 #define MASK_EXMODEADDR (0x3ff << 12)   /* Extended Mode Address -- 10 bits */
0048 #define MASK_EXMODEDATA (0xfff)     /* Extended Mode Data -- 12 bits */
0049
0050 /* Audio Codec Control Address Values / Masks */
0051 /* ----- ----- ------- ------- ------ - ----- */
0052 #define MASK_ADDR0  (0x0 << 12) /* Expanded Data Mode Address 0 */
0053 #define MASK_ADDR_MUX   MASK_ADDR0  /* Mux Control */
0054 #define MASK_ADDR_GAIN  MASK_ADDR0
0055
0056 #define MASK_ADDR1  (0x1 << 12) /* Expanded Data Mode Address 1 */
0057 #define MASK_ADDR_MUTE  MASK_ADDR1
0058 #define MASK_ADDR_RATE  MASK_ADDR1
0059
0060 #define MASK_ADDR2  (0x2 << 12) /* Expanded Data Mode Address 2 */
0061 #define MASK_ADDR_VOLA  MASK_ADDR2  /* Volume Control A -- Headphones */
0062 #define MASK_ADDR_VOLHD MASK_ADDR2
0063
0064 #define MASK_ADDR4  (0x4 << 12) /* Expanded Data Mode Address 4 */
0065 #define MASK_ADDR_VOLC  MASK_ADDR4  /* Volume Control C -- Speaker */
0066 #define MASK_ADDR_VOLSPK MASK_ADDR4
0067
0068 /* additional registers of screamer */
0069 #define MASK_ADDR5  (0x5 << 12) /* Expanded Data Mode Address 5 */
0070 #define MASK_ADDR6  (0x6 << 12) /* Expanded Data Mode Address 6 */
0071 #define MASK_ADDR7  (0x7 << 12) /* Expanded Data Mode Address 7 */
0072
0073 /* Address 0 Bit Masks & Macros */
0074 /* ------- - --- ----- - ------ */
0075 #define MASK_GAINRIGHT  (0xf)       /* Gain Right Mask */
0076 #define MASK_GAINLEFT   (0xf << 4)  /* Gain Left Mask */
0077 #define MASK_GAINLINE   (0x1 << 8)  /* Disable Mic preamp */
0078 #define MASK_GAINMIC    (0x0 << 8)  /* Enable Mic preamp */
0079 #define MASK_MUX_CD (0x1 << 9)  /* Select CD in MUX */
0080 #define MASK_MUX_MIC    (0x1 << 10) /* Select Mic in MUX */
0081 #define MASK_MUX_AUDIN  (0x1 << 11) /* Select Audio In in MUX */
0082 #define MASK_MUX_LINE   MASK_MUX_AUDIN
0083 #define SHIFT_GAINLINE  8
0084 #define SHIFT_MUX_CD    9
0085 #define SHIFT_MUX_MIC   10
0086 #define SHIFT_MUX_LINE  11
0087
0088 #define GAINRIGHT(x)    ((x) & MASK_GAINRIGHT)
0089 #define GAINLEFT(x) (((x) << 4) & MASK_GAINLEFT)
0090
0091 /* Address 1 Bit Masks */
0092 /* ------- - --- ----- */
0093 #define MASK_ADDR1RES1  (0x3)       /* Reserved */
0094 #define MASK_RECALIBRATE (0x1 << 2) /* Recalibrate */
0095 #define MASK_SAMPLERATE (0x7 << 3)  /* Sample Rate: */
0096 #define MASK_LOOPTHRU   (0x1 << 6)  /* Loopthrough Enable */
0097 #define SHIFT_LOOPTHRU  6
0098 #define MASK_CMUTE  (0x1 << 7)  /* Output C (Speaker) Mute when 1 */
0099 #define MASK_SPKMUTE    MASK_CMUTE
0100 #define SHIFT_SPKMUTE   7
0101 #define MASK_ADDR1RES2  (0x1 << 8)  /* Reserved */
0102 #define MASK_AMUTE  (0x1 << 9)  /* Output A (Headphone) Mute when 1 */
0103 #define MASK_HDMUTE MASK_AMUTE
0104 #define SHIFT_HDMUTE    9
0105 #define MASK_PAROUT (0x3 << 10) /* Parallel Out (???) */
0106 #define MASK_PAROUT0    (0x1 << 10) /* Parallel Out (???) */
0107 #define MASK_PAROUT1    (0x1 << 11) /* Parallel Out (enable speaker) */
0108 #define SHIFT_PAROUT    10
0109 #define SHIFT_PAROUT0   10
0110 #define SHIFT_PAROUT1   11
0111
0112 #define SAMPLERATE_48000    (0x0 << 3)  /* 48 or 44.1 kHz */
0113 #define SAMPLERATE_32000    (0x1 << 3)  /* 32 or 29.4 kHz */
0114 #define SAMPLERATE_24000    (0x2 << 3)  /* 24 or 22.05 kHz */
0115 #define SAMPLERATE_19200    (0x3 << 3)  /* 19.2 or 17.64 kHz */
0116 #define SAMPLERATE_16000    (0x4 << 3)  /* 16 or 14.7 kHz */
0117 #define SAMPLERATE_12000    (0x5 << 3)  /* 12 or 11.025 kHz */
0118 #define SAMPLERATE_9600     (0x6 << 3)  /* 9.6 or 8.82 kHz */
0119 #define SAMPLERATE_8000     (0x7 << 3)  /* 8 or 7.35 kHz */
0120
0121 /* Address 2 & 4 Bit Masks & Macros */
0122 /* ------- - - - --- ----- - ------ */
0123 #define MASK_OUTVOLRIGHT (0xf)      /* Output Right Volume */
0124 #define MASK_ADDR2RES1  (0x2 << 4)  /* Reserved */
0125 #define MASK_ADDR4RES1  MASK_ADDR2RES1
0126 #define MASK_OUTVOLLEFT (0xf << 6)  /* Output Left Volume */
0127 #define MASK_ADDR2RES2  (0x2 << 10) /* Reserved */
0128 #define MASK_ADDR4RES2  MASK_ADDR2RES2
0129
0130 #define VOLRIGHT(x) (((~(x)) & MASK_OUTVOLRIGHT))
0131 #define VOLLEFT(x)  (((~(x)) << 6) & MASK_OUTVOLLEFT)
0132
0133 /* address 6 */
0134 #define MASK_MIC_BOOST  (0x4)       /* screamer mic boost */
0135 #define SHIFT_MIC_BOOST 2
0136
0137 /* Audio Codec Status Reg Bit Masks */
0138 /* ----- ----- ------ --- --- ----- */
0139 #define MASK_EXTEND (0x1 << 23) /* Extend */
0140 #define MASK_VALID  (0x1 << 22) /* Valid Data? */
0141 #define MASK_OFLEFT (0x1 << 21) /* Overflow Left */
0142 #define MASK_OFRIGHT    (0x1 << 20) /* Overflow Right */
0143 #define MASK_ERRCODE    (0xf << 16) /* Error Code */
0144 #define MASK_REVISION   (0xf << 12) /* Revision Number */
0145 #define MASK_MFGID  (0xf << 8)  /* Mfg. ID */
0146 #define MASK_CODSTATRES (0xf << 4)  /* bits 4 - 7 reserved */
0147 #define MASK_INSENSE    (0xf)       /* port sense bits: */
0148 #define MASK_HDPCONN        8   /* headphone plugged in */
0149 #define MASK_LOCONN     4   /* line-out plugged in */
0150 #define MASK_LICONN     2   /* line-in plugged in */
0151 #define MASK_MICCONN        1   /* microphone plugged in */
0152 #define MASK_LICONN_IMAC    8   /* line-in plugged in */
0153 #define MASK_HDPRCONN_IMAC  4   /* headphone right plugged in */
0154 #define MASK_HDPLCONN_IMAC  2   /* headphone left plugged in */
0155 #define MASK_LOCONN_IMAC    1   /* line-out plugged in */
0156
0157 /* Clipping Count Reg Bit Masks */
0158 /* -------- ----- --- --- ----- */
0159 #define MASK_CLIPLEFT   (0xff << 7) /* Clipping Count, Left Channel */
0160 #define MASK_CLIPRIGHT  (0xff)      /* Clipping Count, Right Channel */
0161
0162 /* DBDMA ChannelStatus Bit Masks */
0163 /* ----- ------------- --- ----- */
0164 #define MASK_CSERR  (0x1 << 7)  /* Error */
0165 #define MASK_EOI    (0x1 << 6)  /* End of Input --
0166                        only for Input Channel */
0167 #define MASK_CSUNUSED   (0x1f << 1) /* bits 1-5 not used */
0168 #define MASK_WAIT   (0x1)       /* Wait */
0169
0170 /* Various Rates */
0171 /* ------- ----- */
0172 #define RATE_48000  (0x0 << 8)  /* 48 kHz */
0173 #define RATE_44100  (0x0 << 8)  /* 44.1 kHz */
0174 #define RATE_32000  (0x1 << 8)  /* 32 kHz */
0175 #define RATE_29400  (0x1 << 8)  /* 29.4 kHz */
0176 #define RATE_24000  (0x2 << 8)  /* 24 kHz */
0177 #define RATE_22050  (0x2 << 8)  /* 22.05 kHz */
0178 #define RATE_19200  (0x3 << 8)  /* 19.2 kHz */
0179 #define RATE_17640  (0x3 << 8)  /* 17.64 kHz */
0180 #define RATE_16000  (0x4 << 8)  /* 16 kHz */
0181 #define RATE_14700  (0x4 << 8)  /* 14.7 kHz */
0182 #define RATE_12000  (0x5 << 8)  /* 12 kHz */
0183 #define RATE_11025  (0x5 << 8)  /* 11.025 kHz */
0184 #define RATE_9600   (0x6 << 8)  /* 9.6 kHz */
0185 #define RATE_8820   (0x6 << 8)  /* 8.82 kHz */
0186 #define RATE_8000   (0x7 << 8)  /* 8 kHz */
0187 #define RATE_7350   (0x7 << 8)  /* 7.35 kHz */
0188
0189 #define RATE_LOW    1   /* HIGH = 48kHz, etc;  LOW = 44.1kHz, etc. */
0190
0191
0192 #endif /* __AWACS_H */