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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Digigram VXpocket soundcards
0004  *
0005  * lowlevel routines for VXpocket soundcards
0006  *
0007  * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/firmware.h>
0013 #include <linux/io.h>
0014 #include <sound/core.h>
0015 #include "vxpocket.h"
0016 
0017 
0018 static const int vxp_reg_offset[VX_REG_MAX] = {
0019     [VX_ICR]    = 0x00,     // ICR
0020     [VX_CVR]    = 0x01,     // CVR
0021     [VX_ISR]    = 0x02,     // ISR
0022     [VX_IVR]    = 0x03,     // IVR
0023     [VX_RXH]    = 0x05,     // RXH
0024     [VX_RXM]    = 0x06,     // RXM
0025     [VX_RXL]    = 0x07,     // RXL
0026     [VX_DMA]    = 0x04,     // DMA
0027     [VX_CDSP]   = 0x08,     // CDSP
0028     [VX_LOFREQ] = 0x09,     // LFREQ
0029     [VX_HIFREQ] = 0x0a,     // HFREQ
0030     [VX_DATA]   = 0x0b,     // DATA
0031     [VX_MICRO]  = 0x0c,     // MICRO
0032     [VX_DIALOG] = 0x0d,     // DIALOG
0033     [VX_CSUER]  = 0x0e,     // CSUER
0034     [VX_RUER]   = 0x0f,     // RUER
0035 };
0036 
0037 
0038 static inline unsigned long vxp_reg_addr(struct vx_core *_chip, int reg)
0039 {
0040     struct snd_vxpocket *chip = to_vxpocket(_chip);
0041     return chip->port + vxp_reg_offset[reg];
0042 }
0043 
0044 /*
0045  * snd_vx_inb - read a byte from the register
0046  * @offset: register offset
0047  */
0048 static unsigned char vxp_inb(struct vx_core *chip, int offset)
0049 {
0050     return inb(vxp_reg_addr(chip, offset));
0051 }
0052 
0053 /*
0054  * snd_vx_outb - write a byte on the register
0055  * @offset: the register offset
0056  * @val: the value to write
0057  */
0058 static void vxp_outb(struct vx_core *chip, int offset, unsigned char val)
0059 {
0060     outb(val, vxp_reg_addr(chip, offset));
0061 }
0062 
0063 /*
0064  * redefine macros to call directly
0065  */
0066 #undef vx_inb
0067 #define vx_inb(chip,reg)    vxp_inb((struct vx_core *)(chip), VX_##reg)
0068 #undef vx_outb
0069 #define vx_outb(chip,reg,val)   vxp_outb((struct vx_core *)(chip), VX_##reg,val)
0070 
0071 
0072 /*
0073  * vx_check_magic - check the magic word on xilinx
0074  *
0075  * returns zero if a magic word is detected, or a negative error code.
0076  */
0077 static int vx_check_magic(struct vx_core *chip)
0078 {
0079     unsigned long end_time = jiffies + HZ / 5;
0080     int c;
0081     do {
0082         c = vx_inb(chip, CDSP);
0083         if (c == CDSP_MAGIC)
0084             return 0;
0085         msleep(10);
0086     } while (time_after_eq(end_time, jiffies));
0087     snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c);
0088     return -EIO;
0089 }
0090 
0091 
0092 /*
0093  * vx_reset_dsp - reset the DSP
0094  */
0095 
0096 #define XX_DSP_RESET_WAIT_TIME      2   /* ms */
0097 
0098 static void vxp_reset_dsp(struct vx_core *_chip)
0099 {
0100     struct snd_vxpocket *chip = to_vxpocket(_chip);
0101 
0102     /* set the reset dsp bit to 1 */
0103     vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_DSP_RESET_MASK);
0104     vx_inb(chip, CDSP);
0105     mdelay(XX_DSP_RESET_WAIT_TIME);
0106     /* reset the bit */
0107     chip->regCDSP &= ~VXP_CDSP_DSP_RESET_MASK;
0108     vx_outb(chip, CDSP, chip->regCDSP);
0109     vx_inb(chip, CDSP);
0110     mdelay(XX_DSP_RESET_WAIT_TIME);
0111 }
0112 
0113 /*
0114  * reset codec bit
0115  */
0116 static void vxp_reset_codec(struct vx_core *_chip)
0117 {
0118     struct snd_vxpocket *chip = to_vxpocket(_chip);
0119 
0120     /* Set the reset CODEC bit to 1. */
0121     vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
0122     vx_inb(chip, CDSP);
0123     msleep(10);
0124     /* Set the reset CODEC bit to 0. */
0125     chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
0126     vx_outb(chip, CDSP, chip->regCDSP);
0127     vx_inb(chip, CDSP);
0128     msleep(1);
0129 }
0130 
0131 /*
0132  * vx_load_xilinx_binary - load the xilinx binary image
0133  * the binary image is the binary array converted from the bitstream file.
0134  */
0135 static int vxp_load_xilinx_binary(struct vx_core *_chip, const struct firmware *fw)
0136 {
0137     struct snd_vxpocket *chip = to_vxpocket(_chip);
0138     unsigned int i;
0139     int c;
0140     int regCSUER, regRUER;
0141     const unsigned char *image;
0142     unsigned char data;
0143 
0144     /* Switch to programmation mode */
0145     chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
0146     vx_outb(chip, DIALOG, chip->regDIALOG);
0147 
0148     /* Save register CSUER and RUER */
0149     regCSUER = vx_inb(chip, CSUER);
0150     regRUER = vx_inb(chip, RUER);
0151 
0152     /* reset HF0 and HF1 */
0153     vx_outb(chip, ICR, 0);
0154 
0155     /* Wait for answer HF2 equal to 1 */
0156     snd_printdd(KERN_DEBUG "check ISR_HF2\n");
0157     if (vx_check_isr(_chip, ISR_HF2, ISR_HF2, 20) < 0)
0158         goto _error;
0159 
0160     /* set HF1 for loading xilinx binary */
0161     vx_outb(chip, ICR, ICR_HF1);
0162     image = fw->data;
0163     for (i = 0; i < fw->size; i++, image++) {
0164         data = *image;
0165         if (vx_wait_isr_bit(_chip, ISR_TX_EMPTY) < 0)
0166             goto _error;
0167         vx_outb(chip, TXL, data);
0168         /* wait for reading */
0169         if (vx_wait_for_rx_full(_chip) < 0)
0170             goto _error;
0171         c = vx_inb(chip, RXL);
0172         if (c != (int)data)
0173             snd_printk(KERN_ERR "vxpocket: load xilinx mismatch at %d: 0x%x != 0x%x\n", i, c, (int)data);
0174         }
0175 
0176     /* reset HF1 */
0177     vx_outb(chip, ICR, 0);
0178 
0179     /* wait for HF3 */
0180     if (vx_check_isr(_chip, ISR_HF3, ISR_HF3, 20) < 0)
0181         goto _error;
0182 
0183     /* read the number of bytes received */
0184     if (vx_wait_for_rx_full(_chip) < 0)
0185         goto _error;
0186 
0187     c = (int)vx_inb(chip, RXH) << 16;
0188     c |= (int)vx_inb(chip, RXM) << 8;
0189     c |= vx_inb(chip, RXL);
0190 
0191     snd_printdd(KERN_DEBUG "xilinx: dsp size received 0x%x, orig 0x%zx\n", c, fw->size);
0192 
0193     vx_outb(chip, ICR, ICR_HF0);
0194 
0195     /* TEMPO 250ms : wait until Xilinx is downloaded */
0196     msleep(300);
0197 
0198     /* test magical word */
0199     if (vx_check_magic(_chip) < 0)
0200         goto _error;
0201 
0202     /* Restore register 0x0E and 0x0F (thus replacing COR and FCSR) */
0203     vx_outb(chip, CSUER, regCSUER);
0204     vx_outb(chip, RUER, regRUER);
0205 
0206     /* Reset the Xilinx's signal enabling IO access */
0207     chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
0208     vx_outb(chip, DIALOG, chip->regDIALOG);
0209     vx_inb(chip, DIALOG);
0210     msleep(10);
0211     chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
0212     vx_outb(chip, DIALOG, chip->regDIALOG);
0213     vx_inb(chip, DIALOG);
0214 
0215     /* Reset of the Codec */
0216     vxp_reset_codec(_chip);
0217     vx_reset_dsp(_chip);
0218 
0219     return 0;
0220 
0221  _error:
0222     vx_outb(chip, CSUER, regCSUER);
0223     vx_outb(chip, RUER, regRUER);
0224     chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
0225     vx_outb(chip, DIALOG, chip->regDIALOG);
0226     return -EIO;
0227 }
0228 
0229 
0230 /*
0231  * vxp_load_dsp - load_dsp callback
0232  */
0233 static int vxp_load_dsp(struct vx_core *vx, int index, const struct firmware *fw)
0234 {
0235     int err;
0236 
0237     switch (index) {
0238     case 0:
0239         /* xilinx boot */
0240         err = vx_check_magic(vx);
0241         if (err < 0)
0242             return err;
0243         err = snd_vx_load_boot_image(vx, fw);
0244         if (err < 0)
0245             return err;
0246         return 0;
0247     case 1:
0248         /* xilinx image */
0249         return vxp_load_xilinx_binary(vx, fw);
0250     case 2:
0251         /* DSP boot */
0252         return snd_vx_dsp_boot(vx, fw);
0253     case 3:
0254         /* DSP image */
0255         return snd_vx_dsp_load(vx, fw);
0256     default:
0257         snd_BUG();
0258         return -EINVAL;
0259     }
0260 }
0261         
0262 
0263 /*
0264  * vx_test_and_ack - test and acknowledge interrupt
0265  *
0266  * called from irq hander, too
0267  *
0268  * spinlock held!
0269  */
0270 static int vxp_test_and_ack(struct vx_core *_chip)
0271 {
0272     struct snd_vxpocket *chip = to_vxpocket(_chip);
0273 
0274     /* not booted yet? */
0275     if (! (_chip->chip_status & VX_STAT_XILINX_LOADED))
0276         return -ENXIO;
0277 
0278     if (! (vx_inb(chip, DIALOG) & VXP_DLG_MEMIRQ_MASK))
0279         return -EIO;
0280     
0281     /* ok, interrupts generated, now ack it */
0282     /* set ACQUIT bit up and down */
0283     vx_outb(chip, DIALOG, chip->regDIALOG | VXP_DLG_ACK_MEMIRQ_MASK);
0284     /* useless read just to spend some time and maintain
0285      * the ACQUIT signal up for a while ( a bus cycle )
0286      */
0287     vx_inb(chip, DIALOG);
0288     vx_outb(chip, DIALOG, chip->regDIALOG & ~VXP_DLG_ACK_MEMIRQ_MASK);
0289 
0290     return 0;
0291 }
0292 
0293 
0294 /*
0295  * vx_validate_irq - enable/disable IRQ
0296  */
0297 static void vxp_validate_irq(struct vx_core *_chip, int enable)
0298 {
0299     struct snd_vxpocket *chip = to_vxpocket(_chip);
0300 
0301     /* Set the interrupt enable bit to 1 in CDSP register */
0302     if (enable)
0303         chip->regCDSP |= VXP_CDSP_VALID_IRQ_MASK;
0304     else
0305         chip->regCDSP &= ~VXP_CDSP_VALID_IRQ_MASK;
0306     vx_outb(chip, CDSP, chip->regCDSP);
0307 }
0308 
0309 /*
0310  * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
0311  * @do_write: 0 = read, 1 = set up for DMA write
0312  */
0313 static void vx_setup_pseudo_dma(struct vx_core *_chip, int do_write)
0314 {
0315     struct snd_vxpocket *chip = to_vxpocket(_chip);
0316 
0317     /* Interrupt mode and HREQ pin enabled for host transmit / receive data transfers */
0318     vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
0319     /* Reset the pseudo-dma register */
0320     vx_inb(chip, ISR);
0321     vx_outb(chip, ISR, 0);
0322 
0323     /* Select DMA in read/write transfer mode and in 16-bit accesses */
0324     chip->regDIALOG |= VXP_DLG_DMA16_SEL_MASK;
0325     chip->regDIALOG |= do_write ? VXP_DLG_DMAWRITE_SEL_MASK : VXP_DLG_DMAREAD_SEL_MASK;
0326     vx_outb(chip, DIALOG, chip->regDIALOG);
0327 
0328 }
0329 
0330 /*
0331  * vx_release_pseudo_dma - disable the pseudo-DMA mode
0332  */
0333 static void vx_release_pseudo_dma(struct vx_core *_chip)
0334 {
0335     struct snd_vxpocket *chip = to_vxpocket(_chip);
0336 
0337     /* Disable DMA and 16-bit accesses */
0338     chip->regDIALOG &= ~(VXP_DLG_DMAWRITE_SEL_MASK|
0339                  VXP_DLG_DMAREAD_SEL_MASK|
0340                  VXP_DLG_DMA16_SEL_MASK);
0341     vx_outb(chip, DIALOG, chip->regDIALOG);
0342     /* HREQ pin disabled. */
0343     vx_outb(chip, ICR, 0);
0344 }
0345 
0346 /*
0347  * vx_pseudo_dma_write - write bulk data on pseudo-DMA mode
0348  * @count: data length to transfer in bytes
0349  *
0350  * data size must be aligned to 6 bytes to ensure the 24bit alignment on DSP.
0351  * NB: call with a certain lock!
0352  */
0353 static void vxp_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0354               struct vx_pipe *pipe, int count)
0355 {
0356     long port = vxp_reg_addr(chip, VX_DMA);
0357     int offset = pipe->hw_ptr;
0358     unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
0359 
0360     vx_setup_pseudo_dma(chip, 1);
0361     if (offset + count >= pipe->buffer_bytes) {
0362         int length = pipe->buffer_bytes - offset;
0363         count -= length;
0364         length >>= 1; /* in 16bit words */
0365         /* Transfer using pseudo-dma. */
0366         for (; length > 0; length--) {
0367             outw(*addr, port);
0368             addr++;
0369         }
0370         addr = (unsigned short *)runtime->dma_area;
0371         pipe->hw_ptr = 0;
0372     }
0373     pipe->hw_ptr += count;
0374     count >>= 1; /* in 16bit words */
0375     /* Transfer using pseudo-dma. */
0376     for (; count > 0; count--) {
0377         outw(*addr, port);
0378         addr++;
0379     }
0380     vx_release_pseudo_dma(chip);
0381 }
0382 
0383 
0384 /*
0385  * vx_pseudo_dma_read - read bulk data on pseudo DMA mode
0386  * @offset: buffer offset in bytes
0387  * @count: data length to transfer in bytes
0388  *
0389  * the read length must be aligned to 6 bytes, as well as write.
0390  * NB: call with a certain lock!
0391  */
0392 static void vxp_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0393              struct vx_pipe *pipe, int count)
0394 {
0395     struct snd_vxpocket *pchip = to_vxpocket(chip);
0396     long port = vxp_reg_addr(chip, VX_DMA);
0397     int offset = pipe->hw_ptr;
0398     unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
0399 
0400     if (snd_BUG_ON(count % 2))
0401         return;
0402     vx_setup_pseudo_dma(chip, 0);
0403     if (offset + count >= pipe->buffer_bytes) {
0404         int length = pipe->buffer_bytes - offset;
0405         count -= length;
0406         length >>= 1; /* in 16bit words */
0407         /* Transfer using pseudo-dma. */
0408         for (; length > 0; length--)
0409             *addr++ = inw(port);
0410         addr = (unsigned short *)runtime->dma_area;
0411         pipe->hw_ptr = 0;
0412     }
0413     pipe->hw_ptr += count;
0414     count >>= 1; /* in 16bit words */
0415     /* Transfer using pseudo-dma. */
0416     for (; count > 1; count--)
0417         *addr++ = inw(port);
0418     /* Disable DMA */
0419     pchip->regDIALOG &= ~VXP_DLG_DMAREAD_SEL_MASK;
0420     vx_outb(chip, DIALOG, pchip->regDIALOG);
0421     /* Read the last word (16 bits) */
0422     *addr = inw(port);
0423     /* Disable 16-bit accesses */
0424     pchip->regDIALOG &= ~VXP_DLG_DMA16_SEL_MASK;
0425     vx_outb(chip, DIALOG, pchip->regDIALOG);
0426     /* HREQ pin disabled. */
0427     vx_outb(chip, ICR, 0);
0428 }
0429 
0430 
0431 /*
0432  * write a codec data (24bit)
0433  */
0434 static void vxp_write_codec_reg(struct vx_core *chip, int codec, unsigned int data)
0435 {
0436     int i;
0437 
0438     /* Activate access to the corresponding codec register */
0439     if (! codec)
0440         vx_inb(chip, LOFREQ);
0441     else
0442         vx_inb(chip, CODEC2);
0443         
0444     /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
0445     for (i = 0; i < 24; i++, data <<= 1)
0446         vx_outb(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
0447     
0448     /* Terminate access to codec registers */
0449     vx_inb(chip, HIFREQ);
0450 }
0451 
0452 
0453 /*
0454  * vx_set_mic_boost - set mic boost level (on vxp440 only)
0455  * @boost: 0 = 20dB, 1 = +38dB
0456  */
0457 void vx_set_mic_boost(struct vx_core *chip, int boost)
0458 {
0459     struct snd_vxpocket *pchip = to_vxpocket(chip);
0460 
0461     if (chip->chip_status & VX_STAT_IS_STALE)
0462         return;
0463 
0464     mutex_lock(&chip->lock);
0465     if (pchip->regCDSP & P24_CDSP_MICS_SEL_MASK) {
0466         if (boost) {
0467             /* boost: 38 dB */
0468             pchip->regCDSP &= ~P24_CDSP_MIC20_SEL_MASK;
0469             pchip->regCDSP |=  P24_CDSP_MIC38_SEL_MASK;
0470         } else {
0471             /* minimum value: 20 dB */
0472             pchip->regCDSP |=  P24_CDSP_MIC20_SEL_MASK;
0473             pchip->regCDSP &= ~P24_CDSP_MIC38_SEL_MASK;
0474                 }
0475         vx_outb(chip, CDSP, pchip->regCDSP);
0476     }
0477     mutex_unlock(&chip->lock);
0478 }
0479 
0480 /*
0481  * remap the linear value (0-8) to the actual value (0-15)
0482  */
0483 static int vx_compute_mic_level(int level)
0484 {
0485     switch (level) {
0486     case 5: level = 6 ; break;
0487     case 6: level = 8 ; break;
0488     case 7: level = 11; break;
0489     case 8: level = 15; break;
0490     default: break ;
0491     }
0492     return level;
0493 }
0494 
0495 /*
0496  * vx_set_mic_level - set mic level (on vxpocket only)
0497  * @level: the mic level = 0 - 8 (max)
0498  */
0499 void vx_set_mic_level(struct vx_core *chip, int level)
0500 {
0501     struct snd_vxpocket *pchip = to_vxpocket(chip);
0502 
0503     if (chip->chip_status & VX_STAT_IS_STALE)
0504         return;
0505 
0506     mutex_lock(&chip->lock);
0507     if (pchip->regCDSP & VXP_CDSP_MIC_SEL_MASK) {
0508         level = vx_compute_mic_level(level);
0509         vx_outb(chip, MICRO, level);
0510     }
0511     mutex_unlock(&chip->lock);
0512 }
0513 
0514 
0515 /*
0516  * change the input audio source
0517  */
0518 static void vxp_change_audio_source(struct vx_core *_chip, int src)
0519 {
0520     struct snd_vxpocket *chip = to_vxpocket(_chip);
0521 
0522     switch (src) {
0523     case VX_AUDIO_SRC_DIGITAL:
0524         chip->regCDSP |= VXP_CDSP_DATAIN_SEL_MASK;
0525         vx_outb(chip, CDSP, chip->regCDSP);
0526         break;
0527     case VX_AUDIO_SRC_LINE:
0528         chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
0529         if (_chip->type == VX_TYPE_VXP440)
0530             chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
0531         else
0532             chip->regCDSP &= ~VXP_CDSP_MIC_SEL_MASK;
0533         vx_outb(chip, CDSP, chip->regCDSP);
0534         break;
0535     case VX_AUDIO_SRC_MIC:
0536         chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
0537         /* reset mic levels */
0538         if (_chip->type == VX_TYPE_VXP440) {
0539             chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
0540             if (chip->mic_level)
0541                 chip->regCDSP |=  P24_CDSP_MIC38_SEL_MASK;
0542             else
0543                 chip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
0544             vx_outb(chip, CDSP, chip->regCDSP);
0545         } else {
0546             chip->regCDSP |= VXP_CDSP_MIC_SEL_MASK;
0547             vx_outb(chip, CDSP, chip->regCDSP);
0548             vx_outb(chip, MICRO, vx_compute_mic_level(chip->mic_level));
0549         }
0550         break;
0551     }
0552 }
0553 
0554 /*
0555  * change the clock source
0556  * source = INTERNAL_QUARTZ or UER_SYNC
0557  */
0558 static void vxp_set_clock_source(struct vx_core *_chip, int source)
0559 {
0560     struct snd_vxpocket *chip = to_vxpocket(_chip);
0561 
0562     if (source == INTERNAL_QUARTZ)
0563         chip->regCDSP &= ~VXP_CDSP_CLOCKIN_SEL_MASK;
0564     else
0565         chip->regCDSP |= VXP_CDSP_CLOCKIN_SEL_MASK;
0566     vx_outb(chip, CDSP, chip->regCDSP);
0567 }
0568 
0569 
0570 /*
0571  * reset the board
0572  */
0573 static void vxp_reset_board(struct vx_core *_chip, int cold_reset)
0574 {
0575     struct snd_vxpocket *chip = to_vxpocket(_chip);
0576 
0577     chip->regCDSP = 0;
0578     chip->regDIALOG = 0;
0579 }
0580 
0581 
0582 /*
0583  * callbacks
0584  */
0585 /* exported */
0586 const struct snd_vx_ops snd_vxpocket_ops = {
0587     .in8 = vxp_inb,
0588     .out8 = vxp_outb,
0589     .test_and_ack = vxp_test_and_ack,
0590     .validate_irq = vxp_validate_irq,
0591     .write_codec = vxp_write_codec_reg,
0592     .reset_codec = vxp_reset_codec,
0593     .change_audio_source = vxp_change_audio_source,
0594     .set_clock_source = vxp_set_clock_source,
0595     .load_dsp = vxp_load_dsp,
0596     .add_controls = vxp_add_mic_controls,
0597     .reset_dsp = vxp_reset_dsp,
0598     .reset_board = vxp_reset_board,
0599     .dma_write = vxp_dma_write,
0600     .dma_read = vxp_dma_read,
0601 };
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