pci/ymfpci/ymfpci.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_YMFPCI_H
0003 #define __SOUND_YMFPCI_H
0004
0005 /*
0006  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
0007  *  Definitions for Yahama YMF724/740/744/754 chips
0008  */
0009
0010 #include <sound/pcm.h>
0011 #include <sound/rawmidi.h>
0012 #include <sound/ac97_codec.h>
0013 #include <sound/timer.h>
0014 #include <linux/gameport.h>
0015
0016 /*
0017  *  Direct registers
0018  */
0019
0020 #define YMFREG(chip, reg)       (chip->port + YDSXGR_##reg)
0021
0022 #define YDSXGR_INTFLAG          0x0004
0023 #define YDSXGR_ACTIVITY         0x0006
0024 #define YDSXGR_GLOBALCTRL       0x0008
0025 #define YDSXGR_ZVCTRL           0x000A
0026 #define YDSXGR_TIMERCTRL        0x0010
0027 #define YDSXGR_TIMERCOUNT       0x0012
0028 #define YDSXGR_SPDIFOUTCTRL     0x0018
0029 #define YDSXGR_SPDIFOUTSTATUS       0x001C
0030 #define YDSXGR_EEPROMCTRL       0x0020
0031 #define YDSXGR_SPDIFINCTRL      0x0034
0032 #define YDSXGR_SPDIFINSTATUS        0x0038
0033 #define YDSXGR_DSPPROGRAMDL     0x0048
0034 #define YDSXGR_DLCNTRL          0x004C
0035 #define YDSXGR_GPIOININTFLAG        0x0050
0036 #define YDSXGR_GPIOININTENABLE      0x0052
0037 #define YDSXGR_GPIOINSTATUS     0x0054
0038 #define YDSXGR_GPIOOUTCTRL      0x0056
0039 #define YDSXGR_GPIOFUNCENABLE       0x0058
0040 #define YDSXGR_GPIOTYPECONFIG       0x005A
0041 #define YDSXGR_AC97CMDDATA      0x0060
0042 #define YDSXGR_AC97CMDADR       0x0062
0043 #define YDSXGR_PRISTATUSDATA        0x0064
0044 #define YDSXGR_PRISTATUSADR     0x0066
0045 #define YDSXGR_SECSTATUSDATA        0x0068
0046 #define YDSXGR_SECSTATUSADR     0x006A
0047 #define YDSXGR_SECCONFIG        0x0070
0048 #define YDSXGR_LEGACYOUTVOL     0x0080
0049 #define YDSXGR_LEGACYOUTVOLL        0x0080
0050 #define YDSXGR_LEGACYOUTVOLR        0x0082
0051 #define YDSXGR_NATIVEDACOUTVOL      0x0084
0052 #define YDSXGR_NATIVEDACOUTVOLL     0x0084
0053 #define YDSXGR_NATIVEDACOUTVOLR     0x0086
0054 #define YDSXGR_ZVOUTVOL         0x0088
0055 #define YDSXGR_ZVOUTVOLL        0x0088
0056 #define YDSXGR_ZVOUTVOLR        0x008A
0057 #define YDSXGR_SECADCOUTVOL     0x008C
0058 #define YDSXGR_SECADCOUTVOLL        0x008C
0059 #define YDSXGR_SECADCOUTVOLR        0x008E
0060 #define YDSXGR_PRIADCOUTVOL     0x0090
0061 #define YDSXGR_PRIADCOUTVOLL        0x0090
0062 #define YDSXGR_PRIADCOUTVOLR        0x0092
0063 #define YDSXGR_LEGACYLOOPVOL        0x0094
0064 #define YDSXGR_LEGACYLOOPVOLL       0x0094
0065 #define YDSXGR_LEGACYLOOPVOLR       0x0096
0066 #define YDSXGR_NATIVEDACLOOPVOL     0x0098
0067 #define YDSXGR_NATIVEDACLOOPVOLL    0x0098
0068 #define YDSXGR_NATIVEDACLOOPVOLR    0x009A
0069 #define YDSXGR_ZVLOOPVOL        0x009C
0070 #define YDSXGR_ZVLOOPVOLL       0x009E
0071 #define YDSXGR_ZVLOOPVOLR       0x009E
0072 #define YDSXGR_SECADCLOOPVOL        0x00A0
0073 #define YDSXGR_SECADCLOOPVOLL       0x00A0
0074 #define YDSXGR_SECADCLOOPVOLR       0x00A2
0075 #define YDSXGR_PRIADCLOOPVOL        0x00A4
0076 #define YDSXGR_PRIADCLOOPVOLL       0x00A4
0077 #define YDSXGR_PRIADCLOOPVOLR       0x00A6
0078 #define YDSXGR_NATIVEADCINVOL       0x00A8
0079 #define YDSXGR_NATIVEADCINVOLL      0x00A8
0080 #define YDSXGR_NATIVEADCINVOLR      0x00AA
0081 #define YDSXGR_NATIVEDACINVOL       0x00AC
0082 #define YDSXGR_NATIVEDACINVOLL      0x00AC
0083 #define YDSXGR_NATIVEDACINVOLR      0x00AE
0084 #define YDSXGR_BUF441OUTVOL     0x00B0
0085 #define YDSXGR_BUF441OUTVOLL        0x00B0
0086 #define YDSXGR_BUF441OUTVOLR        0x00B2
0087 #define YDSXGR_BUF441LOOPVOL        0x00B4
0088 #define YDSXGR_BUF441LOOPVOLL       0x00B4
0089 #define YDSXGR_BUF441LOOPVOLR       0x00B6
0090 #define YDSXGR_SPDIFOUTVOL      0x00B8
0091 #define YDSXGR_SPDIFOUTVOLL     0x00B8
0092 #define YDSXGR_SPDIFOUTVOLR     0x00BA
0093 #define YDSXGR_SPDIFLOOPVOL     0x00BC
0094 #define YDSXGR_SPDIFLOOPVOLL        0x00BC
0095 #define YDSXGR_SPDIFLOOPVOLR        0x00BE
0096 #define YDSXGR_ADCSLOTSR        0x00C0
0097 #define YDSXGR_RECSLOTSR        0x00C4
0098 #define YDSXGR_ADCFORMAT        0x00C8
0099 #define YDSXGR_RECFORMAT        0x00CC
0100 #define YDSXGR_P44SLOTSR        0x00D0
0101 #define YDSXGR_STATUS           0x0100
0102 #define YDSXGR_CTRLSELECT       0x0104
0103 #define YDSXGR_MODE         0x0108
0104 #define YDSXGR_SAMPLECOUNT      0x010C
0105 #define YDSXGR_NUMOFSAMPLES     0x0110
0106 #define YDSXGR_CONFIG           0x0114
0107 #define YDSXGR_PLAYCTRLSIZE     0x0140
0108 #define YDSXGR_RECCTRLSIZE      0x0144
0109 #define YDSXGR_EFFCTRLSIZE      0x0148
0110 #define YDSXGR_WORKSIZE         0x014C
0111 #define YDSXGR_MAPOFREC         0x0150
0112 #define YDSXGR_MAPOFEFFECT      0x0154
0113 #define YDSXGR_PLAYCTRLBASE     0x0158
0114 #define YDSXGR_RECCTRLBASE      0x015C
0115 #define YDSXGR_EFFCTRLBASE      0x0160
0116 #define YDSXGR_WORKBASE         0x0164
0117 #define YDSXGR_DSPINSTRAM       0x1000
0118 #define YDSXGR_CTRLINSTRAM      0x4000
0119
0120 #define YDSXG_AC97READCMD       0x8000
0121 #define YDSXG_AC97WRITECMD      0x0000
0122
0123 #define PCIR_DSXG_LEGACY        0x40
0124 #define PCIR_DSXG_ELEGACY       0x42
0125 #define PCIR_DSXG_CTRL          0x48
0126 #define PCIR_DSXG_PWRCTRL1      0x4a
0127 #define PCIR_DSXG_PWRCTRL2      0x4e
0128 #define PCIR_DSXG_FMBASE        0x60
0129 #define PCIR_DSXG_SBBASE        0x62
0130 #define PCIR_DSXG_MPU401BASE        0x64
0131 #define PCIR_DSXG_JOYBASE       0x66
0132
0133 #define YDSXG_DSPLENGTH         0x0080
0134 #define YDSXG_CTRLLENGTH        0x3000
0135
0136 #define YDSXG_DEFAULT_WORK_SIZE     0x0400
0137
0138 #define YDSXG_PLAYBACK_VOICES       64
0139 #define YDSXG_CAPTURE_VOICES        2
0140 #define YDSXG_EFFECT_VOICES     5
0141
0142 #define YMFPCI_LEGACY_SBEN  (1 << 0)    /* soundblaster enable */
0143 #define YMFPCI_LEGACY_FMEN  (1 << 1)    /* OPL3 enable */
0144 #define YMFPCI_LEGACY_JPEN  (1 << 2)    /* joystick enable */
0145 #define YMFPCI_LEGACY_MEN   (1 << 3)    /* MPU401 enable */
0146 #define YMFPCI_LEGACY_MIEN  (1 << 4)    /* MPU RX irq enable */
0147 #define YMFPCI_LEGACY_IOBITS    (1 << 5)    /* i/o bits range, 0 = 16bit, 1 =10bit */
0148 #define YMFPCI_LEGACY_SDMA  (3 << 6)    /* SB DMA select */
0149 #define YMFPCI_LEGACY_SBIRQ (7 << 8)    /* SB IRQ select */
0150 #define YMFPCI_LEGACY_MPUIRQ    (7 << 11)   /* MPU IRQ select */
0151 #define YMFPCI_LEGACY_SIEN  (1 << 14)   /* serialized IRQ */
0152 #define YMFPCI_LEGACY_LAD   (1 << 15)   /* legacy audio disable */
0153
0154 #define YMFPCI_LEGACY2_FMIO (3 << 0)    /* OPL3 i/o address (724/740) */
0155 #define YMFPCI_LEGACY2_SBIO (3 << 2)    /* SB i/o address (724/740) */
0156 #define YMFPCI_LEGACY2_MPUIO    (3 << 4)    /* MPU401 i/o address (724/740) */
0157 #define YMFPCI_LEGACY2_JSIO (3 << 6)    /* joystick i/o address (724/740) */
0158 #define YMFPCI_LEGACY2_MAIM (1 << 8)    /* MPU401 ack intr mask */
0159 #define YMFPCI_LEGACY2_SMOD (3 << 11)   /* SB DMA mode */
0160 #define YMFPCI_LEGACY2_SBVER    (3 << 13)   /* SB version select */
0161 #define YMFPCI_LEGACY2_IMOD (1 << 15)   /* legacy IRQ mode */
0162 /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
0163
0164 #if IS_REACHABLE(CONFIG_GAMEPORT)
0165 #define SUPPORT_JOYSTICK
0166 #endif
0167
0168 /*
0169  *
0170  */
0171
0172 struct snd_ymfpci_playback_bank {
0173     __le32 format;
0174     __le32 loop_default;
0175     __le32 base;            /* 32-bit address */
0176     __le32 loop_start;      /* 32-bit offset */
0177     __le32 loop_end;        /* 32-bit offset */
0178     __le32 loop_frac;       /* 8-bit fraction - loop_start */
0179     __le32 delta_end;       /* pitch delta end */
0180     __le32 lpfK_end;
0181     __le32 eg_gain_end;
0182     __le32 left_gain_end;
0183     __le32 right_gain_end;
0184     __le32 eff1_gain_end;
0185     __le32 eff2_gain_end;
0186     __le32 eff3_gain_end;
0187     __le32 lpfQ;
0188     __le32 status;
0189     __le32 num_of_frames;
0190     __le32 loop_count;
0191     __le32 start;
0192     __le32 start_frac;
0193     __le32 delta;
0194     __le32 lpfK;
0195     __le32 eg_gain;
0196     __le32 left_gain;
0197     __le32 right_gain;
0198     __le32 eff1_gain;
0199     __le32 eff2_gain;
0200     __le32 eff3_gain;
0201     __le32 lpfD1;
0202     __le32 lpfD2;
0203  };
0204
0205 struct snd_ymfpci_capture_bank {
0206     __le32 base;            /* 32-bit address */
0207     __le32 loop_end;        /* 32-bit offset */
0208     __le32 start;           /* 32-bit offset */
0209     __le32 num_of_loops;        /* counter */
0210 };
0211
0212 struct snd_ymfpci_effect_bank {
0213     __le32 base;            /* 32-bit address */
0214     __le32 loop_end;        /* 32-bit offset */
0215     __le32 start;           /* 32-bit offset */
0216     __le32 temp;
0217 };
0218
0219 struct snd_ymfpci_pcm;
0220 struct snd_ymfpci;
0221
0222 enum snd_ymfpci_voice_type {
0223     YMFPCI_PCM,
0224     YMFPCI_SYNTH,
0225     YMFPCI_MIDI
0226 };
0227
0228 struct snd_ymfpci_voice {
0229     struct snd_ymfpci *chip;
0230     int number;
0231     unsigned int use: 1,
0232         pcm: 1,
0233         synth: 1,
0234         midi: 1;
0235     struct snd_ymfpci_playback_bank *bank;
0236     dma_addr_t bank_addr;
0237     void (*interrupt)(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice);
0238     struct snd_ymfpci_pcm *ypcm;
0239 };
0240
0241 enum snd_ymfpci_pcm_type {
0242     PLAYBACK_VOICE,
0243     CAPTURE_REC,
0244     CAPTURE_AC97,
0245     EFFECT_DRY_LEFT,
0246     EFFECT_DRY_RIGHT,
0247     EFFECT_EFF1,
0248     EFFECT_EFF2,
0249     EFFECT_EFF3
0250 };
0251
0252 struct snd_ymfpci_pcm {
0253     struct snd_ymfpci *chip;
0254     enum snd_ymfpci_pcm_type type;
0255     struct snd_pcm_substream *substream;
0256     struct snd_ymfpci_voice *voices[2]; /* playback only */
0257     unsigned int running: 1,
0258              use_441_slot: 1,
0259                  output_front: 1,
0260                  output_rear: 1,
0261                  swap_rear: 1;
0262     unsigned int update_pcm_vol;
0263     u32 period_size;        /* cached from runtime->period_size */
0264     u32 buffer_size;        /* cached from runtime->buffer_size */
0265     u32 period_pos;
0266     u32 last_pos;
0267     u32 capture_bank_number;
0268     u32 shift;
0269 };
0270
0271 struct snd_ymfpci {
0272     int irq;
0273
0274     unsigned int device_id; /* PCI device ID */
0275     unsigned char rev;  /* PCI revision */
0276     unsigned long reg_area_phys;
0277     void __iomem *reg_area_virt;
0278
0279     unsigned short old_legacy_ctrl;
0280 #ifdef SUPPORT_JOYSTICK
0281     struct gameport *gameport;
0282 #endif
0283
0284     struct snd_dma_buffer *work_ptr;
0285
0286     unsigned int bank_size_playback;
0287     unsigned int bank_size_capture;
0288     unsigned int bank_size_effect;
0289     unsigned int work_size;
0290
0291     void *bank_base_playback;
0292     void *bank_base_capture;
0293     void *bank_base_effect;
0294     void *work_base;
0295     dma_addr_t bank_base_playback_addr;
0296     dma_addr_t bank_base_capture_addr;
0297     dma_addr_t bank_base_effect_addr;
0298     dma_addr_t work_base_addr;
0299     struct snd_dma_buffer ac3_tmp_base;
0300
0301     __le32 *ctrl_playback;
0302     struct snd_ymfpci_playback_bank *bank_playback[YDSXG_PLAYBACK_VOICES][2];
0303     struct snd_ymfpci_capture_bank *bank_capture[YDSXG_CAPTURE_VOICES][2];
0304     struct snd_ymfpci_effect_bank *bank_effect[YDSXG_EFFECT_VOICES][2];
0305
0306     int start_count;
0307
0308     u32 active_bank;
0309     struct snd_ymfpci_voice voices[64];
0310     int src441_used;
0311
0312     struct snd_ac97_bus *ac97_bus;
0313     struct snd_ac97 *ac97;
0314     struct snd_rawmidi *rawmidi;
0315     struct snd_timer *timer;
0316     unsigned int timer_ticks;
0317
0318     struct pci_dev *pci;
0319     struct snd_card *card;
0320     struct snd_pcm *pcm;
0321     struct snd_pcm *pcm2;
0322     struct snd_pcm *pcm_spdif;
0323     struct snd_pcm *pcm_4ch;
0324     struct snd_pcm_substream *capture_substream[YDSXG_CAPTURE_VOICES];
0325     struct snd_pcm_substream *effect_substream[YDSXG_EFFECT_VOICES];
0326     struct snd_kcontrol *ctl_vol_recsrc;
0327     struct snd_kcontrol *ctl_vol_adcrec;
0328     struct snd_kcontrol *ctl_vol_spdifrec;
0329     unsigned short spdif_bits, spdif_pcm_bits;
0330     struct snd_kcontrol *spdif_pcm_ctl;
0331     int mode_dup4ch;
0332     int rear_opened;
0333     int spdif_opened;
0334     struct snd_ymfpci_pcm_mixer {
0335         u16 left;
0336         u16 right;
0337         struct snd_kcontrol *ctl;
0338     } pcm_mixer[32];
0339
0340     spinlock_t reg_lock;
0341     spinlock_t voice_lock;
0342     wait_queue_head_t interrupt_sleep;
0343     atomic_t interrupt_sleep_count;
0344     struct snd_info_entry *proc_entry;
0345     const struct firmware *dsp_microcode;
0346     const struct firmware *controller_microcode;
0347
0348 #ifdef CONFIG_PM_SLEEP
0349     u32 *saved_regs;
0350     u32 saved_ydsxgr_mode;
0351     u16 saved_dsxg_legacy;
0352     u16 saved_dsxg_elegacy;
0353 #endif
0354 };
0355
0356 int snd_ymfpci_create(struct snd_card *card,
0357               struct pci_dev *pci,
0358               unsigned short old_legacy_ctrl);
0359 void snd_ymfpci_free_gameport(struct snd_ymfpci *chip);
0360
0361 extern const struct dev_pm_ops snd_ymfpci_pm;
0362
0363 int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device);
0364 int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device);
0365 int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device);
0366 int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device);
0367 int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch);
0368 int snd_ymfpci_timer(struct snd_ymfpci *chip, int device);
0369
0370 #endif /* __SOUND_YMFPCI_H */