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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Digigram VX222 V2/Mic soundcards
0004  *
0005  * VX222-specific low-level routines
0006  *
0007  * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/firmware.h>
0013 #include <linux/mutex.h>
0014 #include <linux/io.h>
0015 
0016 #include <sound/core.h>
0017 #include <sound/control.h>
0018 #include <sound/tlv.h>
0019 #include "vx222.h"
0020 
0021 
0022 static const int vx2_reg_offset[VX_REG_MAX] = {
0023     [VX_ICR]    = 0x00,
0024     [VX_CVR]    = 0x04,
0025     [VX_ISR]    = 0x08,
0026     [VX_IVR]    = 0x0c,
0027     [VX_RXH]    = 0x14,
0028     [VX_RXM]    = 0x18,
0029     [VX_RXL]    = 0x1c,
0030     [VX_DMA]    = 0x10,
0031     [VX_CDSP]   = 0x20,
0032     [VX_CFG]    = 0x24,
0033     [VX_RUER]   = 0x28,
0034     [VX_DATA]   = 0x2c,
0035     [VX_STATUS] = 0x30,
0036     [VX_LOFREQ] = 0x34,
0037     [VX_HIFREQ] = 0x38,
0038     [VX_CSUER]  = 0x3c,
0039     [VX_SELMIC] = 0x40,
0040     [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate
0041     [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate
0042     [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate
0043     [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET
0044     [VX_CNTRL]  = 0x50,     // VX_CNTRL_REGISTER_OFFSET
0045     [VX_GPIOC]  = 0x54,     // VX_GPIOC (new with PLX9030)
0046 };
0047 
0048 static const int vx2_reg_index[VX_REG_MAX] = {
0049     [VX_ICR]    = 1,
0050     [VX_CVR]    = 1,
0051     [VX_ISR]    = 1,
0052     [VX_IVR]    = 1,
0053     [VX_RXH]    = 1,
0054     [VX_RXM]    = 1,
0055     [VX_RXL]    = 1,
0056     [VX_DMA]    = 1,
0057     [VX_CDSP]   = 1,
0058     [VX_CFG]    = 1,
0059     [VX_RUER]   = 1,
0060     [VX_DATA]   = 1,
0061     [VX_STATUS] = 1,
0062     [VX_LOFREQ] = 1,
0063     [VX_HIFREQ] = 1,
0064     [VX_CSUER]  = 1,
0065     [VX_SELMIC] = 1,
0066     [VX_COMPOT] = 1,
0067     [VX_SCOMPR] = 1,
0068     [VX_GLIMIT] = 1,
0069     [VX_INTCSR] = 0,    /* on the PLX */
0070     [VX_CNTRL]  = 0,    /* on the PLX */
0071     [VX_GPIOC]  = 0,    /* on the PLX */
0072 };
0073 
0074 static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg)
0075 {
0076     struct snd_vx222 *chip = to_vx222(_chip);
0077     return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg];
0078 }
0079 
0080 /**
0081  * vx2_inb - read a byte from the register
0082  * @chip: VX core instance
0083  * @offset: register enum
0084  */
0085 static unsigned char vx2_inb(struct vx_core *chip, int offset)
0086 {
0087     return inb(vx2_reg_addr(chip, offset));
0088 }
0089 
0090 /**
0091  * vx2_outb - write a byte on the register
0092  * @chip: VX core instance
0093  * @offset: the register offset
0094  * @val: the value to write
0095  */
0096 static void vx2_outb(struct vx_core *chip, int offset, unsigned char val)
0097 {
0098     outb(val, vx2_reg_addr(chip, offset));
0099     /*
0100     dev_dbg(chip->card->dev, "outb: %x -> %x\n", val, vx2_reg_addr(chip, offset));
0101     */
0102 }
0103 
0104 /**
0105  * vx2_inl - read a 32bit word from the register
0106  * @chip: VX core instance
0107  * @offset: register enum
0108  */
0109 static unsigned int vx2_inl(struct vx_core *chip, int offset)
0110 {
0111     return inl(vx2_reg_addr(chip, offset));
0112 }
0113 
0114 /**
0115  * vx2_outl - write a 32bit word on the register
0116  * @chip: VX core instance
0117  * @offset: the register enum
0118  * @val: the value to write
0119  */
0120 static void vx2_outl(struct vx_core *chip, int offset, unsigned int val)
0121 {
0122     /*
0123     dev_dbg(chip->card->dev, "outl: %x -> %x\n", val, vx2_reg_addr(chip, offset));
0124     */
0125     outl(val, vx2_reg_addr(chip, offset));
0126 }
0127 
0128 /*
0129  * redefine macros to call directly
0130  */
0131 #undef vx_inb
0132 #define vx_inb(chip,reg)    vx2_inb((struct vx_core*)(chip), VX_##reg)
0133 #undef vx_outb
0134 #define vx_outb(chip,reg,val)   vx2_outb((struct vx_core*)(chip), VX_##reg, val)
0135 #undef vx_inl
0136 #define vx_inl(chip,reg)    vx2_inl((struct vx_core*)(chip), VX_##reg)
0137 #undef vx_outl
0138 #define vx_outl(chip,reg,val)   vx2_outl((struct vx_core*)(chip), VX_##reg, val)
0139 
0140 
0141 /*
0142  * vx_reset_dsp - reset the DSP
0143  */
0144 
0145 #define XX_DSP_RESET_WAIT_TIME      2   /* ms */
0146 
0147 static void vx2_reset_dsp(struct vx_core *_chip)
0148 {
0149     struct snd_vx222 *chip = to_vx222(_chip);
0150 
0151     /* set the reset dsp bit to 0 */
0152     vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
0153 
0154     mdelay(XX_DSP_RESET_WAIT_TIME);
0155 
0156     chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
0157     /* set the reset dsp bit to 1 */
0158     vx_outl(chip, CDSP, chip->regCDSP);
0159 }
0160 
0161 
0162 static int vx2_test_xilinx(struct vx_core *_chip)
0163 {
0164     struct snd_vx222 *chip = to_vx222(_chip);
0165     unsigned int data;
0166 
0167     dev_dbg(_chip->card->dev, "testing xilinx...\n");
0168     /* This test uses several write/read sequences on TEST0 and TEST1 bits
0169      * to figure out whever or not the xilinx was correctly loaded
0170      */
0171 
0172     /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */
0173     vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
0174     vx_inl(chip, ISR);
0175     data = vx_inl(chip, STATUS);
0176     if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
0177         dev_dbg(_chip->card->dev, "bad!\n");
0178         return -ENODEV;
0179     }
0180 
0181     /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */
0182     vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
0183     vx_inl(chip, ISR);
0184     data = vx_inl(chip, STATUS);
0185     if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
0186         dev_dbg(_chip->card->dev, "bad! #2\n");
0187         return -ENODEV;
0188     }
0189 
0190     if (_chip->type == VX_TYPE_BOARD) {
0191         /* not implemented on VX_2_BOARDS */
0192         /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */
0193         vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
0194         vx_inl(chip, ISR);
0195         data = vx_inl(chip, STATUS);
0196         if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
0197             dev_dbg(_chip->card->dev, "bad! #3\n");
0198             return -ENODEV;
0199         }
0200 
0201         /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */
0202         vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
0203         vx_inl(chip, ISR);
0204         data = vx_inl(chip, STATUS);
0205         if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
0206             dev_dbg(_chip->card->dev, "bad! #4\n");
0207             return -ENODEV;
0208         }
0209     }
0210     dev_dbg(_chip->card->dev, "ok, xilinx fine.\n");
0211     return 0;
0212 }
0213 
0214 
0215 /**
0216  * vx2_setup_pseudo_dma - set up the pseudo dma read/write mode.
0217  * @chip: VX core instance
0218  * @do_write: 0 = read, 1 = set up for DMA write
0219  */
0220 static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write)
0221 {
0222     /* Interrupt mode and HREQ pin enabled for host transmit data transfers
0223      * (in case of the use of the pseudo-dma facility).
0224      */
0225     vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
0226 
0227     /* Reset the pseudo-dma register (in case of the use of the
0228      * pseudo-dma facility).
0229      */
0230     vx_outl(chip, RESET_DMA, 0);
0231 }
0232 
0233 /*
0234  * vx_release_pseudo_dma - disable the pseudo-DMA mode
0235  */
0236 static inline void vx2_release_pseudo_dma(struct vx_core *chip)
0237 {
0238     /* HREQ pin disabled. */
0239     vx_outl(chip, ICR, 0);
0240 }
0241 
0242 
0243 
0244 /* pseudo-dma write */
0245 static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0246               struct vx_pipe *pipe, int count)
0247 {
0248     unsigned long port = vx2_reg_addr(chip, VX_DMA);
0249     int offset = pipe->hw_ptr;
0250     u32 *addr = (u32 *)(runtime->dma_area + offset);
0251 
0252     if (snd_BUG_ON(count % 4))
0253         return;
0254 
0255     vx2_setup_pseudo_dma(chip, 1);
0256 
0257     /* Transfer using pseudo-dma.
0258      */
0259     if (offset + count >= pipe->buffer_bytes) {
0260         int length = pipe->buffer_bytes - offset;
0261         count -= length;
0262         length >>= 2; /* in 32bit words */
0263         /* Transfer using pseudo-dma. */
0264         for (; length > 0; length--) {
0265             outl(*addr, port);
0266             addr++;
0267         }
0268         addr = (u32 *)runtime->dma_area;
0269         pipe->hw_ptr = 0;
0270     }
0271     pipe->hw_ptr += count;
0272     count >>= 2; /* in 32bit words */
0273     /* Transfer using pseudo-dma. */
0274     for (; count > 0; count--) {
0275         outl(*addr, port);
0276         addr++;
0277     }
0278 
0279     vx2_release_pseudo_dma(chip);
0280 }
0281 
0282 
0283 /* pseudo dma read */
0284 static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0285              struct vx_pipe *pipe, int count)
0286 {
0287     int offset = pipe->hw_ptr;
0288     u32 *addr = (u32 *)(runtime->dma_area + offset);
0289     unsigned long port = vx2_reg_addr(chip, VX_DMA);
0290 
0291     if (snd_BUG_ON(count % 4))
0292         return;
0293 
0294     vx2_setup_pseudo_dma(chip, 0);
0295     /* Transfer using pseudo-dma.
0296      */
0297     if (offset + count >= pipe->buffer_bytes) {
0298         int length = pipe->buffer_bytes - offset;
0299         count -= length;
0300         length >>= 2; /* in 32bit words */
0301         /* Transfer using pseudo-dma. */
0302         for (; length > 0; length--)
0303             *addr++ = inl(port);
0304         addr = (u32 *)runtime->dma_area;
0305         pipe->hw_ptr = 0;
0306     }
0307     pipe->hw_ptr += count;
0308     count >>= 2; /* in 32bit words */
0309     /* Transfer using pseudo-dma. */
0310     for (; count > 0; count--)
0311         *addr++ = inl(port);
0312 
0313     vx2_release_pseudo_dma(chip);
0314 }
0315 
0316 #define VX_XILINX_RESET_MASK        0x40000000
0317 #define VX_USERBIT0_MASK            0x00000004
0318 #define VX_USERBIT1_MASK            0x00000020
0319 #define VX_CNTRL_REGISTER_VALUE     0x00172012
0320 
0321 /*
0322  * transfer counts bits to PLX
0323  */
0324 static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data)
0325 {
0326     unsigned int i;
0327 
0328     for (i = 0; i < counts; i++) {
0329         unsigned int val;
0330 
0331         /* set the clock bit to 0. */
0332         val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK;
0333         vx2_outl(chip, port, val);
0334         vx2_inl(chip, port);
0335         udelay(1);
0336 
0337         if (data & (1 << i))
0338             val |= VX_USERBIT1_MASK;
0339         else
0340             val &= ~VX_USERBIT1_MASK;
0341         vx2_outl(chip, port, val);
0342         vx2_inl(chip, port);
0343 
0344         /* set the clock bit to 1. */
0345         val |= VX_USERBIT0_MASK;
0346         vx2_outl(chip, port, val);
0347         vx2_inl(chip, port);
0348         udelay(1);
0349     }
0350     return 0;
0351 }
0352 
0353 /*
0354  * load the xilinx image
0355  */
0356 static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx)
0357 {
0358     unsigned int i;
0359     unsigned int port;
0360     const unsigned char *image;
0361 
0362     /* XILINX reset (wait at least 1 millisecond between reset on and off). */
0363     vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
0364     vx_inl(chip, CNTRL);
0365     msleep(10);
0366     vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
0367     vx_inl(chip, CNTRL);
0368     msleep(10);
0369 
0370     if (chip->type == VX_TYPE_BOARD)
0371         port = VX_CNTRL;
0372     else
0373         port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */
0374 
0375     image = xilinx->data;
0376     for (i = 0; i < xilinx->size; i++, image++) {
0377         if (put_xilinx_data(chip, port, 8, *image) < 0)
0378             return -EINVAL;
0379         /* don't take too much time in this loop... */
0380         cond_resched();
0381     }
0382     put_xilinx_data(chip, port, 4, 0xff); /* end signature */
0383 
0384     msleep(200);
0385 
0386     /* test after loading (is buggy with VX222) */
0387     if (chip->type != VX_TYPE_BOARD) {
0388         /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */
0389         i = vx_inl(chip, GPIOC);
0390         if (i & 0x0100)
0391             return 0;
0392         dev_err(chip->card->dev,
0393             "xilinx test failed after load, GPIOC=0x%x\n", i);
0394         return -EINVAL;
0395     }
0396 
0397     return 0;
0398 }
0399 
0400     
0401 /*
0402  * load the boot/dsp images
0403  */
0404 static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp)
0405 {
0406     int err;
0407 
0408     switch (index) {
0409     case 1:
0410         /* xilinx image */
0411         err = vx2_load_xilinx_binary(vx, dsp);
0412         if (err < 0)
0413             return err;
0414         err = vx2_test_xilinx(vx);
0415         if (err < 0)
0416             return err;
0417         return 0;
0418     case 2:
0419         /* DSP boot */
0420         return snd_vx_dsp_boot(vx, dsp);
0421     case 3:
0422         /* DSP image */
0423         return snd_vx_dsp_load(vx, dsp);
0424     default:
0425         snd_BUG();
0426         return -EINVAL;
0427     }
0428 }
0429 
0430 
0431 /*
0432  * vx_test_and_ack - test and acknowledge interrupt
0433  *
0434  * called from irq hander, too
0435  *
0436  * spinlock held!
0437  */
0438 static int vx2_test_and_ack(struct vx_core *chip)
0439 {
0440     /* not booted yet? */
0441     if (! (chip->chip_status & VX_STAT_XILINX_LOADED))
0442         return -ENXIO;
0443 
0444     if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK))
0445         return -EIO;
0446     
0447     /* ok, interrupts generated, now ack it */
0448     /* set ACQUIT bit up and down */
0449     vx_outl(chip, STATUS, 0);
0450     /* useless read just to spend some time and maintain
0451      * the ACQUIT signal up for a while ( a bus cycle )
0452      */
0453     vx_inl(chip, STATUS);
0454     /* ack */
0455     vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK);
0456     /* useless read just to spend some time and maintain
0457      * the ACQUIT signal up for a while ( a bus cycle ) */
0458     vx_inl(chip, STATUS);
0459     /* clear */
0460     vx_outl(chip, STATUS, 0);
0461 
0462     return 0;
0463 }
0464 
0465 
0466 /*
0467  * vx_validate_irq - enable/disable IRQ
0468  */
0469 static void vx2_validate_irq(struct vx_core *_chip, int enable)
0470 {
0471     struct snd_vx222 *chip = to_vx222(_chip);
0472 
0473     /* Set the interrupt enable bit to 1 in CDSP register */
0474     if (enable) {
0475         /* Set the PCI interrupt enable bit to 1.*/
0476         vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK);
0477         chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK;
0478     } else {
0479         /* Set the PCI interrupt enable bit to 0. */
0480         vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK);
0481         chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK;
0482     }
0483     vx_outl(chip, CDSP, chip->regCDSP);
0484 }
0485 
0486 
0487 /*
0488  * write an AKM codec data (24bit)
0489  */
0490 static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data)
0491 {
0492     unsigned int i;
0493 
0494     vx_inl(chip, HIFREQ);
0495 
0496     /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
0497     for (i = 0; i < 24; i++, data <<= 1)
0498         vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
0499     /* Terminate access to codec registers */
0500     vx_inl(chip, RUER);
0501 }
0502 
0503 
0504 #define AKM_CODEC_POWER_CONTROL_CMD 0xA007
0505 #define AKM_CODEC_RESET_ON_CMD      0xA100
0506 #define AKM_CODEC_RESET_OFF_CMD     0xA103
0507 #define AKM_CODEC_CLOCK_FORMAT_CMD  0xA240
0508 #define AKM_CODEC_MUTE_CMD          0xA38D
0509 #define AKM_CODEC_UNMUTE_CMD        0xA30D
0510 #define AKM_CODEC_LEFT_LEVEL_CMD    0xA400
0511 #define AKM_CODEC_RIGHT_LEVEL_CMD   0xA500
0512 
0513 static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = {
0514     0x7f,       // [000] =  +0.000 dB  ->  AKM(0x7f) =  +0.000 dB  error(+0.000 dB)
0515     0x7d,       // [001] =  -0.500 dB  ->  AKM(0x7d) =  -0.572 dB  error(-0.072 dB)
0516     0x7c,       // [002] =  -1.000 dB  ->  AKM(0x7c) =  -0.873 dB  error(+0.127 dB)
0517     0x7a,       // [003] =  -1.500 dB  ->  AKM(0x7a) =  -1.508 dB  error(-0.008 dB)
0518     0x79,       // [004] =  -2.000 dB  ->  AKM(0x79) =  -1.844 dB  error(+0.156 dB)
0519     0x77,       // [005] =  -2.500 dB  ->  AKM(0x77) =  -2.557 dB  error(-0.057 dB)
0520     0x76,       // [006] =  -3.000 dB  ->  AKM(0x76) =  -2.937 dB  error(+0.063 dB)
0521     0x75,       // [007] =  -3.500 dB  ->  AKM(0x75) =  -3.334 dB  error(+0.166 dB)
0522     0x73,       // [008] =  -4.000 dB  ->  AKM(0x73) =  -4.188 dB  error(-0.188 dB)
0523     0x72,       // [009] =  -4.500 dB  ->  AKM(0x72) =  -4.648 dB  error(-0.148 dB)
0524     0x71,       // [010] =  -5.000 dB  ->  AKM(0x71) =  -5.134 dB  error(-0.134 dB)
0525     0x70,       // [011] =  -5.500 dB  ->  AKM(0x70) =  -5.649 dB  error(-0.149 dB)
0526     0x6f,       // [012] =  -6.000 dB  ->  AKM(0x6f) =  -6.056 dB  error(-0.056 dB)
0527     0x6d,       // [013] =  -6.500 dB  ->  AKM(0x6d) =  -6.631 dB  error(-0.131 dB)
0528     0x6c,       // [014] =  -7.000 dB  ->  AKM(0x6c) =  -6.933 dB  error(+0.067 dB)
0529     0x6a,       // [015] =  -7.500 dB  ->  AKM(0x6a) =  -7.571 dB  error(-0.071 dB)
0530     0x69,       // [016] =  -8.000 dB  ->  AKM(0x69) =  -7.909 dB  error(+0.091 dB)
0531     0x67,       // [017] =  -8.500 dB  ->  AKM(0x67) =  -8.626 dB  error(-0.126 dB)
0532     0x66,       // [018] =  -9.000 dB  ->  AKM(0x66) =  -9.008 dB  error(-0.008 dB)
0533     0x65,       // [019] =  -9.500 dB  ->  AKM(0x65) =  -9.407 dB  error(+0.093 dB)
0534     0x64,       // [020] = -10.000 dB  ->  AKM(0x64) =  -9.826 dB  error(+0.174 dB)
0535     0x62,       // [021] = -10.500 dB  ->  AKM(0x62) = -10.730 dB  error(-0.230 dB)
0536     0x61,       // [022] = -11.000 dB  ->  AKM(0x61) = -11.219 dB  error(-0.219 dB)
0537     0x60,       // [023] = -11.500 dB  ->  AKM(0x60) = -11.738 dB  error(-0.238 dB)
0538     0x5f,       // [024] = -12.000 dB  ->  AKM(0x5f) = -12.149 dB  error(-0.149 dB)
0539     0x5e,       // [025] = -12.500 dB  ->  AKM(0x5e) = -12.434 dB  error(+0.066 dB)
0540     0x5c,       // [026] = -13.000 dB  ->  AKM(0x5c) = -13.033 dB  error(-0.033 dB)
0541     0x5b,       // [027] = -13.500 dB  ->  AKM(0x5b) = -13.350 dB  error(+0.150 dB)
0542     0x59,       // [028] = -14.000 dB  ->  AKM(0x59) = -14.018 dB  error(-0.018 dB)
0543     0x58,       // [029] = -14.500 dB  ->  AKM(0x58) = -14.373 dB  error(+0.127 dB)
0544     0x56,       // [030] = -15.000 dB  ->  AKM(0x56) = -15.130 dB  error(-0.130 dB)
0545     0x55,       // [031] = -15.500 dB  ->  AKM(0x55) = -15.534 dB  error(-0.034 dB)
0546     0x54,       // [032] = -16.000 dB  ->  AKM(0x54) = -15.958 dB  error(+0.042 dB)
0547     0x53,       // [033] = -16.500 dB  ->  AKM(0x53) = -16.404 dB  error(+0.096 dB)
0548     0x52,       // [034] = -17.000 dB  ->  AKM(0x52) = -16.874 dB  error(+0.126 dB)
0549     0x51,       // [035] = -17.500 dB  ->  AKM(0x51) = -17.371 dB  error(+0.129 dB)
0550     0x50,       // [036] = -18.000 dB  ->  AKM(0x50) = -17.898 dB  error(+0.102 dB)
0551     0x4e,       // [037] = -18.500 dB  ->  AKM(0x4e) = -18.605 dB  error(-0.105 dB)
0552     0x4d,       // [038] = -19.000 dB  ->  AKM(0x4d) = -18.905 dB  error(+0.095 dB)
0553     0x4b,       // [039] = -19.500 dB  ->  AKM(0x4b) = -19.538 dB  error(-0.038 dB)
0554     0x4a,       // [040] = -20.000 dB  ->  AKM(0x4a) = -19.872 dB  error(+0.128 dB)
0555     0x48,       // [041] = -20.500 dB  ->  AKM(0x48) = -20.583 dB  error(-0.083 dB)
0556     0x47,       // [042] = -21.000 dB  ->  AKM(0x47) = -20.961 dB  error(+0.039 dB)
0557     0x46,       // [043] = -21.500 dB  ->  AKM(0x46) = -21.356 dB  error(+0.144 dB)
0558     0x44,       // [044] = -22.000 dB  ->  AKM(0x44) = -22.206 dB  error(-0.206 dB)
0559     0x43,       // [045] = -22.500 dB  ->  AKM(0x43) = -22.664 dB  error(-0.164 dB)
0560     0x42,       // [046] = -23.000 dB  ->  AKM(0x42) = -23.147 dB  error(-0.147 dB)
0561     0x41,       // [047] = -23.500 dB  ->  AKM(0x41) = -23.659 dB  error(-0.159 dB)
0562     0x40,       // [048] = -24.000 dB  ->  AKM(0x40) = -24.203 dB  error(-0.203 dB)
0563     0x3f,       // [049] = -24.500 dB  ->  AKM(0x3f) = -24.635 dB  error(-0.135 dB)
0564     0x3e,       // [050] = -25.000 dB  ->  AKM(0x3e) = -24.935 dB  error(+0.065 dB)
0565     0x3c,       // [051] = -25.500 dB  ->  AKM(0x3c) = -25.569 dB  error(-0.069 dB)
0566     0x3b,       // [052] = -26.000 dB  ->  AKM(0x3b) = -25.904 dB  error(+0.096 dB)
0567     0x39,       // [053] = -26.500 dB  ->  AKM(0x39) = -26.615 dB  error(-0.115 dB)
0568     0x38,       // [054] = -27.000 dB  ->  AKM(0x38) = -26.994 dB  error(+0.006 dB)
0569     0x37,       // [055] = -27.500 dB  ->  AKM(0x37) = -27.390 dB  error(+0.110 dB)
0570     0x36,       // [056] = -28.000 dB  ->  AKM(0x36) = -27.804 dB  error(+0.196 dB)
0571     0x34,       // [057] = -28.500 dB  ->  AKM(0x34) = -28.699 dB  error(-0.199 dB)
0572     0x33,       // [058] = -29.000 dB  ->  AKM(0x33) = -29.183 dB  error(-0.183 dB)
0573     0x32,       // [059] = -29.500 dB  ->  AKM(0x32) = -29.696 dB  error(-0.196 dB)
0574     0x31,       // [060] = -30.000 dB  ->  AKM(0x31) = -30.241 dB  error(-0.241 dB)
0575     0x31,       // [061] = -30.500 dB  ->  AKM(0x31) = -30.241 dB  error(+0.259 dB)
0576     0x30,       // [062] = -31.000 dB  ->  AKM(0x30) = -30.823 dB  error(+0.177 dB)
0577     0x2e,       // [063] = -31.500 dB  ->  AKM(0x2e) = -31.610 dB  error(-0.110 dB)
0578     0x2d,       // [064] = -32.000 dB  ->  AKM(0x2d) = -31.945 dB  error(+0.055 dB)
0579     0x2b,       // [065] = -32.500 dB  ->  AKM(0x2b) = -32.659 dB  error(-0.159 dB)
0580     0x2a,       // [066] = -33.000 dB  ->  AKM(0x2a) = -33.038 dB  error(-0.038 dB)
0581     0x29,       // [067] = -33.500 dB  ->  AKM(0x29) = -33.435 dB  error(+0.065 dB)
0582     0x28,       // [068] = -34.000 dB  ->  AKM(0x28) = -33.852 dB  error(+0.148 dB)
0583     0x27,       // [069] = -34.500 dB  ->  AKM(0x27) = -34.289 dB  error(+0.211 dB)
0584     0x25,       // [070] = -35.000 dB  ->  AKM(0x25) = -35.235 dB  error(-0.235 dB)
0585     0x24,       // [071] = -35.500 dB  ->  AKM(0x24) = -35.750 dB  error(-0.250 dB)
0586     0x24,       // [072] = -36.000 dB  ->  AKM(0x24) = -35.750 dB  error(+0.250 dB)
0587     0x23,       // [073] = -36.500 dB  ->  AKM(0x23) = -36.297 dB  error(+0.203 dB)
0588     0x22,       // [074] = -37.000 dB  ->  AKM(0x22) = -36.881 dB  error(+0.119 dB)
0589     0x21,       // [075] = -37.500 dB  ->  AKM(0x21) = -37.508 dB  error(-0.008 dB)
0590     0x20,       // [076] = -38.000 dB  ->  AKM(0x20) = -38.183 dB  error(-0.183 dB)
0591     0x1f,       // [077] = -38.500 dB  ->  AKM(0x1f) = -38.726 dB  error(-0.226 dB)
0592     0x1e,       // [078] = -39.000 dB  ->  AKM(0x1e) = -39.108 dB  error(-0.108 dB)
0593     0x1d,       // [079] = -39.500 dB  ->  AKM(0x1d) = -39.507 dB  error(-0.007 dB)
0594     0x1c,       // [080] = -40.000 dB  ->  AKM(0x1c) = -39.926 dB  error(+0.074 dB)
0595     0x1b,       // [081] = -40.500 dB  ->  AKM(0x1b) = -40.366 dB  error(+0.134 dB)
0596     0x1a,       // [082] = -41.000 dB  ->  AKM(0x1a) = -40.829 dB  error(+0.171 dB)
0597     0x19,       // [083] = -41.500 dB  ->  AKM(0x19) = -41.318 dB  error(+0.182 dB)
0598     0x18,       // [084] = -42.000 dB  ->  AKM(0x18) = -41.837 dB  error(+0.163 dB)
0599     0x17,       // [085] = -42.500 dB  ->  AKM(0x17) = -42.389 dB  error(+0.111 dB)
0600     0x16,       // [086] = -43.000 dB  ->  AKM(0x16) = -42.978 dB  error(+0.022 dB)
0601     0x15,       // [087] = -43.500 dB  ->  AKM(0x15) = -43.610 dB  error(-0.110 dB)
0602     0x14,       // [088] = -44.000 dB  ->  AKM(0x14) = -44.291 dB  error(-0.291 dB)
0603     0x14,       // [089] = -44.500 dB  ->  AKM(0x14) = -44.291 dB  error(+0.209 dB)
0604     0x13,       // [090] = -45.000 dB  ->  AKM(0x13) = -45.031 dB  error(-0.031 dB)
0605     0x12,       // [091] = -45.500 dB  ->  AKM(0x12) = -45.840 dB  error(-0.340 dB)
0606     0x12,       // [092] = -46.000 dB  ->  AKM(0x12) = -45.840 dB  error(+0.160 dB)
0607     0x11,       // [093] = -46.500 dB  ->  AKM(0x11) = -46.731 dB  error(-0.231 dB)
0608     0x11,       // [094] = -47.000 dB  ->  AKM(0x11) = -46.731 dB  error(+0.269 dB)
0609     0x10,       // [095] = -47.500 dB  ->  AKM(0x10) = -47.725 dB  error(-0.225 dB)
0610     0x10,       // [096] = -48.000 dB  ->  AKM(0x10) = -47.725 dB  error(+0.275 dB)
0611     0x0f,       // [097] = -48.500 dB  ->  AKM(0x0f) = -48.553 dB  error(-0.053 dB)
0612     0x0e,       // [098] = -49.000 dB  ->  AKM(0x0e) = -49.152 dB  error(-0.152 dB)
0613     0x0d,       // [099] = -49.500 dB  ->  AKM(0x0d) = -49.796 dB  error(-0.296 dB)
0614     0x0d,       // [100] = -50.000 dB  ->  AKM(0x0d) = -49.796 dB  error(+0.204 dB)
0615     0x0c,       // [101] = -50.500 dB  ->  AKM(0x0c) = -50.491 dB  error(+0.009 dB)
0616     0x0b,       // [102] = -51.000 dB  ->  AKM(0x0b) = -51.247 dB  error(-0.247 dB)
0617     0x0b,       // [103] = -51.500 dB  ->  AKM(0x0b) = -51.247 dB  error(+0.253 dB)
0618     0x0a,       // [104] = -52.000 dB  ->  AKM(0x0a) = -52.075 dB  error(-0.075 dB)
0619     0x0a,       // [105] = -52.500 dB  ->  AKM(0x0a) = -52.075 dB  error(+0.425 dB)
0620     0x09,       // [106] = -53.000 dB  ->  AKM(0x09) = -52.990 dB  error(+0.010 dB)
0621     0x09,       // [107] = -53.500 dB  ->  AKM(0x09) = -52.990 dB  error(+0.510 dB)
0622     0x08,       // [108] = -54.000 dB  ->  AKM(0x08) = -54.013 dB  error(-0.013 dB)
0623     0x08,       // [109] = -54.500 dB  ->  AKM(0x08) = -54.013 dB  error(+0.487 dB)
0624     0x07,       // [110] = -55.000 dB  ->  AKM(0x07) = -55.173 dB  error(-0.173 dB)
0625     0x07,       // [111] = -55.500 dB  ->  AKM(0x07) = -55.173 dB  error(+0.327 dB)
0626     0x06,       // [112] = -56.000 dB  ->  AKM(0x06) = -56.512 dB  error(-0.512 dB)
0627     0x06,       // [113] = -56.500 dB  ->  AKM(0x06) = -56.512 dB  error(-0.012 dB)
0628     0x06,       // [114] = -57.000 dB  ->  AKM(0x06) = -56.512 dB  error(+0.488 dB)
0629     0x05,       // [115] = -57.500 dB  ->  AKM(0x05) = -58.095 dB  error(-0.595 dB)
0630     0x05,       // [116] = -58.000 dB  ->  AKM(0x05) = -58.095 dB  error(-0.095 dB)
0631     0x05,       // [117] = -58.500 dB  ->  AKM(0x05) = -58.095 dB  error(+0.405 dB)
0632     0x05,       // [118] = -59.000 dB  ->  AKM(0x05) = -58.095 dB  error(+0.905 dB)
0633     0x04,       // [119] = -59.500 dB  ->  AKM(0x04) = -60.034 dB  error(-0.534 dB)
0634     0x04,       // [120] = -60.000 dB  ->  AKM(0x04) = -60.034 dB  error(-0.034 dB)
0635     0x04,       // [121] = -60.500 dB  ->  AKM(0x04) = -60.034 dB  error(+0.466 dB)
0636     0x04,       // [122] = -61.000 dB  ->  AKM(0x04) = -60.034 dB  error(+0.966 dB)
0637     0x03,       // [123] = -61.500 dB  ->  AKM(0x03) = -62.532 dB  error(-1.032 dB)
0638     0x03,       // [124] = -62.000 dB  ->  AKM(0x03) = -62.532 dB  error(-0.532 dB)
0639     0x03,       // [125] = -62.500 dB  ->  AKM(0x03) = -62.532 dB  error(-0.032 dB)
0640     0x03,       // [126] = -63.000 dB  ->  AKM(0x03) = -62.532 dB  error(+0.468 dB)
0641     0x03,       // [127] = -63.500 dB  ->  AKM(0x03) = -62.532 dB  error(+0.968 dB)
0642     0x03,       // [128] = -64.000 dB  ->  AKM(0x03) = -62.532 dB  error(+1.468 dB)
0643     0x02,       // [129] = -64.500 dB  ->  AKM(0x02) = -66.054 dB  error(-1.554 dB)
0644     0x02,       // [130] = -65.000 dB  ->  AKM(0x02) = -66.054 dB  error(-1.054 dB)
0645     0x02,       // [131] = -65.500 dB  ->  AKM(0x02) = -66.054 dB  error(-0.554 dB)
0646     0x02,       // [132] = -66.000 dB  ->  AKM(0x02) = -66.054 dB  error(-0.054 dB)
0647     0x02,       // [133] = -66.500 dB  ->  AKM(0x02) = -66.054 dB  error(+0.446 dB)
0648     0x02,       // [134] = -67.000 dB  ->  AKM(0x02) = -66.054 dB  error(+0.946 dB)
0649     0x02,       // [135] = -67.500 dB  ->  AKM(0x02) = -66.054 dB  error(+1.446 dB)
0650     0x02,       // [136] = -68.000 dB  ->  AKM(0x02) = -66.054 dB  error(+1.946 dB)
0651     0x02,       // [137] = -68.500 dB  ->  AKM(0x02) = -66.054 dB  error(+2.446 dB)
0652     0x02,       // [138] = -69.000 dB  ->  AKM(0x02) = -66.054 dB  error(+2.946 dB)
0653     0x01,       // [139] = -69.500 dB  ->  AKM(0x01) = -72.075 dB  error(-2.575 dB)
0654     0x01,       // [140] = -70.000 dB  ->  AKM(0x01) = -72.075 dB  error(-2.075 dB)
0655     0x01,       // [141] = -70.500 dB  ->  AKM(0x01) = -72.075 dB  error(-1.575 dB)
0656     0x01,       // [142] = -71.000 dB  ->  AKM(0x01) = -72.075 dB  error(-1.075 dB)
0657     0x01,       // [143] = -71.500 dB  ->  AKM(0x01) = -72.075 dB  error(-0.575 dB)
0658     0x01,       // [144] = -72.000 dB  ->  AKM(0x01) = -72.075 dB  error(-0.075 dB)
0659     0x01,       // [145] = -72.500 dB  ->  AKM(0x01) = -72.075 dB  error(+0.425 dB)
0660     0x01,       // [146] = -73.000 dB  ->  AKM(0x01) = -72.075 dB  error(+0.925 dB)
0661     0x00};      // [147] = -73.500 dB  ->  AKM(0x00) =  mute       error(+infini)
0662 
0663 /*
0664  * pseudo-codec write entry
0665  */
0666 static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data)
0667 {
0668     unsigned int val;
0669 
0670     if (reg == XX_CODEC_DAC_CONTROL_REGISTER) {
0671         vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD);
0672         return;
0673     }
0674 
0675     /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need
0676        a look up table, as there is no linear matching between the driver codec values
0677        and the real dBu value
0678     */
0679     if (snd_BUG_ON(data >= sizeof(vx2_akm_gains_lut)))
0680         return;
0681 
0682     switch (reg) {
0683     case XX_CODEC_LEVEL_LEFT_REGISTER:
0684         val = AKM_CODEC_LEFT_LEVEL_CMD;
0685         break;
0686     case XX_CODEC_LEVEL_RIGHT_REGISTER:
0687         val = AKM_CODEC_RIGHT_LEVEL_CMD;
0688         break;
0689     default:
0690         snd_BUG();
0691         return;
0692     }
0693     val |= vx2_akm_gains_lut[data];
0694 
0695     vx2_write_codec_reg(chip, val);
0696 }
0697 
0698 
0699 /*
0700  * write codec bit for old VX222 board
0701  */
0702 static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data)
0703 {
0704     int i;
0705 
0706     /* activate access to codec registers */
0707     vx_inl(chip, HIFREQ);
0708 
0709     for (i = 0; i < 24; i++, data <<= 1)
0710         vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
0711 
0712     /* Terminate access to codec registers */
0713     vx_inl(chip, RUER);
0714 }
0715 
0716 
0717 /*
0718  * reset codec bit
0719  */
0720 static void vx2_reset_codec(struct vx_core *_chip)
0721 {
0722     struct snd_vx222 *chip = to_vx222(_chip);
0723 
0724     /* Set the reset CODEC bit to 0. */
0725     vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
0726     vx_inl(chip, CDSP);
0727     msleep(10);
0728     /* Set the reset CODEC bit to 1. */
0729     chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
0730     vx_outl(chip, CDSP, chip->regCDSP);
0731     vx_inl(chip, CDSP);
0732     if (_chip->type == VX_TYPE_BOARD) {
0733         msleep(1);
0734         return;
0735     }
0736 
0737     msleep(5);  /* additionnel wait time for AKM's */
0738 
0739     vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
0740     
0741     vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */
0742     vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */
0743     vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */
0744 
0745     if (_chip->type == VX_TYPE_MIC) {
0746         /* set up the micro input selector */
0747         chip->regSELMIC =  MICRO_SELECT_INPUT_NORM |
0748             MICRO_SELECT_PREAMPLI_G_0 |
0749             MICRO_SELECT_NOISE_T_52DB;
0750 
0751         /* reset phantom power supply */
0752         chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM;
0753 
0754         vx_outl(_chip, SELMIC, chip->regSELMIC);
0755     }
0756 }
0757 
0758 
0759 /*
0760  * change the audio source
0761  */
0762 static void vx2_change_audio_source(struct vx_core *_chip, int src)
0763 {
0764     struct snd_vx222 *chip = to_vx222(_chip);
0765 
0766     switch (src) {
0767     case VX_AUDIO_SRC_DIGITAL:
0768         chip->regCFG |= VX_CFG_DATAIN_SEL_MASK;
0769         break;
0770     default:
0771         chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK;
0772         break;
0773     }
0774     vx_outl(chip, CFG, chip->regCFG);
0775 }
0776 
0777 
0778 /*
0779  * set the clock source
0780  */
0781 static void vx2_set_clock_source(struct vx_core *_chip, int source)
0782 {
0783     struct snd_vx222 *chip = to_vx222(_chip);
0784 
0785     if (source == INTERNAL_QUARTZ)
0786         chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK;
0787     else
0788         chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK;
0789     vx_outl(chip, CFG, chip->regCFG);
0790 }
0791 
0792 /*
0793  * reset the board
0794  */
0795 static void vx2_reset_board(struct vx_core *_chip, int cold_reset)
0796 {
0797     struct snd_vx222 *chip = to_vx222(_chip);
0798 
0799     /* initialize the register values */
0800     chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ;
0801     chip->regCFG = 0;
0802 }
0803 
0804 
0805 
0806 /*
0807  * input level controls for VX222 Mic
0808  */
0809 
0810 /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318),
0811  * 318 = 210 + 36 + 36 + 36   (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli)
0812  * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset !
0813  */
0814 #define V2_MICRO_LEVEL_RANGE        (318 - 255)
0815 
0816 static void vx2_set_input_level(struct snd_vx222 *chip)
0817 {
0818     int i, miclevel, preamp;
0819     unsigned int data;
0820 
0821     miclevel = chip->mic_level;
0822     miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */
0823     preamp = 0;
0824         while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */
0825         preamp++;   /* raise pre ampli + 18dB */
0826         miclevel -= (18 * 2);   /* lower level 18 dB (*2 because of 0.5 dB steps !) */
0827         }
0828     if (snd_BUG_ON(preamp >= 4))
0829         return;
0830 
0831     /* set pre-amp level */
0832     chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK;
0833     chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK;
0834     vx_outl(chip, SELMIC, chip->regSELMIC);
0835 
0836     data = (unsigned int)miclevel << 16 |
0837         (unsigned int)chip->input_level[1] << 8 |
0838         (unsigned int)chip->input_level[0];
0839     vx_inl(chip, DATA); /* Activate input level programming */
0840 
0841     /* We have to send 32 bits (4 x 8 bits) */
0842     for (i = 0; i < 32; i++, data <<= 1)
0843         vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0));
0844 
0845     vx_inl(chip, RUER); /* Terminate input level programming */
0846 }
0847 
0848 
0849 #define MIC_LEVEL_MAX   0xff
0850 
0851 static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0);
0852 
0853 /*
0854  * controls API for input levels
0855  */
0856 
0857 /* input levels */
0858 static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0859 {
0860     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0861     uinfo->count = 2;
0862     uinfo->value.integer.min = 0;
0863     uinfo->value.integer.max = MIC_LEVEL_MAX;
0864     return 0;
0865 }
0866 
0867 static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0868 {
0869     struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
0870     struct snd_vx222 *chip = to_vx222(_chip);
0871     mutex_lock(&_chip->mixer_mutex);
0872     ucontrol->value.integer.value[0] = chip->input_level[0];
0873     ucontrol->value.integer.value[1] = chip->input_level[1];
0874     mutex_unlock(&_chip->mixer_mutex);
0875     return 0;
0876 }
0877 
0878 static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0879 {
0880     struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
0881     struct snd_vx222 *chip = to_vx222(_chip);
0882     if (ucontrol->value.integer.value[0] < 0 ||
0883         ucontrol->value.integer.value[0] > MIC_LEVEL_MAX)
0884         return -EINVAL;
0885     if (ucontrol->value.integer.value[1] < 0 ||
0886         ucontrol->value.integer.value[1] > MIC_LEVEL_MAX)
0887         return -EINVAL;
0888     mutex_lock(&_chip->mixer_mutex);
0889     if (chip->input_level[0] != ucontrol->value.integer.value[0] ||
0890         chip->input_level[1] != ucontrol->value.integer.value[1]) {
0891         chip->input_level[0] = ucontrol->value.integer.value[0];
0892         chip->input_level[1] = ucontrol->value.integer.value[1];
0893         vx2_set_input_level(chip);
0894         mutex_unlock(&_chip->mixer_mutex);
0895         return 1;
0896     }
0897     mutex_unlock(&_chip->mixer_mutex);
0898     return 0;
0899 }
0900 
0901 /* mic level */
0902 static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0903 {
0904     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0905     uinfo->count = 1;
0906     uinfo->value.integer.min = 0;
0907     uinfo->value.integer.max = MIC_LEVEL_MAX;
0908     return 0;
0909 }
0910 
0911 static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0912 {
0913     struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
0914     struct snd_vx222 *chip = to_vx222(_chip);
0915     ucontrol->value.integer.value[0] = chip->mic_level;
0916     return 0;
0917 }
0918 
0919 static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0920 {
0921     struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
0922     struct snd_vx222 *chip = to_vx222(_chip);
0923     if (ucontrol->value.integer.value[0] < 0 ||
0924         ucontrol->value.integer.value[0] > MIC_LEVEL_MAX)
0925         return -EINVAL;
0926     mutex_lock(&_chip->mixer_mutex);
0927     if (chip->mic_level != ucontrol->value.integer.value[0]) {
0928         chip->mic_level = ucontrol->value.integer.value[0];
0929         vx2_set_input_level(chip);
0930         mutex_unlock(&_chip->mixer_mutex);
0931         return 1;
0932     }
0933     mutex_unlock(&_chip->mixer_mutex);
0934     return 0;
0935 }
0936 
0937 static const struct snd_kcontrol_new vx_control_input_level = {
0938     .iface =    SNDRV_CTL_ELEM_IFACE_MIXER,
0939     .access =   (SNDRV_CTL_ELEM_ACCESS_READWRITE |
0940              SNDRV_CTL_ELEM_ACCESS_TLV_READ),
0941     .name =     "Capture Volume",
0942     .info =     vx_input_level_info,
0943     .get =      vx_input_level_get,
0944     .put =      vx_input_level_put,
0945     .tlv = { .p = db_scale_mic },
0946 };
0947 
0948 static const struct snd_kcontrol_new vx_control_mic_level = {
0949     .iface =    SNDRV_CTL_ELEM_IFACE_MIXER,
0950     .access =   (SNDRV_CTL_ELEM_ACCESS_READWRITE |
0951              SNDRV_CTL_ELEM_ACCESS_TLV_READ),
0952     .name =     "Mic Capture Volume",
0953     .info =     vx_mic_level_info,
0954     .get =      vx_mic_level_get,
0955     .put =      vx_mic_level_put,
0956     .tlv = { .p = db_scale_mic },
0957 };
0958 
0959 /*
0960  * FIXME: compressor/limiter implementation is missing yet...
0961  */
0962 
0963 static int vx2_add_mic_controls(struct vx_core *_chip)
0964 {
0965     struct snd_vx222 *chip = to_vx222(_chip);
0966     int err;
0967 
0968     if (_chip->type != VX_TYPE_MIC)
0969         return 0;
0970 
0971     /* mute input levels */
0972     chip->input_level[0] = chip->input_level[1] = 0;
0973     chip->mic_level = 0;
0974     vx2_set_input_level(chip);
0975 
0976     /* controls */
0977     err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip));
0978     if (err < 0)
0979         return err;
0980     err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip));
0981     if (err < 0)
0982         return err;
0983 
0984     return 0;
0985 }
0986 
0987 
0988 /*
0989  * callbacks
0990  */
0991 const struct snd_vx_ops vx222_ops = {
0992     .in8 = vx2_inb,
0993     .in32 = vx2_inl,
0994     .out8 = vx2_outb,
0995     .out32 = vx2_outl,
0996     .test_and_ack = vx2_test_and_ack,
0997     .validate_irq = vx2_validate_irq,
0998     .akm_write = vx2_write_akm,
0999     .reset_codec = vx2_reset_codec,
1000     .change_audio_source = vx2_change_audio_source,
1001     .set_clock_source = vx2_set_clock_source,
1002     .load_dsp = vx2_load_dsp,
1003     .reset_dsp = vx2_reset_dsp,
1004     .reset_board = vx2_reset_board,
1005     .dma_write = vx2_dma_write,
1006     .dma_read = vx2_dma_read,
1007     .add_controls = vx2_add_mic_controls,
1008 };
1009 
1010 /* for old VX222 board */
1011 const struct snd_vx_ops vx222_old_ops = {
1012     .in8 = vx2_inb,
1013     .in32 = vx2_inl,
1014     .out8 = vx2_outb,
1015     .out32 = vx2_outl,
1016     .test_and_ack = vx2_test_and_ack,
1017     .validate_irq = vx2_validate_irq,
1018     .write_codec = vx2_old_write_codec_bit,
1019     .reset_codec = vx2_reset_codec,
1020     .change_audio_source = vx2_change_audio_source,
1021     .set_clock_source = vx2_set_clock_source,
1022     .load_dsp = vx2_load_dsp,
1023     .reset_dsp = vx2_reset_dsp,
1024     .reset_board = vx2_reset_board,
1025     .dma_write = vx2_dma_write,
1026     .dma_read = vx2_dma_read,
1027 };
1028
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