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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *   ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
0004  *
0005  *      Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
0006  *                              Pilo Chambert <pilo.c@wanadoo.fr>
0007  *
0008  *      Thanks to :        Anders Torger <torger@ludd.luth.se>,
0009  *                         Henk Hesselink <henk@anda.nl>
0010  *                         for writing the digi96-driver 
0011  *                         and RME for all informations.
0012  * 
0013  * ****************************************************************************
0014  * 
0015  * Note #1 "Sek'd models" ................................... martin 2002-12-07
0016  * 
0017  * Identical soundcards by Sek'd were labeled:
0018  * RME Digi 32     = Sek'd Prodif 32
0019  * RME Digi 32 Pro = Sek'd Prodif 96
0020  * RME Digi 32/8   = Sek'd Prodif Gold
0021  * 
0022  * ****************************************************************************
0023  * 
0024  * Note #2 "full duplex mode" ............................... martin 2002-12-07
0025  * 
0026  * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
0027  * in this mode. Rec data and play data are using the same buffer therefore. At
0028  * first you have got the playing bits in the buffer and then (after playing
0029  * them) they were overwitten by the captured sound of the CS8412/14. Both 
0030  * modes (play/record) are running harmonically hand in hand in the same buffer
0031  * and you have only one start bit plus one interrupt bit to control this 
0032  * paired action.
0033  * This is opposite to the latter rme96 where playing and capturing is totally
0034  * separated and so their full duplex mode is supported by alsa (using two 
0035  * start bits and two interrupts for two different buffers). 
0036  * But due to the wrong sequence of playing and capturing ALSA shows no solved
0037  * full duplex support for the rme32 at the moment. That's bad, but I'm not
0038  * able to solve it. Are you motivated enough to solve this problem now? Your
0039  * patch would be welcome!
0040  * 
0041  * ****************************************************************************
0042  *
0043  * "The story after the long seeking" -- tiwai
0044  *
0045  * Ok, the situation regarding the full duplex is now improved a bit.
0046  * In the fullduplex mode (given by the module parameter), the hardware buffer
0047  * is split to halves for read and write directions at the DMA pointer.
0048  * That is, the half above the current DMA pointer is used for write, and
0049  * the half below is used for read.  To mangle this strange behavior, an
0050  * software intermediate buffer is introduced.  This is, of course, not good
0051  * from the viewpoint of the data transfer efficiency.  However, this allows
0052  * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
0053  *
0054  * ****************************************************************************
0055  */
0056 
0057 
0058 #include <linux/delay.h>
0059 #include <linux/gfp.h>
0060 #include <linux/init.h>
0061 #include <linux/interrupt.h>
0062 #include <linux/pci.h>
0063 #include <linux/module.h>
0064 #include <linux/io.h>
0065 
0066 #include <sound/core.h>
0067 #include <sound/info.h>
0068 #include <sound/control.h>
0069 #include <sound/pcm.h>
0070 #include <sound/pcm_params.h>
0071 #include <sound/pcm-indirect.h>
0072 #include <sound/asoundef.h>
0073 #include <sound/initval.h>
0074 
0075 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;  /* Index 0-MAX */
0076 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;   /* ID for this card */
0077 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
0078 static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
0079 
0080 module_param_array(index, int, NULL, 0444);
0081 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
0082 module_param_array(id, charp, NULL, 0444);
0083 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
0084 module_param_array(enable, bool, NULL, 0444);
0085 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
0086 module_param_array(fullduplex, bool, NULL, 0444);
0087 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
0088 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
0089 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
0090 MODULE_LICENSE("GPL");
0091 
0092 /* Defines for RME Digi32 series */
0093 #define RME32_SPDIF_NCHANNELS 2
0094 
0095 /* Playback and capture buffer size */
0096 #define RME32_BUFFER_SIZE 0x20000
0097 
0098 /* IO area size */
0099 #define RME32_IO_SIZE 0x30000
0100 
0101 /* IO area offsets */
0102 #define RME32_IO_DATA_BUFFER        0x0
0103 #define RME32_IO_CONTROL_REGISTER   0x20000
0104 #define RME32_IO_GET_POS            0x20000
0105 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
0106 #define RME32_IO_RESET_POS          0x20100
0107 
0108 /* Write control register bits */
0109 #define RME32_WCR_START     (1 << 0)    /* startbit */
0110 #define RME32_WCR_MONO      (1 << 1)    /* 0=stereo, 1=mono
0111                                            Setting the whole card to mono
0112                                            doesn't seem to be very useful.
0113                                            A software-solution can handle 
0114                                            full-duplex with one direction in
0115                                            stereo and the other way in mono. 
0116                                            So, the hardware should work all 
0117                                            the time in stereo! */
0118 #define RME32_WCR_MODE24    (1 << 2)    /* 0=16bit, 1=32bit */
0119 #define RME32_WCR_SEL       (1 << 3)    /* 0=input on output, 1=normal playback/capture */
0120 #define RME32_WCR_FREQ_0    (1 << 4)    /* frequency (play) */
0121 #define RME32_WCR_FREQ_1    (1 << 5)
0122 #define RME32_WCR_INP_0     (1 << 6)    /* input switch */
0123 #define RME32_WCR_INP_1     (1 << 7)
0124 #define RME32_WCR_RESET     (1 << 8)    /* Reset address */
0125 #define RME32_WCR_MUTE      (1 << 9)    /* digital mute for output */
0126 #define RME32_WCR_PRO       (1 << 10)   /* 1=professional, 0=consumer */
0127 #define RME32_WCR_DS_BM     (1 << 11)   /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
0128 #define RME32_WCR_ADAT      (1 << 12)   /* Adat Mode (only Adat-Version) */
0129 #define RME32_WCR_AUTOSYNC  (1 << 13)   /* AutoSync */
0130 #define RME32_WCR_PD        (1 << 14)   /* DAC Reset (only PRO-Version) */
0131 #define RME32_WCR_EMP       (1 << 15)   /* 1=Emphasis on (only PRO-Version) */
0132 
0133 #define RME32_WCR_BITPOS_FREQ_0 4
0134 #define RME32_WCR_BITPOS_FREQ_1 5
0135 #define RME32_WCR_BITPOS_INP_0 6
0136 #define RME32_WCR_BITPOS_INP_1 7
0137 
0138 /* Read control register bits */
0139 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
0140 #define RME32_RCR_LOCK      (1 << 23)   /* 1=locked, 0=not locked */
0141 #define RME32_RCR_ERF       (1 << 26)   /* 1=Error, 0=no Error */
0142 #define RME32_RCR_FREQ_0    (1 << 27)   /* CS841x frequency (record) */
0143 #define RME32_RCR_FREQ_1    (1 << 28)
0144 #define RME32_RCR_FREQ_2    (1 << 29)
0145 #define RME32_RCR_KMODE     (1 << 30)   /* card mode: 1=PLL, 0=quartz */
0146 #define RME32_RCR_IRQ       (1 << 31)   /* interrupt */
0147 
0148 #define RME32_RCR_BITPOS_F0 27
0149 #define RME32_RCR_BITPOS_F1 28
0150 #define RME32_RCR_BITPOS_F2 29
0151 
0152 /* Input types */
0153 #define RME32_INPUT_OPTICAL 0
0154 #define RME32_INPUT_COAXIAL 1
0155 #define RME32_INPUT_INTERNAL 2
0156 #define RME32_INPUT_XLR 3
0157 
0158 /* Clock modes */
0159 #define RME32_CLOCKMODE_SLAVE 0
0160 #define RME32_CLOCKMODE_MASTER_32 1
0161 #define RME32_CLOCKMODE_MASTER_44 2
0162 #define RME32_CLOCKMODE_MASTER_48 3
0163 
0164 /* Block sizes in bytes */
0165 #define RME32_BLOCK_SIZE 8192
0166 
0167 /* Software intermediate buffer (max) size */
0168 #define RME32_MID_BUFFER_SIZE (1024*1024)
0169 
0170 /* Hardware revisions */
0171 #define RME32_32_REVISION 192
0172 #define RME32_328_REVISION_OLD 100
0173 #define RME32_328_REVISION_NEW 101
0174 #define RME32_PRO_REVISION_WITH_8412 192
0175 #define RME32_PRO_REVISION_WITH_8414 150
0176 
0177 
0178 struct rme32 {
0179     spinlock_t lock;
0180     int irq;
0181     unsigned long port;
0182     void __iomem *iobase;
0183 
0184     u32 wcreg;      /* cached write control register value */
0185     u32 wcreg_spdif;    /* S/PDIF setup */
0186     u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
0187     u32 rcreg;      /* cached read control register value */
0188 
0189     u8 rev;         /* card revision number */
0190 
0191     struct snd_pcm_substream *playback_substream;
0192     struct snd_pcm_substream *capture_substream;
0193 
0194     int playback_frlog; /* log2 of framesize */
0195     int capture_frlog;
0196 
0197     size_t playback_periodsize; /* in bytes, zero if not used */
0198     size_t capture_periodsize;  /* in bytes, zero if not used */
0199 
0200     unsigned int fullduplex_mode;
0201     int running;
0202 
0203     struct snd_pcm_indirect playback_pcm;
0204     struct snd_pcm_indirect capture_pcm;
0205 
0206     struct snd_card *card;
0207     struct snd_pcm *spdif_pcm;
0208     struct snd_pcm *adat_pcm;
0209     struct pci_dev *pci;
0210     struct snd_kcontrol *spdif_ctl;
0211 };
0212 
0213 static const struct pci_device_id snd_rme32_ids[] = {
0214     {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
0215     {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
0216     {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
0217     {0,}
0218 };
0219 
0220 MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
0221 
0222 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
0223 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
0224 
0225 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
0226 
0227 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
0228 
0229 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
0230 
0231 static void snd_rme32_proc_init(struct rme32 * rme32);
0232 
0233 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
0234 
0235 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
0236 {
0237     return (readl(rme32->iobase + RME32_IO_GET_POS)
0238         & RME32_RCR_AUDIO_ADDR_MASK);
0239 }
0240 
0241 /* silence callback for halfduplex mode */
0242 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream,
0243                       int channel, unsigned long pos,
0244                       unsigned long count)
0245 {
0246     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0247 
0248     memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
0249     return 0;
0250 }
0251 
0252 /* copy callback for halfduplex mode */
0253 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream,
0254                    int channel, unsigned long pos,
0255                    void __user *src, unsigned long count)
0256 {
0257     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0258 
0259     if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
0260                 src, count))
0261         return -EFAULT;
0262     return 0;
0263 }
0264 
0265 static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream,
0266                       int channel, unsigned long pos,
0267                       void *src, unsigned long count)
0268 {
0269     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0270 
0271     memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count);
0272     return 0;
0273 }
0274 
0275 /* copy callback for halfduplex mode */
0276 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream,
0277                   int channel, unsigned long pos,
0278                   void __user *dst, unsigned long count)
0279 {
0280     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0281 
0282     if (copy_to_user_fromio(dst,
0283                 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
0284                 count))
0285         return -EFAULT;
0286     return 0;
0287 }
0288 
0289 static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream,
0290                      int channel, unsigned long pos,
0291                      void *dst, unsigned long count)
0292 {
0293     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0294 
0295     memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count);
0296     return 0;
0297 }
0298 
0299 /*
0300  * SPDIF I/O capabilities (half-duplex mode)
0301  */
0302 static const struct snd_pcm_hardware snd_rme32_spdif_info = {
0303     .info =     (SNDRV_PCM_INFO_MMAP_IOMEM |
0304              SNDRV_PCM_INFO_MMAP_VALID |
0305              SNDRV_PCM_INFO_INTERLEAVED | 
0306              SNDRV_PCM_INFO_PAUSE |
0307              SNDRV_PCM_INFO_SYNC_START |
0308              SNDRV_PCM_INFO_SYNC_APPLPTR),
0309     .formats =  (SNDRV_PCM_FMTBIT_S16_LE | 
0310              SNDRV_PCM_FMTBIT_S32_LE),
0311     .rates =    (SNDRV_PCM_RATE_32000 |
0312              SNDRV_PCM_RATE_44100 | 
0313              SNDRV_PCM_RATE_48000),
0314     .rate_min = 32000,
0315     .rate_max = 48000,
0316     .channels_min = 2,
0317     .channels_max = 2,
0318     .buffer_bytes_max = RME32_BUFFER_SIZE,
0319     .period_bytes_min = RME32_BLOCK_SIZE,
0320     .period_bytes_max = RME32_BLOCK_SIZE,
0321     .periods_min =  RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
0322     .periods_max =  RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
0323     .fifo_size =    0,
0324 };
0325 
0326 /*
0327  * ADAT I/O capabilities (half-duplex mode)
0328  */
0329 static const struct snd_pcm_hardware snd_rme32_adat_info =
0330 {
0331     .info =          (SNDRV_PCM_INFO_MMAP_IOMEM |
0332                   SNDRV_PCM_INFO_MMAP_VALID |
0333                   SNDRV_PCM_INFO_INTERLEAVED |
0334                   SNDRV_PCM_INFO_PAUSE |
0335                   SNDRV_PCM_INFO_SYNC_START |
0336                   SNDRV_PCM_INFO_SYNC_APPLPTR),
0337     .formats=            SNDRV_PCM_FMTBIT_S16_LE,
0338     .rates =             (SNDRV_PCM_RATE_44100 | 
0339                   SNDRV_PCM_RATE_48000),
0340     .rate_min =          44100,
0341     .rate_max =          48000,
0342     .channels_min =      8,
0343     .channels_max =      8,
0344     .buffer_bytes_max =  RME32_BUFFER_SIZE,
0345     .period_bytes_min =  RME32_BLOCK_SIZE,
0346     .period_bytes_max =  RME32_BLOCK_SIZE,
0347     .periods_min =      RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
0348     .periods_max =      RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
0349     .fifo_size =        0,
0350 };
0351 
0352 /*
0353  * SPDIF I/O capabilities (full-duplex mode)
0354  */
0355 static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
0356     .info =     (SNDRV_PCM_INFO_MMAP |
0357              SNDRV_PCM_INFO_MMAP_VALID |
0358              SNDRV_PCM_INFO_INTERLEAVED | 
0359              SNDRV_PCM_INFO_PAUSE |
0360              SNDRV_PCM_INFO_SYNC_START |
0361              SNDRV_PCM_INFO_SYNC_APPLPTR),
0362     .formats =  (SNDRV_PCM_FMTBIT_S16_LE | 
0363              SNDRV_PCM_FMTBIT_S32_LE),
0364     .rates =    (SNDRV_PCM_RATE_32000 |
0365              SNDRV_PCM_RATE_44100 | 
0366              SNDRV_PCM_RATE_48000),
0367     .rate_min = 32000,
0368     .rate_max = 48000,
0369     .channels_min = 2,
0370     .channels_max = 2,
0371     .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
0372     .period_bytes_min = RME32_BLOCK_SIZE,
0373     .period_bytes_max = RME32_BLOCK_SIZE,
0374     .periods_min =  2,
0375     .periods_max =  RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
0376     .fifo_size =    0,
0377 };
0378 
0379 /*
0380  * ADAT I/O capabilities (full-duplex mode)
0381  */
0382 static const struct snd_pcm_hardware snd_rme32_adat_fd_info =
0383 {
0384     .info =          (SNDRV_PCM_INFO_MMAP |
0385                   SNDRV_PCM_INFO_MMAP_VALID |
0386                   SNDRV_PCM_INFO_INTERLEAVED |
0387                   SNDRV_PCM_INFO_PAUSE |
0388                   SNDRV_PCM_INFO_SYNC_START |
0389                   SNDRV_PCM_INFO_SYNC_APPLPTR),
0390     .formats=            SNDRV_PCM_FMTBIT_S16_LE,
0391     .rates =             (SNDRV_PCM_RATE_44100 | 
0392                   SNDRV_PCM_RATE_48000),
0393     .rate_min =          44100,
0394     .rate_max =          48000,
0395     .channels_min =      8,
0396     .channels_max =      8,
0397     .buffer_bytes_max =  RME32_MID_BUFFER_SIZE,
0398     .period_bytes_min =  RME32_BLOCK_SIZE,
0399     .period_bytes_max =  RME32_BLOCK_SIZE,
0400     .periods_min =      2,
0401     .periods_max =      RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
0402     .fifo_size =        0,
0403 };
0404 
0405 static void snd_rme32_reset_dac(struct rme32 *rme32)
0406 {
0407         writel(rme32->wcreg | RME32_WCR_PD,
0408                rme32->iobase + RME32_IO_CONTROL_REGISTER);
0409         writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0410 }
0411 
0412 static int snd_rme32_playback_getrate(struct rme32 * rme32)
0413 {
0414     int rate;
0415 
0416     rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
0417            (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
0418     switch (rate) {
0419     case 1:
0420         rate = 32000;
0421         break;
0422     case 2:
0423         rate = 44100;
0424         break;
0425     case 3:
0426         rate = 48000;
0427         break;
0428     default:
0429         return -1;
0430     }
0431     return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
0432 }
0433 
0434 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
0435 {
0436     int n;
0437 
0438     *is_adat = 0;
0439     if (rme32->rcreg & RME32_RCR_LOCK) { 
0440                 /* ADAT rate */
0441                 *is_adat = 1;
0442     }
0443     if (rme32->rcreg & RME32_RCR_ERF) {
0444         return -1;
0445     }
0446 
0447         /* S/PDIF rate */
0448     n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
0449         (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
0450         (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
0451 
0452     if (RME32_PRO_WITH_8414(rme32))
0453         switch (n) {    /* supporting the CS8414 */
0454         case 0:
0455         case 1:
0456         case 2:
0457             return -1;
0458         case 3:
0459             return 96000;
0460         case 4:
0461             return 88200;
0462         case 5:
0463             return 48000;
0464         case 6:
0465             return 44100;
0466         case 7:
0467             return 32000;
0468         default:
0469             return -1;
0470         } 
0471     else
0472         switch (n) {    /* supporting the CS8412 */
0473         case 0:
0474             return -1;
0475         case 1:
0476             return 48000;
0477         case 2:
0478             return 44100;
0479         case 3:
0480             return 32000;
0481         case 4:
0482             return 48000;
0483         case 5:
0484             return 44100;
0485         case 6:
0486             return 44056;
0487         case 7:
0488             return 32000;
0489         default:
0490             break;
0491         }
0492     return -1;
0493 }
0494 
0495 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
0496 {
0497         int ds;
0498 
0499         ds = rme32->wcreg & RME32_WCR_DS_BM;
0500     switch (rate) {
0501     case 32000:
0502         rme32->wcreg &= ~RME32_WCR_DS_BM;
0503         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
0504             ~RME32_WCR_FREQ_1;
0505         break;
0506     case 44100:
0507         rme32->wcreg &= ~RME32_WCR_DS_BM;
0508         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 
0509             ~RME32_WCR_FREQ_0;
0510         break;
0511     case 48000:
0512         rme32->wcreg &= ~RME32_WCR_DS_BM;
0513         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
0514             RME32_WCR_FREQ_1;
0515         break;
0516     case 64000:
0517         if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
0518             return -EINVAL;
0519         rme32->wcreg |= RME32_WCR_DS_BM;
0520         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
0521             ~RME32_WCR_FREQ_1;
0522         break;
0523     case 88200:
0524         if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
0525             return -EINVAL;
0526         rme32->wcreg |= RME32_WCR_DS_BM;
0527         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 
0528             ~RME32_WCR_FREQ_0;
0529         break;
0530     case 96000:
0531         if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
0532             return -EINVAL;
0533         rme32->wcreg |= RME32_WCR_DS_BM;
0534         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
0535             RME32_WCR_FREQ_1;
0536         break;
0537     default:
0538         return -EINVAL;
0539     }
0540         if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
0541             (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
0542         {
0543                 /* change to/from double-speed: reset the DAC (if available) */
0544                 snd_rme32_reset_dac(rme32);
0545         } else {
0546                 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0547     }
0548     return 0;
0549 }
0550 
0551 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
0552 {
0553     switch (mode) {
0554     case RME32_CLOCKMODE_SLAVE:
0555         /* AutoSync */
0556         rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & 
0557             ~RME32_WCR_FREQ_1;
0558         break;
0559     case RME32_CLOCKMODE_MASTER_32:
0560         /* Internal 32.0kHz */
0561         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
0562             ~RME32_WCR_FREQ_1;
0563         break;
0564     case RME32_CLOCKMODE_MASTER_44:
0565         /* Internal 44.1kHz */
0566         rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | 
0567             RME32_WCR_FREQ_1;
0568         break;
0569     case RME32_CLOCKMODE_MASTER_48:
0570         /* Internal 48.0kHz */
0571         rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
0572             RME32_WCR_FREQ_1;
0573         break;
0574     default:
0575         return -EINVAL;
0576     }
0577     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0578     return 0;
0579 }
0580 
0581 static int snd_rme32_getclockmode(struct rme32 * rme32)
0582 {
0583     return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
0584         (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
0585 }
0586 
0587 static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
0588 {
0589     switch (type) {
0590     case RME32_INPUT_OPTICAL:
0591         rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & 
0592             ~RME32_WCR_INP_1;
0593         break;
0594     case RME32_INPUT_COAXIAL:
0595         rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & 
0596             ~RME32_WCR_INP_1;
0597         break;
0598     case RME32_INPUT_INTERNAL:
0599         rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | 
0600             RME32_WCR_INP_1;
0601         break;
0602     case RME32_INPUT_XLR:
0603         rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | 
0604             RME32_WCR_INP_1;
0605         break;
0606     default:
0607         return -EINVAL;
0608     }
0609     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0610     return 0;
0611 }
0612 
0613 static int snd_rme32_getinputtype(struct rme32 * rme32)
0614 {
0615     return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
0616         (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
0617 }
0618 
0619 static void
0620 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
0621 {
0622     int frlog;
0623 
0624     if (n_channels == 2) {
0625         frlog = 1;
0626     } else {
0627         /* assume 8 channels */
0628         frlog = 3;
0629     }
0630     if (is_playback) {
0631         frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
0632         rme32->playback_frlog = frlog;
0633     } else {
0634         frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
0635         rme32->capture_frlog = frlog;
0636     }
0637 }
0638 
0639 static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
0640 {
0641     switch (format) {
0642     case SNDRV_PCM_FORMAT_S16_LE:
0643         rme32->wcreg &= ~RME32_WCR_MODE24;
0644         break;
0645     case SNDRV_PCM_FORMAT_S32_LE:
0646         rme32->wcreg |= RME32_WCR_MODE24;
0647         break;
0648     default:
0649         return -EINVAL;
0650     }
0651     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0652     return 0;
0653 }
0654 
0655 static int
0656 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
0657                  struct snd_pcm_hw_params *params)
0658 {
0659     int err, rate, dummy;
0660     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0661     struct snd_pcm_runtime *runtime = substream->runtime;
0662 
0663     if (!rme32->fullduplex_mode) {
0664         runtime->dma_area = (void __force *)(rme32->iobase +
0665                              RME32_IO_DATA_BUFFER);
0666         runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
0667         runtime->dma_bytes = RME32_BUFFER_SIZE;
0668     }
0669 
0670     spin_lock_irq(&rme32->lock);
0671     rate = 0;
0672     if (rme32->rcreg & RME32_RCR_KMODE)
0673         rate = snd_rme32_capture_getrate(rme32, &dummy);
0674     if (rate > 0) {
0675         /* AutoSync */
0676         if ((int)params_rate(params) != rate) {
0677             spin_unlock_irq(&rme32->lock);
0678             return -EIO;
0679         }
0680     } else {
0681         err = snd_rme32_playback_setrate(rme32, params_rate(params));
0682         if (err < 0) {
0683             spin_unlock_irq(&rme32->lock);
0684             return err;
0685         }
0686     }
0687     err = snd_rme32_setformat(rme32, params_format(params));
0688     if (err < 0) {
0689         spin_unlock_irq(&rme32->lock);
0690         return err;
0691     }
0692 
0693     snd_rme32_setframelog(rme32, params_channels(params), 1);
0694     if (rme32->capture_periodsize != 0) {
0695         if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
0696             spin_unlock_irq(&rme32->lock);
0697             return -EBUSY;
0698         }
0699     }
0700     rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
0701     /* S/PDIF setup */
0702     if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
0703         rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
0704         rme32->wcreg |= rme32->wcreg_spdif_stream;
0705         writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0706     }
0707     spin_unlock_irq(&rme32->lock);
0708 
0709     return 0;
0710 }
0711 
0712 static int
0713 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
0714                 struct snd_pcm_hw_params *params)
0715 {
0716     int err, isadat, rate;
0717     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0718     struct snd_pcm_runtime *runtime = substream->runtime;
0719 
0720     if (!rme32->fullduplex_mode) {
0721         runtime->dma_area = (void __force *)rme32->iobase +
0722                     RME32_IO_DATA_BUFFER;
0723         runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
0724         runtime->dma_bytes = RME32_BUFFER_SIZE;
0725     }
0726 
0727     spin_lock_irq(&rme32->lock);
0728     /* enable AutoSync for record-preparing */
0729     rme32->wcreg |= RME32_WCR_AUTOSYNC;
0730     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0731 
0732     err = snd_rme32_setformat(rme32, params_format(params));
0733     if (err < 0) {
0734         spin_unlock_irq(&rme32->lock);
0735         return err;
0736     }
0737     err = snd_rme32_playback_setrate(rme32, params_rate(params));
0738     if (err < 0) {
0739         spin_unlock_irq(&rme32->lock);
0740         return err;
0741     }
0742     rate = snd_rme32_capture_getrate(rme32, &isadat);
0743     if (rate > 0) {
0744                 if ((int)params_rate(params) != rate) {
0745             spin_unlock_irq(&rme32->lock);
0746                         return -EIO;                    
0747                 }
0748                 if ((isadat && runtime->hw.channels_min == 2) ||
0749                     (!isadat && runtime->hw.channels_min == 8)) {
0750             spin_unlock_irq(&rme32->lock);
0751                         return -EIO;
0752                 }
0753     }
0754     /* AutoSync off for recording */
0755     rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
0756     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0757 
0758     snd_rme32_setframelog(rme32, params_channels(params), 0);
0759     if (rme32->playback_periodsize != 0) {
0760         if (params_period_size(params) << rme32->capture_frlog !=
0761             rme32->playback_periodsize) {
0762             spin_unlock_irq(&rme32->lock);
0763             return -EBUSY;
0764         }
0765     }
0766     rme32->capture_periodsize =
0767         params_period_size(params) << rme32->capture_frlog;
0768     spin_unlock_irq(&rme32->lock);
0769 
0770     return 0;
0771 }
0772 
0773 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
0774 {
0775     if (!from_pause) {
0776         writel(0, rme32->iobase + RME32_IO_RESET_POS);
0777     }
0778 
0779     rme32->wcreg |= RME32_WCR_START;
0780     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0781 }
0782 
0783 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
0784 {
0785     /*
0786      * Check if there is an unconfirmed IRQ, if so confirm it, or else
0787      * the hardware will not stop generating interrupts
0788      */
0789     rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
0790     if (rme32->rcreg & RME32_RCR_IRQ) {
0791         writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
0792     }
0793     rme32->wcreg &= ~RME32_WCR_START;
0794     if (rme32->wcreg & RME32_WCR_SEL)
0795         rme32->wcreg |= RME32_WCR_MUTE;
0796     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0797     if (! to_pause)
0798         writel(0, rme32->iobase + RME32_IO_RESET_POS);
0799 }
0800 
0801 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
0802 {
0803     struct rme32 *rme32 = (struct rme32 *) dev_id;
0804 
0805     rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
0806     if (!(rme32->rcreg & RME32_RCR_IRQ)) {
0807         return IRQ_NONE;
0808     } else {
0809         if (rme32->capture_substream) {
0810             snd_pcm_period_elapsed(rme32->capture_substream);
0811         }
0812         if (rme32->playback_substream) {
0813             snd_pcm_period_elapsed(rme32->playback_substream);
0814         }
0815         writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
0816     }
0817     return IRQ_HANDLED;
0818 }
0819 
0820 static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
0821 
0822 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
0823     .count = ARRAY_SIZE(period_bytes),
0824     .list = period_bytes,
0825     .mask = 0
0826 };
0827 
0828 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
0829 {
0830     if (! rme32->fullduplex_mode) {
0831         snd_pcm_hw_constraint_single(runtime,
0832                          SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
0833                          RME32_BUFFER_SIZE);
0834         snd_pcm_hw_constraint_list(runtime, 0,
0835                        SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
0836                        &hw_constraints_period_bytes);
0837     }
0838 }
0839 
0840 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
0841 {
0842     int rate, dummy;
0843     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0844     struct snd_pcm_runtime *runtime = substream->runtime;
0845 
0846     snd_pcm_set_sync(substream);
0847 
0848     spin_lock_irq(&rme32->lock);
0849     if (rme32->playback_substream != NULL) {
0850         spin_unlock_irq(&rme32->lock);
0851         return -EBUSY;
0852     }
0853     rme32->wcreg &= ~RME32_WCR_ADAT;
0854     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0855     rme32->playback_substream = substream;
0856     spin_unlock_irq(&rme32->lock);
0857 
0858     if (rme32->fullduplex_mode)
0859         runtime->hw = snd_rme32_spdif_fd_info;
0860     else
0861         runtime->hw = snd_rme32_spdif_info;
0862     if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
0863         runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
0864         runtime->hw.rate_max = 96000;
0865     }
0866     rate = 0;
0867     if (rme32->rcreg & RME32_RCR_KMODE)
0868         rate = snd_rme32_capture_getrate(rme32, &dummy);
0869     if (rate > 0) {
0870         /* AutoSync */
0871         runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
0872         runtime->hw.rate_min = rate;
0873         runtime->hw.rate_max = rate;
0874     }       
0875 
0876     snd_rme32_set_buffer_constraint(rme32, runtime);
0877 
0878     rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
0879     rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
0880     snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
0881                SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
0882     return 0;
0883 }
0884 
0885 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
0886 {
0887     int isadat, rate;
0888     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0889     struct snd_pcm_runtime *runtime = substream->runtime;
0890 
0891     snd_pcm_set_sync(substream);
0892 
0893     spin_lock_irq(&rme32->lock);
0894         if (rme32->capture_substream != NULL) {
0895         spin_unlock_irq(&rme32->lock);
0896                 return -EBUSY;
0897         }
0898     rme32->capture_substream = substream;
0899     spin_unlock_irq(&rme32->lock);
0900 
0901     if (rme32->fullduplex_mode)
0902         runtime->hw = snd_rme32_spdif_fd_info;
0903     else
0904         runtime->hw = snd_rme32_spdif_info;
0905     if (RME32_PRO_WITH_8414(rme32)) {
0906         runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
0907         runtime->hw.rate_max = 96000;
0908     }
0909     rate = snd_rme32_capture_getrate(rme32, &isadat);
0910     if (rate > 0) {
0911         if (isadat) {
0912             return -EIO;
0913         }
0914         runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
0915         runtime->hw.rate_min = rate;
0916         runtime->hw.rate_max = rate;
0917     }
0918 
0919     snd_rme32_set_buffer_constraint(rme32, runtime);
0920 
0921     return 0;
0922 }
0923 
0924 static int
0925 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
0926 {
0927     int rate, dummy;
0928     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0929     struct snd_pcm_runtime *runtime = substream->runtime;
0930     
0931     snd_pcm_set_sync(substream);
0932 
0933     spin_lock_irq(&rme32->lock);    
0934         if (rme32->playback_substream != NULL) {
0935         spin_unlock_irq(&rme32->lock);
0936                 return -EBUSY;
0937         }
0938     rme32->wcreg |= RME32_WCR_ADAT;
0939     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
0940     rme32->playback_substream = substream;
0941     spin_unlock_irq(&rme32->lock);
0942     
0943     if (rme32->fullduplex_mode)
0944         runtime->hw = snd_rme32_adat_fd_info;
0945     else
0946         runtime->hw = snd_rme32_adat_info;
0947     rate = 0;
0948     if (rme32->rcreg & RME32_RCR_KMODE)
0949         rate = snd_rme32_capture_getrate(rme32, &dummy);
0950     if (rate > 0) {
0951                 /* AutoSync */
0952                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
0953                 runtime->hw.rate_min = rate;
0954                 runtime->hw.rate_max = rate;
0955     }        
0956 
0957     snd_rme32_set_buffer_constraint(rme32, runtime);
0958     return 0;
0959 }
0960 
0961 static int
0962 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
0963 {
0964     int isadat, rate;
0965     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0966     struct snd_pcm_runtime *runtime = substream->runtime;
0967 
0968     if (rme32->fullduplex_mode)
0969         runtime->hw = snd_rme32_adat_fd_info;
0970     else
0971         runtime->hw = snd_rme32_adat_info;
0972     rate = snd_rme32_capture_getrate(rme32, &isadat);
0973     if (rate > 0) {
0974         if (!isadat) {
0975             return -EIO;
0976         }
0977                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
0978                 runtime->hw.rate_min = rate;
0979                 runtime->hw.rate_max = rate;
0980         }
0981 
0982     snd_pcm_set_sync(substream);
0983         
0984     spin_lock_irq(&rme32->lock);    
0985     if (rme32->capture_substream != NULL) {
0986         spin_unlock_irq(&rme32->lock);
0987         return -EBUSY;
0988         }
0989     rme32->capture_substream = substream;
0990     spin_unlock_irq(&rme32->lock);
0991 
0992     snd_rme32_set_buffer_constraint(rme32, runtime);
0993     return 0;
0994 }
0995 
0996 static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
0997 {
0998     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
0999     int spdif = 0;
1000 
1001     spin_lock_irq(&rme32->lock);
1002     rme32->playback_substream = NULL;
1003     rme32->playback_periodsize = 0;
1004     spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1005     spin_unlock_irq(&rme32->lock);
1006     if (spdif) {
1007         rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1008         snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1009                    SNDRV_CTL_EVENT_MASK_INFO,
1010                    &rme32->spdif_ctl->id);
1011     }
1012     return 0;
1013 }
1014 
1015 static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1016 {
1017     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1018 
1019     spin_lock_irq(&rme32->lock);
1020     rme32->capture_substream = NULL;
1021     rme32->capture_periodsize = 0;
1022     spin_unlock_irq(&rme32->lock);
1023     return 0;
1024 }
1025 
1026 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1027 {
1028     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1029 
1030     spin_lock_irq(&rme32->lock);
1031     if (rme32->fullduplex_mode) {
1032         memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1033         rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1034         rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1035     } else {
1036         writel(0, rme32->iobase + RME32_IO_RESET_POS);
1037     }
1038     if (rme32->wcreg & RME32_WCR_SEL)
1039         rme32->wcreg &= ~RME32_WCR_MUTE;
1040     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1041     spin_unlock_irq(&rme32->lock);
1042     return 0;
1043 }
1044 
1045 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1046 {
1047     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1048 
1049     spin_lock_irq(&rme32->lock);
1050     if (rme32->fullduplex_mode) {
1051         memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1052         rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1053         rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1054         rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1055     } else {
1056         writel(0, rme32->iobase + RME32_IO_RESET_POS);
1057     }
1058     spin_unlock_irq(&rme32->lock);
1059     return 0;
1060 }
1061 
1062 static int
1063 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1064 {
1065     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1066     struct snd_pcm_substream *s;
1067 
1068     spin_lock(&rme32->lock);
1069     snd_pcm_group_for_each_entry(s, substream) {
1070         if (s != rme32->playback_substream &&
1071             s != rme32->capture_substream)
1072             continue;
1073         switch (cmd) {
1074         case SNDRV_PCM_TRIGGER_START:
1075             rme32->running |= (1 << s->stream);
1076             if (rme32->fullduplex_mode) {
1077                 /* remember the current DMA position */
1078                 if (s == rme32->playback_substream) {
1079                     rme32->playback_pcm.hw_io =
1080                     rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1081                 } else {
1082                     rme32->capture_pcm.hw_io =
1083                     rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1084                 }
1085             }
1086             break;
1087         case SNDRV_PCM_TRIGGER_STOP:
1088             rme32->running &= ~(1 << s->stream);
1089             break;
1090         }
1091         snd_pcm_trigger_done(s, substream);
1092     }
1093     
1094     switch (cmd) {
1095     case SNDRV_PCM_TRIGGER_START:
1096         if (rme32->running && ! RME32_ISWORKING(rme32))
1097             snd_rme32_pcm_start(rme32, 0);
1098         break;
1099     case SNDRV_PCM_TRIGGER_STOP:
1100         if (! rme32->running && RME32_ISWORKING(rme32))
1101             snd_rme32_pcm_stop(rme32, 0);
1102         break;
1103     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1104         if (rme32->running && RME32_ISWORKING(rme32))
1105             snd_rme32_pcm_stop(rme32, 1);
1106         break;
1107     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1108         if (rme32->running && ! RME32_ISWORKING(rme32))
1109             snd_rme32_pcm_start(rme32, 1);
1110         break;
1111     }
1112     spin_unlock(&rme32->lock);
1113     return 0;
1114 }
1115 
1116 /* pointer callback for halfduplex mode */
1117 static snd_pcm_uframes_t
1118 snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1119 {
1120     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1121     return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1122 }
1123 
1124 static snd_pcm_uframes_t
1125 snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1126 {
1127     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1128     return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1129 }
1130 
1131 
1132 /* ack and pointer callbacks for fullduplex mode */
1133 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1134                     struct snd_pcm_indirect *rec, size_t bytes)
1135 {
1136     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1137     memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1138             substream->runtime->dma_area + rec->sw_data, bytes);
1139 }
1140 
1141 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1142 {
1143     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1144     struct snd_pcm_indirect *rec, *cprec;
1145 
1146     rec = &rme32->playback_pcm;
1147     cprec = &rme32->capture_pcm;
1148     spin_lock(&rme32->lock);
1149     rec->hw_queue_size = RME32_BUFFER_SIZE;
1150     if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1151         rec->hw_queue_size -= cprec->hw_ready;
1152     spin_unlock(&rme32->lock);
1153     return snd_pcm_indirect_playback_transfer(substream, rec,
1154                           snd_rme32_pb_trans_copy);
1155 }
1156 
1157 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1158                     struct snd_pcm_indirect *rec, size_t bytes)
1159 {
1160     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1161     memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1162               rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1163               bytes);
1164 }
1165 
1166 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1167 {
1168     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1169     return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1170                          snd_rme32_cp_trans_copy);
1171 }
1172 
1173 static snd_pcm_uframes_t
1174 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1175 {
1176     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1177     return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1178                          snd_rme32_pcm_byteptr(rme32));
1179 }
1180 
1181 static snd_pcm_uframes_t
1182 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1183 {
1184     struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1185     return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1186                         snd_rme32_pcm_byteptr(rme32));
1187 }
1188 
1189 /* for halfduplex mode */
1190 static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1191     .open =     snd_rme32_playback_spdif_open,
1192     .close =    snd_rme32_playback_close,
1193     .hw_params =    snd_rme32_playback_hw_params,
1194     .prepare =  snd_rme32_playback_prepare,
1195     .trigger =  snd_rme32_pcm_trigger,
1196     .pointer =  snd_rme32_playback_pointer,
1197     .copy_user =    snd_rme32_playback_copy,
1198     .copy_kernel =  snd_rme32_playback_copy_kernel,
1199     .fill_silence = snd_rme32_playback_silence,
1200     .mmap =     snd_pcm_lib_mmap_iomem,
1201 };
1202 
1203 static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1204     .open =     snd_rme32_capture_spdif_open,
1205     .close =    snd_rme32_capture_close,
1206     .hw_params =    snd_rme32_capture_hw_params,
1207     .prepare =  snd_rme32_capture_prepare,
1208     .trigger =  snd_rme32_pcm_trigger,
1209     .pointer =  snd_rme32_capture_pointer,
1210     .copy_user =    snd_rme32_capture_copy,
1211     .copy_kernel =  snd_rme32_capture_copy_kernel,
1212     .mmap =     snd_pcm_lib_mmap_iomem,
1213 };
1214 
1215 static const struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1216     .open =     snd_rme32_playback_adat_open,
1217     .close =    snd_rme32_playback_close,
1218     .hw_params =    snd_rme32_playback_hw_params,
1219     .prepare =  snd_rme32_playback_prepare,
1220     .trigger =  snd_rme32_pcm_trigger,
1221     .pointer =  snd_rme32_playback_pointer,
1222     .copy_user =    snd_rme32_playback_copy,
1223     .copy_kernel =  snd_rme32_playback_copy_kernel,
1224     .fill_silence = snd_rme32_playback_silence,
1225     .mmap =     snd_pcm_lib_mmap_iomem,
1226 };
1227 
1228 static const struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1229     .open =     snd_rme32_capture_adat_open,
1230     .close =    snd_rme32_capture_close,
1231     .hw_params =    snd_rme32_capture_hw_params,
1232     .prepare =  snd_rme32_capture_prepare,
1233     .trigger =  snd_rme32_pcm_trigger,
1234     .pointer =  snd_rme32_capture_pointer,
1235     .copy_user =    snd_rme32_capture_copy,
1236     .copy_kernel =  snd_rme32_capture_copy_kernel,
1237     .mmap =     snd_pcm_lib_mmap_iomem,
1238 };
1239 
1240 /* for fullduplex mode */
1241 static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1242     .open =     snd_rme32_playback_spdif_open,
1243     .close =    snd_rme32_playback_close,
1244     .hw_params =    snd_rme32_playback_hw_params,
1245     .prepare =  snd_rme32_playback_prepare,
1246     .trigger =  snd_rme32_pcm_trigger,
1247     .pointer =  snd_rme32_playback_fd_pointer,
1248     .ack =      snd_rme32_playback_fd_ack,
1249 };
1250 
1251 static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1252     .open =     snd_rme32_capture_spdif_open,
1253     .close =    snd_rme32_capture_close,
1254     .hw_params =    snd_rme32_capture_hw_params,
1255     .prepare =  snd_rme32_capture_prepare,
1256     .trigger =  snd_rme32_pcm_trigger,
1257     .pointer =  snd_rme32_capture_fd_pointer,
1258     .ack =      snd_rme32_capture_fd_ack,
1259 };
1260 
1261 static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1262     .open =     snd_rme32_playback_adat_open,
1263     .close =    snd_rme32_playback_close,
1264     .hw_params =    snd_rme32_playback_hw_params,
1265     .prepare =  snd_rme32_playback_prepare,
1266     .trigger =  snd_rme32_pcm_trigger,
1267     .pointer =  snd_rme32_playback_fd_pointer,
1268     .ack =      snd_rme32_playback_fd_ack,
1269 };
1270 
1271 static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1272     .open =     snd_rme32_capture_adat_open,
1273     .close =    snd_rme32_capture_close,
1274     .hw_params =    snd_rme32_capture_hw_params,
1275     .prepare =  snd_rme32_capture_prepare,
1276     .trigger =  snd_rme32_pcm_trigger,
1277     .pointer =  snd_rme32_capture_fd_pointer,
1278     .ack =      snd_rme32_capture_fd_ack,
1279 };
1280 
1281 static void snd_rme32_free(struct rme32 *rme32)
1282 {
1283     if (rme32->irq >= 0)
1284         snd_rme32_pcm_stop(rme32, 0);
1285 }
1286 
1287 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1288 {
1289     struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1290     rme32->spdif_pcm = NULL;
1291 }
1292 
1293 static void
1294 snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1295 {
1296     struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1297     rme32->adat_pcm = NULL;
1298 }
1299 
1300 static int snd_rme32_create(struct rme32 *rme32)
1301 {
1302     struct pci_dev *pci = rme32->pci;
1303     int err;
1304 
1305     rme32->irq = -1;
1306     spin_lock_init(&rme32->lock);
1307 
1308     err = pcim_enable_device(pci);
1309     if (err < 0)
1310         return err;
1311 
1312     err = pci_request_regions(pci, "RME32");
1313     if (err < 0)
1314         return err;
1315     rme32->port = pci_resource_start(rme32->pci, 0);
1316 
1317     rme32->iobase = devm_ioremap(&pci->dev, rme32->port, RME32_IO_SIZE);
1318     if (!rme32->iobase) {
1319         dev_err(rme32->card->dev,
1320             "unable to remap memory region 0x%lx-0x%lx\n",
1321             rme32->port, rme32->port + RME32_IO_SIZE - 1);
1322         return -ENOMEM;
1323     }
1324 
1325     if (devm_request_irq(&pci->dev, pci->irq, snd_rme32_interrupt,
1326                  IRQF_SHARED, KBUILD_MODNAME, rme32)) {
1327         dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
1328         return -EBUSY;
1329     }
1330     rme32->irq = pci->irq;
1331     rme32->card->sync_irq = rme32->irq;
1332 
1333     /* read the card's revision number */
1334     pci_read_config_byte(pci, 8, &rme32->rev);
1335 
1336     /* set up ALSA pcm device for S/PDIF */
1337     err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm);
1338     if (err < 0)
1339         return err;
1340     rme32->spdif_pcm->private_data = rme32;
1341     rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1342     strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1343     if (rme32->fullduplex_mode) {
1344         snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1345                 &snd_rme32_playback_spdif_fd_ops);
1346         snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1347                 &snd_rme32_capture_spdif_fd_ops);
1348         snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1349                            NULL, 0, RME32_MID_BUFFER_SIZE);
1350         rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1351     } else {
1352         snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1353                 &snd_rme32_playback_spdif_ops);
1354         snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1355                 &snd_rme32_capture_spdif_ops);
1356         rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1357     }
1358 
1359     /* set up ALSA pcm device for ADAT */
1360     if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1361         (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1362         /* ADAT is not available on DIGI32 and DIGI32 Pro */
1363         rme32->adat_pcm = NULL;
1364     }
1365     else {
1366         err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1367                   1, 1, &rme32->adat_pcm);
1368         if (err < 0)
1369             return err;
1370         rme32->adat_pcm->private_data = rme32;
1371         rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1372         strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1373         if (rme32->fullduplex_mode) {
1374             snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 
1375                     &snd_rme32_playback_adat_fd_ops);
1376             snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 
1377                     &snd_rme32_capture_adat_fd_ops);
1378             snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1379                                NULL,
1380                                0, RME32_MID_BUFFER_SIZE);
1381             rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1382         } else {
1383             snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 
1384                     &snd_rme32_playback_adat_ops);
1385             snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 
1386                     &snd_rme32_capture_adat_ops);
1387             rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1388         }
1389     }
1390 
1391 
1392     rme32->playback_periodsize = 0;
1393     rme32->capture_periodsize = 0;
1394 
1395     /* make sure playback/capture is stopped, if by some reason active */
1396     snd_rme32_pcm_stop(rme32, 0);
1397 
1398         /* reset DAC */
1399         snd_rme32_reset_dac(rme32);
1400 
1401     /* reset buffer pointer */
1402     writel(0, rme32->iobase + RME32_IO_RESET_POS);
1403 
1404     /* set default values in registers */
1405     rme32->wcreg = RME32_WCR_SEL |   /* normal playback */
1406         RME32_WCR_INP_0 | /* input select */
1407         RME32_WCR_MUTE;  /* muting on */
1408     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1409 
1410 
1411     /* init switch interface */
1412     err = snd_rme32_create_switches(rme32->card, rme32);
1413     if (err < 0)
1414         return err;
1415 
1416     /* init proc interface */
1417     snd_rme32_proc_init(rme32);
1418 
1419     rme32->capture_substream = NULL;
1420     rme32->playback_substream = NULL;
1421 
1422     return 0;
1423 }
1424 
1425 /*
1426  * proc interface
1427  */
1428 
1429 static void
1430 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1431 {
1432     int n;
1433     struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1434 
1435     rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1436 
1437     snd_iprintf(buffer, rme32->card->longname);
1438     snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1439 
1440     snd_iprintf(buffer, "\nGeneral settings\n");
1441     if (rme32->fullduplex_mode)
1442         snd_iprintf(buffer, "  Full-duplex mode\n");
1443     else
1444         snd_iprintf(buffer, "  Half-duplex mode\n");
1445     if (RME32_PRO_WITH_8414(rme32)) {
1446         snd_iprintf(buffer, "  receiver: CS8414\n");
1447     } else {
1448         snd_iprintf(buffer, "  receiver: CS8412\n");
1449     }
1450     if (rme32->wcreg & RME32_WCR_MODE24) {
1451         snd_iprintf(buffer, "  format: 24 bit");
1452     } else {
1453         snd_iprintf(buffer, "  format: 16 bit");
1454     }
1455     if (rme32->wcreg & RME32_WCR_MONO) {
1456         snd_iprintf(buffer, ", Mono\n");
1457     } else {
1458         snd_iprintf(buffer, ", Stereo\n");
1459     }
1460 
1461     snd_iprintf(buffer, "\nInput settings\n");
1462     switch (snd_rme32_getinputtype(rme32)) {
1463     case RME32_INPUT_OPTICAL:
1464         snd_iprintf(buffer, "  input: optical");
1465         break;
1466     case RME32_INPUT_COAXIAL:
1467         snd_iprintf(buffer, "  input: coaxial");
1468         break;
1469     case RME32_INPUT_INTERNAL:
1470         snd_iprintf(buffer, "  input: internal");
1471         break;
1472     case RME32_INPUT_XLR:
1473         snd_iprintf(buffer, "  input: XLR");
1474         break;
1475     }
1476     if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1477         snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1478     } else {
1479         if (n) {
1480             snd_iprintf(buffer, " (8 channels)\n");
1481         } else {
1482             snd_iprintf(buffer, " (2 channels)\n");
1483         }
1484         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1485                 snd_rme32_capture_getrate(rme32, &n));
1486     }
1487 
1488     snd_iprintf(buffer, "\nOutput settings\n");
1489     if (rme32->wcreg & RME32_WCR_SEL) {
1490         snd_iprintf(buffer, "  output signal: normal playback");
1491     } else {
1492         snd_iprintf(buffer, "  output signal: same as input");
1493     }
1494     if (rme32->wcreg & RME32_WCR_MUTE) {
1495         snd_iprintf(buffer, " (muted)\n");
1496     } else {
1497         snd_iprintf(buffer, "\n");
1498     }
1499 
1500     /* master output frequency */
1501     if (!
1502         ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1503          && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1504         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1505                 snd_rme32_playback_getrate(rme32));
1506     }
1507     if (rme32->rcreg & RME32_RCR_KMODE) {
1508         snd_iprintf(buffer, "  sample clock source: AutoSync\n");
1509     } else {
1510         snd_iprintf(buffer, "  sample clock source: Internal\n");
1511     }
1512     if (rme32->wcreg & RME32_WCR_PRO) {
1513         snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1514     } else {
1515         snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1516     }
1517     if (rme32->wcreg & RME32_WCR_EMP) {
1518         snd_iprintf(buffer, "  emphasis: on\n");
1519     } else {
1520         snd_iprintf(buffer, "  emphasis: off\n");
1521     }
1522 }
1523 
1524 static void snd_rme32_proc_init(struct rme32 *rme32)
1525 {
1526     snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read);
1527 }
1528 
1529 /*
1530  * control interface
1531  */
1532 
1533 #define snd_rme32_info_loopback_control     snd_ctl_boolean_mono_info
1534 
1535 static int
1536 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1537                    struct snd_ctl_elem_value *ucontrol)
1538 {
1539     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1540 
1541     spin_lock_irq(&rme32->lock);
1542     ucontrol->value.integer.value[0] =
1543         rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1544     spin_unlock_irq(&rme32->lock);
1545     return 0;
1546 }
1547 static int
1548 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1549                    struct snd_ctl_elem_value *ucontrol)
1550 {
1551     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1552     unsigned int val;
1553     int change;
1554 
1555     val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1556     spin_lock_irq(&rme32->lock);
1557     val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1558     change = val != rme32->wcreg;
1559     if (ucontrol->value.integer.value[0])
1560         val &= ~RME32_WCR_MUTE;
1561     else
1562         val |= RME32_WCR_MUTE;
1563     rme32->wcreg = val;
1564     writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1565     spin_unlock_irq(&rme32->lock);
1566     return change;
1567 }
1568 
1569 static int
1570 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1571                  struct snd_ctl_elem_info *uinfo)
1572 {
1573     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1574     static const char * const texts[4] = {
1575         "Optical", "Coaxial", "Internal", "XLR"
1576     };
1577     int num_items;
1578 
1579     switch (rme32->pci->device) {
1580     case PCI_DEVICE_ID_RME_DIGI32:
1581     case PCI_DEVICE_ID_RME_DIGI32_8:
1582         num_items = 3;
1583         break;
1584     case PCI_DEVICE_ID_RME_DIGI32_PRO:
1585         num_items = 4;
1586         break;
1587     default:
1588         snd_BUG();
1589         return -EINVAL;
1590     }
1591     return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1592 }
1593 static int
1594 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1595                 struct snd_ctl_elem_value *ucontrol)
1596 {
1597     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1598     unsigned int items = 3;
1599 
1600     spin_lock_irq(&rme32->lock);
1601     ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1602 
1603     switch (rme32->pci->device) {
1604     case PCI_DEVICE_ID_RME_DIGI32:
1605     case PCI_DEVICE_ID_RME_DIGI32_8:
1606         items = 3;
1607         break;
1608     case PCI_DEVICE_ID_RME_DIGI32_PRO:
1609         items = 4;
1610         break;
1611     default:
1612         snd_BUG();
1613         break;
1614     }
1615     if (ucontrol->value.enumerated.item[0] >= items) {
1616         ucontrol->value.enumerated.item[0] = items - 1;
1617     }
1618 
1619     spin_unlock_irq(&rme32->lock);
1620     return 0;
1621 }
1622 static int
1623 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1624                 struct snd_ctl_elem_value *ucontrol)
1625 {
1626     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1627     unsigned int val;
1628     int change, items = 3;
1629 
1630     switch (rme32->pci->device) {
1631     case PCI_DEVICE_ID_RME_DIGI32:
1632     case PCI_DEVICE_ID_RME_DIGI32_8:
1633         items = 3;
1634         break;
1635     case PCI_DEVICE_ID_RME_DIGI32_PRO:
1636         items = 4;
1637         break;
1638     default:
1639         snd_BUG();
1640         break;
1641     }
1642     val = ucontrol->value.enumerated.item[0] % items;
1643 
1644     spin_lock_irq(&rme32->lock);
1645     change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1646     snd_rme32_setinputtype(rme32, val);
1647     spin_unlock_irq(&rme32->lock);
1648     return change;
1649 }
1650 
1651 static int
1652 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1653                  struct snd_ctl_elem_info *uinfo)
1654 {
1655     static const char * const texts[4] = { "AutoSync",
1656                   "Internal 32.0kHz", 
1657                   "Internal 44.1kHz", 
1658                   "Internal 48.0kHz" };
1659 
1660     return snd_ctl_enum_info(uinfo, 1, 4, texts);
1661 }
1662 static int
1663 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1664                 struct snd_ctl_elem_value *ucontrol)
1665 {
1666     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1667 
1668     spin_lock_irq(&rme32->lock);
1669     ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1670     spin_unlock_irq(&rme32->lock);
1671     return 0;
1672 }
1673 static int
1674 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1675                 struct snd_ctl_elem_value *ucontrol)
1676 {
1677     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1678     unsigned int val;
1679     int change;
1680 
1681     val = ucontrol->value.enumerated.item[0] % 3;
1682     spin_lock_irq(&rme32->lock);
1683     change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1684     snd_rme32_setclockmode(rme32, val);
1685     spin_unlock_irq(&rme32->lock);
1686     return change;
1687 }
1688 
1689 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1690 {
1691     u32 val = 0;
1692     val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1693     if (val & RME32_WCR_PRO)
1694         val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1695     else
1696         val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1697     return val;
1698 }
1699 
1700 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1701 {
1702     aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1703     if (val & RME32_WCR_PRO)
1704         aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1705     else
1706         aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1707 }
1708 
1709 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1710                     struct snd_ctl_elem_info *uinfo)
1711 {
1712     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1713     uinfo->count = 1;
1714     return 0;
1715 }
1716 
1717 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1718                        struct snd_ctl_elem_value *ucontrol)
1719 {
1720     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1721 
1722     snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1723                  rme32->wcreg_spdif);
1724     return 0;
1725 }
1726 
1727 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1728                        struct snd_ctl_elem_value *ucontrol)
1729 {
1730     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1731     int change;
1732     u32 val;
1733 
1734     val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1735     spin_lock_irq(&rme32->lock);
1736     change = val != rme32->wcreg_spdif;
1737     rme32->wcreg_spdif = val;
1738     spin_unlock_irq(&rme32->lock);
1739     return change;
1740 }
1741 
1742 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1743                            struct snd_ctl_elem_info *uinfo)
1744 {
1745     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1746     uinfo->count = 1;
1747     return 0;
1748 }
1749 
1750 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1751                           struct snd_ctl_elem_value *
1752                           ucontrol)
1753 {
1754     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1755 
1756     snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1757                  rme32->wcreg_spdif_stream);
1758     return 0;
1759 }
1760 
1761 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1762                           struct snd_ctl_elem_value *
1763                           ucontrol)
1764 {
1765     struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1766     int change;
1767     u32 val;
1768 
1769     val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1770     spin_lock_irq(&rme32->lock);
1771     change = val != rme32->wcreg_spdif_stream;
1772     rme32->wcreg_spdif_stream = val;
1773     rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1774     rme32->wcreg |= val;
1775     writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1776     spin_unlock_irq(&rme32->lock);
1777     return change;
1778 }
1779 
1780 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1781                          struct snd_ctl_elem_info *uinfo)
1782 {
1783     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1784     uinfo->count = 1;
1785     return 0;
1786 }
1787 
1788 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1789                         struct snd_ctl_elem_value *
1790                         ucontrol)
1791 {
1792     ucontrol->value.iec958.status[0] = kcontrol->private_value;
1793     return 0;
1794 }
1795 
1796 static const struct snd_kcontrol_new snd_rme32_controls[] = {
1797     {
1798         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1799         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1800         .info = snd_rme32_control_spdif_info,
1801         .get =  snd_rme32_control_spdif_get,
1802         .put =  snd_rme32_control_spdif_put
1803     },
1804     {
1805         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1806         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1807         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1808         .info = snd_rme32_control_spdif_stream_info,
1809         .get =  snd_rme32_control_spdif_stream_get,
1810         .put =  snd_rme32_control_spdif_stream_put
1811     },
1812     {
1813         .access = SNDRV_CTL_ELEM_ACCESS_READ,
1814         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1815         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1816         .info = snd_rme32_control_spdif_mask_info,
1817         .get =  snd_rme32_control_spdif_mask_get,
1818         .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1819     },
1820     {
1821         .access = SNDRV_CTL_ELEM_ACCESS_READ,
1822         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1823         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1824         .info = snd_rme32_control_spdif_mask_info,
1825         .get =  snd_rme32_control_spdif_mask_get,
1826         .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1827     },
1828     {
1829         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1830         .name = "Input Connector",
1831         .info = snd_rme32_info_inputtype_control,
1832         .get =  snd_rme32_get_inputtype_control,
1833         .put =  snd_rme32_put_inputtype_control
1834     },
1835     {
1836         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1837         .name = "Loopback Input",
1838         .info = snd_rme32_info_loopback_control,
1839         .get =  snd_rme32_get_loopback_control,
1840         .put =  snd_rme32_put_loopback_control
1841     },
1842     {
1843         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1844         .name = "Sample Clock Source",
1845         .info = snd_rme32_info_clockmode_control,
1846         .get =  snd_rme32_get_clockmode_control,
1847         .put =  snd_rme32_put_clockmode_control
1848     }
1849 };
1850 
1851 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1852 {
1853     int idx, err;
1854     struct snd_kcontrol *kctl;
1855 
1856     for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1857         kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32);
1858         err = snd_ctl_add(card, kctl);
1859         if (err < 0)
1860             return err;
1861         if (idx == 1)   /* IEC958 (S/PDIF) Stream */
1862             rme32->spdif_ctl = kctl;
1863     }
1864 
1865     return 0;
1866 }
1867 
1868 /*
1869  * Card initialisation
1870  */
1871 
1872 static void snd_rme32_card_free(struct snd_card *card)
1873 {
1874     snd_rme32_free(card->private_data);
1875 }
1876 
1877 static int
1878 __snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1879 {
1880     static int dev;
1881     struct rme32 *rme32;
1882     struct snd_card *card;
1883     int err;
1884 
1885     if (dev >= SNDRV_CARDS) {
1886         return -ENODEV;
1887     }
1888     if (!enable[dev]) {
1889         dev++;
1890         return -ENOENT;
1891     }
1892 
1893     err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1894                 sizeof(*rme32), &card);
1895     if (err < 0)
1896         return err;
1897     card->private_free = snd_rme32_card_free;
1898     rme32 = (struct rme32 *) card->private_data;
1899     rme32->card = card;
1900     rme32->pci = pci;
1901         if (fullduplex[dev])
1902         rme32->fullduplex_mode = 1;
1903     err = snd_rme32_create(rme32);
1904     if (err < 0)
1905         return err;
1906 
1907     strcpy(card->driver, "Digi32");
1908     switch (rme32->pci->device) {
1909     case PCI_DEVICE_ID_RME_DIGI32:
1910         strcpy(card->shortname, "RME Digi32");
1911         break;
1912     case PCI_DEVICE_ID_RME_DIGI32_8:
1913         strcpy(card->shortname, "RME Digi32/8");
1914         break;
1915     case PCI_DEVICE_ID_RME_DIGI32_PRO:
1916         strcpy(card->shortname, "RME Digi32 PRO");
1917         break;
1918     }
1919     sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1920         card->shortname, rme32->rev, rme32->port, rme32->irq);
1921 
1922     err = snd_card_register(card);
1923     if (err < 0)
1924         return err;
1925     pci_set_drvdata(pci, card);
1926     dev++;
1927     return 0;
1928 }
1929 
1930 static int
1931 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1932 {
1933     return snd_card_free_on_error(&pci->dev, __snd_rme32_probe(pci, pci_id));
1934 }
1935 
1936 static struct pci_driver rme32_driver = {
1937     .name =     KBUILD_MODNAME,
1938     .id_table = snd_rme32_ids,
1939     .probe =    snd_rme32_probe,
1940 };
1941 
1942 module_pci_driver(rme32_driver);
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