pci/pcxhr/pcxhr_core.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Driver for Digigram pcxhr compatible soundcards
0004  *
0005  * low level interface with interrupt and message handling
0006  *
0007  * Copyright (c) 2004 by Digigram <alsa@digigram.com>
0008  */
0009
0010 #ifndef __SOUND_PCXHR_CORE_H
0011 #define __SOUND_PCXHR_CORE_H
0012
0013 struct firmware;
0014 struct pcxhr_mgr;
0015
0016 /* init and firmware download commands */
0017 void pcxhr_reset_xilinx_com(struct pcxhr_mgr *mgr);
0018 void pcxhr_reset_dsp(struct pcxhr_mgr *mgr);
0019 void pcxhr_enable_dsp(struct pcxhr_mgr *mgr);
0020 int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second);
0021 int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom);
0022 int pcxhr_load_boot_binary(struct pcxhr_mgr *mgr, const struct firmware *boot);
0023 int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp);
0024
0025 /* DSP time available on MailBox4 register : 24 bit time samples() */
0026 #define PCXHR_DSP_TIME_MASK     0x00ffffff
0027 #define PCXHR_DSP_TIME_INVALID      0x10000000
0028
0029
0030 #define PCXHR_SIZE_MAX_CMD      8
0031 #define PCXHR_SIZE_MAX_STATUS       16
0032 #define PCXHR_SIZE_MAX_LONG_STATUS  256
0033
0034 struct pcxhr_rmh {
0035     u16 cmd_len;        /* length of the command to send (WORDs) */
0036     u16 stat_len;       /* length of the status received (WORDs) */
0037     u16 dsp_stat;       /* status type, RMP_SSIZE_XXX */
0038     u16 cmd_idx;        /* index of the command */
0039     u32 cmd[PCXHR_SIZE_MAX_CMD];
0040     u32 stat[PCXHR_SIZE_MAX_STATUS];
0041 };
0042
0043 enum {
0044     CMD_VERSION,            /* cmd_len = 2  stat_len = 1 */
0045     CMD_SUPPORTED,          /* cmd_len = 1  stat_len = 4 */
0046     CMD_TEST_IT,            /* cmd_len = 1  stat_len = 1 */
0047     CMD_SEND_IRQA,          /* cmd_len = 1  stat_len = 0 */
0048     CMD_ACCESS_IO_WRITE,        /* cmd_len >= 1 stat_len >= 1 */
0049     CMD_ACCESS_IO_READ,     /* cmd_len >= 1 stat_len >= 1 */
0050     CMD_ASYNC,          /* cmd_len = 1  stat_len = 1 */
0051     CMD_MODIFY_CLOCK,       /* cmd_len = 3  stat_len = 0 */
0052     CMD_RESYNC_AUDIO_INPUTS,    /* cmd_len = 1  stat_len = 0 */
0053     CMD_GET_DSP_RESOURCES,      /* cmd_len = 1  stat_len = 4 */
0054     CMD_SET_TIMER_INTERRUPT,    /* cmd_len = 1  stat_len = 0 */
0055     CMD_RES_PIPE,           /* cmd_len >=2  stat_len = 0 */
0056     CMD_FREE_PIPE,          /* cmd_len = 1  stat_len = 0 */
0057     CMD_CONF_PIPE,          /* cmd_len = 2  stat_len = 0 */
0058     CMD_STOP_PIPE,          /* cmd_len = 1  stat_len = 0 */
0059     CMD_PIPE_SAMPLE_COUNT,      /* cmd_len = 2  stat_len = 2 */
0060     CMD_CAN_START_PIPE,     /* cmd_len >= 1 stat_len = 1 */
0061     CMD_START_STREAM,       /* cmd_len = 2  stat_len = 0 */
0062     CMD_STREAM_OUT_LEVEL_ADJUST,    /* cmd_len >= 1 stat_len = 0 */
0063     CMD_STOP_STREAM,        /* cmd_len = 2  stat_len = 0 */
0064     CMD_UPDATE_R_BUFFERS,       /* cmd_len = 4  stat_len = 0 */
0065     CMD_FORMAT_STREAM_OUT,      /* cmd_len >= 2 stat_len = 0 */
0066     CMD_FORMAT_STREAM_IN,       /* cmd_len >= 4 stat_len = 0 */
0067     CMD_STREAM_SAMPLE_COUNT,    /* cmd_len = 2  stat_len = (2 * nb_stream) */
0068     CMD_AUDIO_LEVEL_ADJUST,     /* cmd_len = 3  stat_len = 0 */
0069     CMD_GET_TIME_CODE,      /* cmd_len = 1  stat_len = 5 */
0070     CMD_MANAGE_SIGNAL,      /* cmd_len = 1  stat_len = 0 */
0071     CMD_LAST_INDEX
0072 };
0073
0074 #define MASK_DSP_WORD       0x00ffffff
0075 #define MASK_ALL_STREAM     0x00ffffff
0076 #define MASK_DSP_WORD_LEVEL 0x000001ff
0077 #define MASK_FIRST_FIELD    0x0000001f
0078 #define FIELD_SIZE      5
0079
0080 /*
0081  init the rmh struct; by default cmd_len is set to 1
0082  */
0083 void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd);
0084
0085 void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1,
0086                    unsigned int param2, unsigned int param3);
0087
0088 #define DSP_EXT_CMD_SET(x) (x->dsp_version > 0x012800)
0089
0090 /*
0091  send the rmh
0092  */
0093 int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh);
0094
0095
0096 /* values used for CMD_ACCESS_IO_WRITE and CMD_ACCESS_IO_READ */
0097 #define IO_NUM_REG_CONT         0
0098 #define IO_NUM_REG_GENCLK       1
0099 #define IO_NUM_REG_MUTE_OUT     2
0100 #define IO_NUM_SPEED_RATIO      4
0101 #define IO_NUM_REG_STATUS       5
0102 #define IO_NUM_REG_CUER         10
0103 #define IO_NUM_UER_CHIP_REG     11
0104 #define IO_NUM_REG_CONFIG_SRC       12
0105 #define IO_NUM_REG_OUT_ANA_LEVEL    20
0106 #define IO_NUM_REG_IN_ANA_LEVEL     21
0107
0108 #define REG_CONT_VALSMPTE       0x000800
0109 #define REG_CONT_UNMUTE_INPUTS      0x020000
0110
0111 /* parameters used with register IO_NUM_REG_STATUS */
0112 #define REG_STATUS_OPTIONS      0
0113 #define REG_STATUS_AES_SYNC     8
0114 #define REG_STATUS_AES_1        9
0115 #define REG_STATUS_AES_2        10
0116 #define REG_STATUS_AES_3        11
0117 #define REG_STATUS_AES_4        12
0118 #define REG_STATUS_WORD_CLOCK       13
0119 #define REG_STATUS_INTER_SYNC       14
0120 #define REG_STATUS_CURRENT      0x80
0121 /* results */
0122 #define REG_STATUS_OPT_NO_VIDEO_SIGNAL  0x01
0123 #define REG_STATUS_OPT_DAUGHTER_MASK    0x1c
0124 #define REG_STATUS_OPT_ANALOG_BOARD 0x00
0125 #define REG_STATUS_OPT_NO_DAUGHTER  0x1c
0126 #define REG_STATUS_OPT_COMPANION_MASK   0xe0
0127 #define REG_STATUS_OPT_NO_COMPANION 0xe0
0128 #define REG_STATUS_SYNC_32000       0x00
0129 #define REG_STATUS_SYNC_44100       0x01
0130 #define REG_STATUS_SYNC_48000       0x02
0131 #define REG_STATUS_SYNC_64000       0x03
0132 #define REG_STATUS_SYNC_88200       0x04
0133 #define REG_STATUS_SYNC_96000       0x05
0134 #define REG_STATUS_SYNC_128000      0x06
0135 #define REG_STATUS_SYNC_176400      0x07
0136 #define REG_STATUS_SYNC_192000      0x08
0137
0138 int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start);
0139
0140 int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask,
0141                 unsigned int value, int *changed);
0142
0143 /* codec parameters */
0144 #define CS8416_RUN      0x200401
0145 #define CS8416_FORMAT_DETECT    0x200b00
0146 #define CS8416_CSB0     0x201900
0147 #define CS8416_CSB1     0x201a00
0148 #define CS8416_CSB2     0x201b00
0149 #define CS8416_CSB3     0x201c00
0150 #define CS8416_CSB4     0x201d00
0151 #define CS8416_VERSION      0x207f00
0152
0153 #define CS8420_DATA_FLOW_CTL    0x200301
0154 #define CS8420_CLOCK_SRC_CTL    0x200401
0155 #define CS8420_RECEIVER_ERRORS  0x201000
0156 #define CS8420_SRC_RATIO    0x201e00
0157 #define CS8420_CSB0     0x202000
0158 #define CS8420_CSB1     0x202100
0159 #define CS8420_CSB2     0x202200
0160 #define CS8420_CSB3     0x202300
0161 #define CS8420_CSB4     0x202400
0162 #define CS8420_VERSION      0x207f00
0163
0164 #define CS4271_MODE_CTL_1   0x200101
0165 #define CS4271_DAC_CTL      0x200201
0166 #define CS4271_VOLMIX       0x200301
0167 #define CS4271_VOLMUTE_LEFT 0x200401
0168 #define CS4271_VOLMUTE_RIGHT    0x200501
0169 #define CS4271_ADC_CTL      0x200601
0170 #define CS4271_MODE_CTL_2   0x200701
0171
0172 #define CHIP_SIG_AND_MAP_SPI    0xff7f00
0173
0174 /* codec selection */
0175 #define CS4271_01_CS        0x160018
0176 #define CS4271_23_CS        0x160019
0177 #define CS4271_45_CS        0x16001a
0178 #define CS4271_67_CS        0x16001b
0179 #define CS4271_89_CS        0x16001c
0180 #define CS4271_AB_CS        0x16001d
0181 #define CS8420_01_CS        0x080090
0182 #define CS8420_23_CS        0x080092
0183 #define CS8420_45_CS        0x080094
0184 #define CS8420_67_CS        0x080096
0185 #define CS8416_01_CS        0x080098
0186
0187
0188 /* interrupt handling */
0189 irqreturn_t pcxhr_interrupt(int irq, void *dev_id);
0190 irqreturn_t pcxhr_threaded_irq(int irq, void *dev_id);
0191
0192 #endif /* __SOUND_PCXHR_CORE_H */