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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Digigram pcxhr compatible soundcards
0004  *
0005  * main file with alsa callbacks
0006  *
0007  * Copyright (c) 2004 by Digigram <alsa@digigram.com>
0008  */
0009 
0010 
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/slab.h>
0014 #include <linux/pci.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/delay.h>
0017 #include <linux/module.h>
0018 #include <linux/mutex.h>
0019 
0020 #include <sound/core.h>
0021 #include <sound/initval.h>
0022 #include <sound/info.h>
0023 #include <sound/control.h>
0024 #include <sound/pcm.h>
0025 #include <sound/pcm_params.h>
0026 #include "pcxhr.h"
0027 #include "pcxhr_mixer.h"
0028 #include "pcxhr_hwdep.h"
0029 #include "pcxhr_core.h"
0030 #include "pcxhr_mix22.h"
0031 
0032 #define DRIVER_NAME "pcxhr"
0033 
0034 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
0035           "Marc Titinger <titinger@digigram.com>");
0036 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
0037 MODULE_LICENSE("GPL");
0038 
0039 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;  /* Index 0-MAX */
0040 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;   /* ID for this card */
0041 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
0042 static bool mono[SNDRV_CARDS];              /* capture  mono only */
0043 
0044 module_param_array(index, int, NULL, 0444);
0045 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
0046 module_param_array(id, charp, NULL, 0444);
0047 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
0048 module_param_array(enable, bool, NULL, 0444);
0049 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
0050 module_param_array(mono, bool, NULL, 0444);
0051 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
0052 
0053 enum {
0054     PCI_ID_VX882HR,
0055     PCI_ID_PCX882HR,
0056     PCI_ID_VX881HR,
0057     PCI_ID_PCX881HR,
0058     PCI_ID_VX882E,
0059     PCI_ID_PCX882E,
0060     PCI_ID_VX881E,
0061     PCI_ID_PCX881E,
0062     PCI_ID_VX1222HR,
0063     PCI_ID_PCX1222HR,
0064     PCI_ID_VX1221HR,
0065     PCI_ID_PCX1221HR,
0066     PCI_ID_VX1222E,
0067     PCI_ID_PCX1222E,
0068     PCI_ID_VX1221E,
0069     PCI_ID_PCX1221E,
0070     PCI_ID_VX222HR,
0071     PCI_ID_VX222E,
0072     PCI_ID_PCX22HR,
0073     PCI_ID_PCX22E,
0074     PCI_ID_VX222HRMIC,
0075     PCI_ID_VX222E_MIC,
0076     PCI_ID_PCX924HR,
0077     PCI_ID_PCX924E,
0078     PCI_ID_PCX924HRMIC,
0079     PCI_ID_PCX924E_MIC,
0080     PCI_ID_VX442HR,
0081     PCI_ID_PCX442HR,
0082     PCI_ID_VX442E,
0083     PCI_ID_PCX442E,
0084     PCI_ID_VX822HR,
0085     PCI_ID_PCX822HR,
0086     PCI_ID_VX822E,
0087     PCI_ID_PCX822E,
0088     PCI_ID_LAST
0089 };
0090 
0091 static const struct pci_device_id pcxhr_ids[] = {
0092     { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
0093     { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
0094     { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
0095     { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
0096     { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, },
0097     { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, },
0098     { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, },
0099     { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, },
0100     { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, },
0101     { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
0102     { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, },
0103     { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
0104     { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, },
0105     { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, },
0106     { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, },
0107     { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, },
0108     { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, },
0109     { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, },
0110     { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, },
0111     { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, },
0112     { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, },
0113     { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, },
0114     { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, },
0115     { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, },
0116     { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, },
0117     { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, },
0118     { 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, },
0119     { 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, },
0120     { 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, },
0121     { 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, },
0122     { 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, },
0123     { 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, },
0124     { 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, },
0125     { 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, },
0126     { 0, }
0127 };
0128 
0129 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
0130 
0131 struct board_parameters {
0132     char* board_name;
0133     short playback_chips;
0134     short capture_chips;
0135     short fw_file_set;
0136     short firmware_num;
0137 };
0138 static const struct board_parameters pcxhr_board_params[] = {
0139 [PCI_ID_VX882HR] =      { "VX882HR",      4, 4, 0, 41 },
0140 [PCI_ID_PCX882HR] =     { "PCX882HR",     4, 4, 0, 41 },
0141 [PCI_ID_VX881HR] =      { "VX881HR",      4, 4, 0, 41 },
0142 [PCI_ID_PCX881HR] =     { "PCX881HR",     4, 4, 0, 41 },
0143 [PCI_ID_VX882E] =       { "VX882e",       4, 4, 1, 41 },
0144 [PCI_ID_PCX882E] =      { "PCX882e",      4, 4, 1, 41 },
0145 [PCI_ID_VX881E] =       { "VX881e",       4, 4, 1, 41 },
0146 [PCI_ID_PCX881E] =      { "PCX881e",      4, 4, 1, 41 },
0147 [PCI_ID_VX1222HR] =     { "VX1222HR",     6, 1, 2, 42 },
0148 [PCI_ID_PCX1222HR] =    { "PCX1222HR",    6, 1, 2, 42 },
0149 [PCI_ID_VX1221HR] =     { "VX1221HR",     6, 1, 2, 42 },
0150 [PCI_ID_PCX1221HR] =    { "PCX1221HR",    6, 1, 2, 42 },
0151 [PCI_ID_VX1222E] =      { "VX1222e",      6, 1, 3, 42 },
0152 [PCI_ID_PCX1222E] =     { "PCX1222e",     6, 1, 3, 42 },
0153 [PCI_ID_VX1221E] =      { "VX1221e",      6, 1, 3, 42 },
0154 [PCI_ID_PCX1221E] =     { "PCX1221e",     6, 1, 3, 42 },
0155 [PCI_ID_VX222HR] =      { "VX222HR",      1, 1, 4, 44 },
0156 [PCI_ID_VX222E] =       { "VX222e",       1, 1, 4, 44 },
0157 [PCI_ID_PCX22HR] =      { "PCX22HR",      1, 0, 4, 44 },
0158 [PCI_ID_PCX22E] =       { "PCX22e",       1, 0, 4, 44 },
0159 [PCI_ID_VX222HRMIC] =   { "VX222HR-Mic",  1, 1, 5, 44 },
0160 [PCI_ID_VX222E_MIC] =   { "VX222e-Mic",   1, 1, 5, 44 },
0161 [PCI_ID_PCX924HR] =     { "PCX924HR",     1, 1, 5, 44 },
0162 [PCI_ID_PCX924E] =      { "PCX924e",      1, 1, 5, 44 },
0163 [PCI_ID_PCX924HRMIC] =  { "PCX924HR-Mic", 1, 1, 5, 44 },
0164 [PCI_ID_PCX924E_MIC] =  { "PCX924e-Mic",  1, 1, 5, 44 },
0165 [PCI_ID_VX442HR] =      { "VX442HR",      2, 2, 0, 41 },
0166 [PCI_ID_PCX442HR] =     { "PCX442HR",     2, 2, 0, 41 },
0167 [PCI_ID_VX442E] =       { "VX442e",       2, 2, 1, 41 },
0168 [PCI_ID_PCX442E] =      { "PCX442e",      2, 2, 1, 41 },
0169 [PCI_ID_VX822HR] =      { "VX822HR",      4, 1, 2, 42 },
0170 [PCI_ID_PCX822HR] =     { "PCX822HR",     4, 1, 2, 42 },
0171 [PCI_ID_VX822E] =       { "VX822e",       4, 1, 3, 42 },
0172 [PCI_ID_PCX822E] =      { "PCX822e",      4, 1, 3, 42 },
0173 };
0174 
0175 /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
0176 /* VX222HR, VX222e, PCX22HR and PCX22e */
0177 #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
0178 /* some boards do not support 192kHz on digital AES input plugs */
0179 #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
0180                       (x->fw_file_set == 0)   || \
0181                       (x->fw_file_set == 2))
0182 
0183 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
0184                    unsigned int* realfreq)
0185 {
0186     unsigned int reg;
0187 
0188     if (freq < 6900 || freq > 110000)
0189         return -EINVAL;
0190     reg = (28224000 * 2) / freq;
0191     reg = (reg - 1) / 2;
0192     if (reg < 0x200)
0193         *pllreg = reg + 0x800;
0194     else if (reg < 0x400)
0195         *pllreg = reg & 0x1ff;
0196     else if (reg < 0x800) {
0197         *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
0198         reg &= ~1;
0199     } else {
0200         *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
0201         reg &= ~3;
0202     }
0203     if (realfreq)
0204         *realfreq = (28224000 / (reg + 1));
0205     return 0;
0206 }
0207 
0208 
0209 #define PCXHR_FREQ_REG_MASK     0x1f
0210 #define PCXHR_FREQ_QUARTZ_48000     0x00
0211 #define PCXHR_FREQ_QUARTZ_24000     0x01
0212 #define PCXHR_FREQ_QUARTZ_12000     0x09
0213 #define PCXHR_FREQ_QUARTZ_32000     0x08
0214 #define PCXHR_FREQ_QUARTZ_16000     0x04
0215 #define PCXHR_FREQ_QUARTZ_8000      0x0c
0216 #define PCXHR_FREQ_QUARTZ_44100     0x02
0217 #define PCXHR_FREQ_QUARTZ_22050     0x0a
0218 #define PCXHR_FREQ_QUARTZ_11025     0x06
0219 #define PCXHR_FREQ_PLL          0x05
0220 #define PCXHR_FREQ_QUARTZ_192000    0x10
0221 #define PCXHR_FREQ_QUARTZ_96000     0x18
0222 #define PCXHR_FREQ_QUARTZ_176400    0x14
0223 #define PCXHR_FREQ_QUARTZ_88200     0x1c
0224 #define PCXHR_FREQ_QUARTZ_128000    0x12
0225 #define PCXHR_FREQ_QUARTZ_64000     0x1a
0226 
0227 #define PCXHR_FREQ_WORD_CLOCK       0x0f
0228 #define PCXHR_FREQ_SYNC_AES     0x0e
0229 #define PCXHR_FREQ_AES_1        0x07
0230 #define PCXHR_FREQ_AES_2        0x0b
0231 #define PCXHR_FREQ_AES_3        0x03
0232 #define PCXHR_FREQ_AES_4        0x0d
0233 
0234 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
0235                    unsigned int *reg, unsigned int *freq)
0236 {
0237     unsigned int val, realfreq, pllreg;
0238     struct pcxhr_rmh rmh;
0239     int err;
0240 
0241     realfreq = rate;
0242     switch (mgr->use_clock_type) {
0243     case PCXHR_CLOCK_TYPE_INTERNAL :    /* clock by quartz or pll */
0244         switch (rate) {
0245         case 48000 :    val = PCXHR_FREQ_QUARTZ_48000;  break;
0246         case 24000 :    val = PCXHR_FREQ_QUARTZ_24000;  break;
0247         case 12000 :    val = PCXHR_FREQ_QUARTZ_12000;  break;
0248         case 32000 :    val = PCXHR_FREQ_QUARTZ_32000;  break;
0249         case 16000 :    val = PCXHR_FREQ_QUARTZ_16000;  break;
0250         case 8000 : val = PCXHR_FREQ_QUARTZ_8000;   break;
0251         case 44100 :    val = PCXHR_FREQ_QUARTZ_44100;  break;
0252         case 22050 :    val = PCXHR_FREQ_QUARTZ_22050;  break;
0253         case 11025 :    val = PCXHR_FREQ_QUARTZ_11025;  break;
0254         case 192000 :   val = PCXHR_FREQ_QUARTZ_192000; break;
0255         case 96000 :    val = PCXHR_FREQ_QUARTZ_96000;  break;
0256         case 176400 :   val = PCXHR_FREQ_QUARTZ_176400; break;
0257         case 88200 :    val = PCXHR_FREQ_QUARTZ_88200;  break;
0258         case 128000 :   val = PCXHR_FREQ_QUARTZ_128000; break;
0259         case 64000 :    val = PCXHR_FREQ_QUARTZ_64000;  break;
0260         default :
0261             val = PCXHR_FREQ_PLL;
0262             /* get the value for the pll register */
0263             err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
0264             if (err)
0265                 return err;
0266             pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
0267             rmh.cmd[0] |= IO_NUM_REG_GENCLK;
0268             rmh.cmd[1]  = pllreg & MASK_DSP_WORD;
0269             rmh.cmd[2]  = pllreg >> 24;
0270             rmh.cmd_len = 3;
0271             err = pcxhr_send_msg(mgr, &rmh);
0272             if (err < 0) {
0273                 dev_err(&mgr->pci->dev,
0274                        "error CMD_ACCESS_IO_WRITE "
0275                        "for PLL register : %x!\n", err);
0276                 return err;
0277             }
0278         }
0279         break;
0280     case PCXHR_CLOCK_TYPE_WORD_CLOCK:
0281         val = PCXHR_FREQ_WORD_CLOCK;
0282         break;
0283     case PCXHR_CLOCK_TYPE_AES_SYNC:
0284         val = PCXHR_FREQ_SYNC_AES;
0285         break;
0286     case PCXHR_CLOCK_TYPE_AES_1:
0287         val = PCXHR_FREQ_AES_1;
0288         break;
0289     case PCXHR_CLOCK_TYPE_AES_2:
0290         val = PCXHR_FREQ_AES_2;
0291         break;
0292     case PCXHR_CLOCK_TYPE_AES_3:
0293         val = PCXHR_FREQ_AES_3;
0294         break;
0295     case PCXHR_CLOCK_TYPE_AES_4:
0296         val = PCXHR_FREQ_AES_4;
0297         break;
0298     default:
0299         return -EINVAL;
0300     }
0301     *reg = val;
0302     *freq = realfreq;
0303     return 0;
0304 }
0305 
0306 
0307 static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
0308                    unsigned int rate,
0309                    int *changed)
0310 {
0311     unsigned int val, realfreq, speed;
0312     struct pcxhr_rmh rmh;
0313     int err;
0314 
0315     err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
0316     if (err)
0317         return err;
0318 
0319     /* codec speed modes */
0320     if (rate < 55000)
0321         speed = 0;  /* single speed */
0322     else if (rate < 100000)
0323         speed = 1;  /* dual speed */
0324     else
0325         speed = 2;  /* quad speed */
0326     if (mgr->codec_speed != speed) {
0327         pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
0328         rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
0329         if (DSP_EXT_CMD_SET(mgr)) {
0330             rmh.cmd[1]  = 1;
0331             rmh.cmd_len = 2;
0332         }
0333         err = pcxhr_send_msg(mgr, &rmh);
0334         if (err)
0335             return err;
0336 
0337         pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
0338         rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
0339         rmh.cmd[1] = speed;
0340         rmh.cmd_len = 2;
0341         err = pcxhr_send_msg(mgr, &rmh);
0342         if (err)
0343             return err;
0344     }
0345     /* set the new frequency */
0346     dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val);
0347     err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
0348                       val, changed);
0349     if (err)
0350         return err;
0351 
0352     mgr->sample_rate_real = realfreq;
0353     mgr->cur_clock_type = mgr->use_clock_type;
0354 
0355     /* unmute after codec speed modes */
0356     if (mgr->codec_speed != speed) {
0357         pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
0358         rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
0359         if (DSP_EXT_CMD_SET(mgr)) {
0360             rmh.cmd[1]  = 1;
0361             rmh.cmd_len = 2;
0362         }
0363         err = pcxhr_send_msg(mgr, &rmh);
0364         if (err)
0365             return err;
0366         mgr->codec_speed = speed;   /* save new codec speed */
0367     }
0368 
0369     dev_dbg(&mgr->pci->dev, "%s to %dHz (realfreq=%d)\n", __func__,
0370             rate, realfreq);
0371     return 0;
0372 }
0373 
0374 #define PCXHR_MODIFY_CLOCK_S_BIT    0x04
0375 
0376 #define PCXHR_IRQ_TIMER_FREQ        92000
0377 #define PCXHR_IRQ_TIMER_PERIOD      48
0378 
0379 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
0380 {
0381     struct pcxhr_rmh rmh;
0382     int err, changed;
0383 
0384     if (rate == 0)
0385         return 0; /* nothing to do */
0386 
0387     if (mgr->is_hr_stereo)
0388         err = hr222_sub_set_clock(mgr, rate, &changed);
0389     else
0390         err = pcxhr_sub_set_clock(mgr, rate, &changed);
0391 
0392     if (err)
0393         return err;
0394 
0395     if (changed) {
0396         pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
0397         rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos  */
0398         if (rate < PCXHR_IRQ_TIMER_FREQ)
0399             rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
0400         else
0401             rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
0402         rmh.cmd[2] = rate;
0403         rmh.cmd_len = 3;
0404         err = pcxhr_send_msg(mgr, &rmh);
0405         if (err)
0406             return err;
0407     }
0408     return 0;
0409 }
0410 
0411 
0412 static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
0413                     enum pcxhr_clock_type clock_type,
0414                     int *sample_rate)
0415 {
0416     struct pcxhr_rmh rmh;
0417     unsigned char reg;
0418     int err, rate;
0419 
0420     switch (clock_type) {
0421     case PCXHR_CLOCK_TYPE_WORD_CLOCK:
0422         reg = REG_STATUS_WORD_CLOCK;
0423         break;
0424     case PCXHR_CLOCK_TYPE_AES_SYNC:
0425         reg = REG_STATUS_AES_SYNC;
0426         break;
0427     case PCXHR_CLOCK_TYPE_AES_1:
0428         reg = REG_STATUS_AES_1;
0429         break;
0430     case PCXHR_CLOCK_TYPE_AES_2:
0431         reg = REG_STATUS_AES_2;
0432         break;
0433     case PCXHR_CLOCK_TYPE_AES_3:
0434         reg = REG_STATUS_AES_3;
0435         break;
0436     case PCXHR_CLOCK_TYPE_AES_4:
0437         reg = REG_STATUS_AES_4;
0438         break;
0439     default:
0440         return -EINVAL;
0441     }
0442     pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
0443     rmh.cmd_len = 2;
0444     rmh.cmd[0] |= IO_NUM_REG_STATUS;
0445     if (mgr->last_reg_stat != reg) {
0446         rmh.cmd[1]  = reg;
0447         err = pcxhr_send_msg(mgr, &rmh);
0448         if (err)
0449             return err;
0450         udelay(100);    /* wait minimum 2 sample_frames at 32kHz ! */
0451         mgr->last_reg_stat = reg;
0452     }
0453     rmh.cmd[1]  = REG_STATUS_CURRENT;
0454     err = pcxhr_send_msg(mgr, &rmh);
0455     if (err)
0456         return err;
0457     switch (rmh.stat[1] & 0x0f) {
0458     case REG_STATUS_SYNC_32000 :    rate = 32000; break;
0459     case REG_STATUS_SYNC_44100 :    rate = 44100; break;
0460     case REG_STATUS_SYNC_48000 :    rate = 48000; break;
0461     case REG_STATUS_SYNC_64000 :    rate = 64000; break;
0462     case REG_STATUS_SYNC_88200 :    rate = 88200; break;
0463     case REG_STATUS_SYNC_96000 :    rate = 96000; break;
0464     case REG_STATUS_SYNC_128000 :   rate = 128000; break;
0465     case REG_STATUS_SYNC_176400 :   rate = 176400; break;
0466     case REG_STATUS_SYNC_192000 :   rate = 192000; break;
0467     default: rate = 0;
0468     }
0469     dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate);
0470     *sample_rate = rate;
0471     return 0;
0472 }
0473 
0474 
0475 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
0476                  enum pcxhr_clock_type clock_type,
0477                  int *sample_rate)
0478 {
0479     if (mgr->is_hr_stereo)
0480         return hr222_get_external_clock(mgr, clock_type,
0481                         sample_rate);
0482     else
0483         return pcxhr_sub_get_external_clock(mgr, clock_type,
0484                             sample_rate);
0485 }
0486 
0487 /*
0488  *  start or stop playback/capture substream
0489  */
0490 static int pcxhr_set_stream_state(struct snd_pcxhr *chip,
0491                   struct pcxhr_stream *stream)
0492 {
0493     int err;
0494     struct pcxhr_rmh rmh;
0495     int stream_mask, start;
0496 
0497     if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
0498         start = 1;
0499     else {
0500         if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
0501             dev_err(chip->card->dev,
0502                 "%s CANNOT be stopped\n", __func__);
0503             return -EINVAL;
0504         }
0505         start = 0;
0506     }
0507     if (!stream->substream)
0508         return -EINVAL;
0509 
0510     stream->timer_abs_periods = 0;
0511     stream->timer_period_frag = 0;  /* reset theoretical stream pos */
0512     stream->timer_buf_periods = 0;
0513     stream->timer_is_synced = 0;
0514 
0515     stream_mask =
0516       stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
0517 
0518     pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
0519     pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
0520                   stream->pipe->first_audio, 0, stream_mask);
0521 
0522     chip = snd_pcm_substream_chip(stream->substream);
0523 
0524     err = pcxhr_send_msg(chip->mgr, &rmh);
0525     if (err)
0526         dev_err(chip->card->dev,
0527             "ERROR %s err=%x;\n", __func__, err);
0528     stream->status =
0529       start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
0530     return err;
0531 }
0532 
0533 #define HEADER_FMT_BASE_LIN     0xfed00000
0534 #define HEADER_FMT_BASE_FLOAT       0xfad00000
0535 #define HEADER_FMT_INTEL        0x00008000
0536 #define HEADER_FMT_24BITS       0x00004000
0537 #define HEADER_FMT_16BITS       0x00002000
0538 #define HEADER_FMT_UPTO11       0x00000200
0539 #define HEADER_FMT_UPTO32       0x00000100
0540 #define HEADER_FMT_MONO         0x00000080
0541 
0542 static int pcxhr_set_format(struct pcxhr_stream *stream)
0543 {
0544     int err, is_capture, sample_rate, stream_num;
0545     struct snd_pcxhr *chip;
0546     struct pcxhr_rmh rmh;
0547     unsigned int header;
0548 
0549     chip = snd_pcm_substream_chip(stream->substream);
0550     switch (stream->format) {
0551     case SNDRV_PCM_FORMAT_U8:
0552         header = HEADER_FMT_BASE_LIN;
0553         break;
0554     case SNDRV_PCM_FORMAT_S16_LE:
0555         header = HEADER_FMT_BASE_LIN |
0556              HEADER_FMT_16BITS | HEADER_FMT_INTEL;
0557         break;
0558     case SNDRV_PCM_FORMAT_S16_BE:
0559         header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
0560         break;
0561     case SNDRV_PCM_FORMAT_S24_3LE:
0562         header = HEADER_FMT_BASE_LIN |
0563              HEADER_FMT_24BITS | HEADER_FMT_INTEL;
0564         break;
0565     case SNDRV_PCM_FORMAT_S24_3BE:
0566         header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
0567         break;
0568     case SNDRV_PCM_FORMAT_FLOAT_LE:
0569         header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
0570         break;
0571     default:
0572         dev_err(chip->card->dev,
0573             "error %s() : unknown format\n", __func__);
0574         return -EINVAL;
0575     }
0576 
0577     sample_rate = chip->mgr->sample_rate;
0578     if (sample_rate <= 32000 && sample_rate !=0) {
0579         if (sample_rate <= 11025)
0580             header |= HEADER_FMT_UPTO11;
0581         else
0582             header |= HEADER_FMT_UPTO32;
0583     }
0584     if (stream->channels == 1)
0585         header |= HEADER_FMT_MONO;
0586 
0587     is_capture = stream->pipe->is_capture;
0588     stream_num = is_capture ? 0 : stream->substream->number;
0589 
0590     pcxhr_init_rmh(&rmh, is_capture ?
0591                CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
0592     pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
0593                   stream_num, 0);
0594     if (is_capture) {
0595         /* bug with old dsp versions: */
0596         /* bit 12 also sets the format of the playback stream */
0597         if (DSP_EXT_CMD_SET(chip->mgr))
0598             rmh.cmd[0] |= 1<<10;
0599         else
0600             rmh.cmd[0] |= 1<<12;
0601     }
0602     rmh.cmd[1] = 0;
0603     rmh.cmd_len = 2;
0604     if (DSP_EXT_CMD_SET(chip->mgr)) {
0605         /* add channels and set bit 19 if channels>2 */
0606         rmh.cmd[1] = stream->channels;
0607         if (!is_capture) {
0608             /* playback : add channel mask to command */
0609             rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
0610             rmh.cmd_len = 3;
0611         }
0612     }
0613     rmh.cmd[rmh.cmd_len++] = header >> 8;
0614     rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
0615     err = pcxhr_send_msg(chip->mgr, &rmh);
0616     if (err)
0617         dev_err(chip->card->dev,
0618             "ERROR %s err=%x;\n", __func__, err);
0619     return err;
0620 }
0621 
0622 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
0623 {
0624     int err, is_capture, stream_num;
0625     struct pcxhr_rmh rmh;
0626     struct snd_pcm_substream *subs = stream->substream;
0627     struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
0628 
0629     is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
0630     stream_num = is_capture ? 0 : subs->number;
0631 
0632     dev_dbg(chip->card->dev,
0633         "%s(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", __func__,
0634         is_capture ? 'c' : 'p',
0635         chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
0636         subs->runtime->dma_bytes, subs->number);
0637 
0638     pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
0639     pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
0640                   stream_num, 0);
0641 
0642     /* max buffer size is 2 MByte */
0643     snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
0644     /* size in bits */
0645     rmh.cmd[1] = subs->runtime->dma_bytes * 8;
0646     /* most significant byte */
0647     rmh.cmd[2] = subs->runtime->dma_addr >> 24;
0648     /* this is a circular buffer */
0649     rmh.cmd[2] |= 1<<19;
0650     /* least 3 significant bytes */
0651     rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
0652     rmh.cmd_len = 4;
0653     err = pcxhr_send_msg(chip->mgr, &rmh);
0654     if (err)
0655         dev_err(chip->card->dev,
0656                "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
0657     return err;
0658 }
0659 
0660 
0661 #if 0
0662 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
0663                    snd_pcm_uframes_t *sample_count)
0664 {
0665     struct pcxhr_rmh rmh;
0666     int err;
0667     pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
0668     pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
0669     pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
0670                   1<<stream->pipe->first_audio);
0671     err = pcxhr_send_msg(chip->mgr, &rmh);
0672     if (err == 0) {
0673         *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
0674         *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
0675     }
0676     dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
0677     return err;
0678 }
0679 #endif
0680 
0681 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
0682                           struct pcxhr_pipe **pipe)
0683 {
0684     if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
0685         *pipe = stream->pipe;
0686         return 1;
0687     }
0688     return 0;
0689 }
0690 
0691 static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr)
0692 {
0693     int i, j, err;
0694     struct pcxhr_pipe *pipe;
0695     struct snd_pcxhr *chip;
0696     int capture_mask = 0;
0697     int playback_mask = 0;
0698 
0699 #ifdef CONFIG_SND_DEBUG_VERBOSE
0700     ktime_t start_time, stop_time, diff_time;
0701 
0702     start_time = ktime_get();
0703 #endif
0704     mutex_lock(&mgr->setup_mutex);
0705 
0706     /* check the pipes concerned and build pipe_array */
0707     for (i = 0; i < mgr->num_cards; i++) {
0708         chip = mgr->chip[i];
0709         for (j = 0; j < chip->nb_streams_capt; j++) {
0710             if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
0711                 capture_mask |= (1 << pipe->first_audio);
0712         }
0713         for (j = 0; j < chip->nb_streams_play; j++) {
0714             if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
0715                 playback_mask |= (1 << pipe->first_audio);
0716                 break;  /* add only once, as all playback
0717                      * streams of one chip use the same pipe
0718                      */
0719             }
0720         }
0721     }
0722     if (capture_mask == 0 && playback_mask == 0) {
0723         mutex_unlock(&mgr->setup_mutex);
0724         dev_err(&mgr->pci->dev, "%s : no pipes\n", __func__);
0725         return;
0726     }
0727 
0728     dev_dbg(&mgr->pci->dev, "%s : playback_mask=%x capture_mask=%x\n",
0729             __func__, playback_mask, capture_mask);
0730 
0731     /* synchronous stop of all the pipes concerned */
0732     err = pcxhr_set_pipe_state(mgr,  playback_mask, capture_mask, 0);
0733     if (err) {
0734         mutex_unlock(&mgr->setup_mutex);
0735         dev_err(&mgr->pci->dev, "%s : "
0736                "error stop pipes (P%x C%x)\n",
0737                __func__, playback_mask, capture_mask);
0738         return;
0739     }
0740 
0741     /* the dsp lost format and buffer info with the stop pipe */
0742     for (i = 0; i < mgr->num_cards; i++) {
0743         struct pcxhr_stream *stream;
0744         chip = mgr->chip[i];
0745         for (j = 0; j < chip->nb_streams_capt; j++) {
0746             stream = &chip->capture_stream[j];
0747             if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
0748                 err = pcxhr_set_format(stream);
0749                 err = pcxhr_update_r_buffer(stream);
0750             }
0751         }
0752         for (j = 0; j < chip->nb_streams_play; j++) {
0753             stream = &chip->playback_stream[j];
0754             if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
0755                 err = pcxhr_set_format(stream);
0756                 err = pcxhr_update_r_buffer(stream);
0757             }
0758         }
0759     }
0760     /* start all the streams */
0761     for (i = 0; i < mgr->num_cards; i++) {
0762         struct pcxhr_stream *stream;
0763         chip = mgr->chip[i];
0764         for (j = 0; j < chip->nb_streams_capt; j++) {
0765             stream = &chip->capture_stream[j];
0766             if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
0767                 err = pcxhr_set_stream_state(chip, stream);
0768         }
0769         for (j = 0; j < chip->nb_streams_play; j++) {
0770             stream = &chip->playback_stream[j];
0771             if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
0772                 err = pcxhr_set_stream_state(chip, stream);
0773         }
0774     }
0775 
0776     /* synchronous start of all the pipes concerned */
0777     err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
0778     if (err) {
0779         mutex_unlock(&mgr->setup_mutex);
0780         dev_err(&mgr->pci->dev, "%s : "
0781                "error start pipes (P%x C%x)\n",
0782                __func__, playback_mask, capture_mask);
0783         return;
0784     }
0785 
0786     /* put the streams into the running state now
0787      * (increment pointer by interrupt)
0788      */
0789     mutex_lock(&mgr->lock);
0790     for ( i =0; i < mgr->num_cards; i++) {
0791         struct pcxhr_stream *stream;
0792         chip = mgr->chip[i];
0793         for(j = 0; j < chip->nb_streams_capt; j++) {
0794             stream = &chip->capture_stream[j];
0795             if(stream->status == PCXHR_STREAM_STATUS_STARTED)
0796                 stream->status = PCXHR_STREAM_STATUS_RUNNING;
0797         }
0798         for (j = 0; j < chip->nb_streams_play; j++) {
0799             stream = &chip->playback_stream[j];
0800             if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
0801                 /* playback will already have advanced ! */
0802                 stream->timer_period_frag += mgr->granularity;
0803                 stream->status = PCXHR_STREAM_STATUS_RUNNING;
0804             }
0805         }
0806     }
0807     mutex_unlock(&mgr->lock);
0808 
0809     mutex_unlock(&mgr->setup_mutex);
0810 
0811 #ifdef CONFIG_SND_DEBUG_VERBOSE
0812     stop_time = ktime_get();
0813     diff_time = ktime_sub(stop_time, start_time);
0814     dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n",
0815             (long)(ktime_to_ns(diff_time)), err);
0816 #endif
0817 }
0818 
0819 
0820 /*
0821  *  trigger callback
0822  */
0823 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
0824 {
0825     struct pcxhr_stream *stream;
0826     struct snd_pcm_substream *s;
0827     struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
0828 
0829     switch (cmd) {
0830     case SNDRV_PCM_TRIGGER_START:
0831         dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n");
0832         if (snd_pcm_stream_linked(subs)) {
0833             snd_pcm_group_for_each_entry(s, subs) {
0834                 if (snd_pcm_substream_chip(s) != chip)
0835                     continue;
0836                 stream = s->runtime->private_data;
0837                 stream->status =
0838                     PCXHR_STREAM_STATUS_SCHEDULE_RUN;
0839                 snd_pcm_trigger_done(s, subs);
0840             }
0841             pcxhr_start_linked_stream(chip->mgr);
0842         } else {
0843             stream = subs->runtime->private_data;
0844             dev_dbg(chip->card->dev, "Only one Substream %c %d\n",
0845                     stream->pipe->is_capture ? 'C' : 'P',
0846                     stream->pipe->first_audio);
0847             if (pcxhr_set_format(stream))
0848                 return -EINVAL;
0849             if (pcxhr_update_r_buffer(stream))
0850                 return -EINVAL;
0851 
0852             stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
0853             if (pcxhr_set_stream_state(chip, stream))
0854                 return -EINVAL;
0855             stream->status = PCXHR_STREAM_STATUS_RUNNING;
0856         }
0857         break;
0858     case SNDRV_PCM_TRIGGER_STOP:
0859         dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n");
0860         snd_pcm_group_for_each_entry(s, subs) {
0861             stream = s->runtime->private_data;
0862             stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
0863             if (pcxhr_set_stream_state(chip, stream))
0864                 return -EINVAL;
0865             snd_pcm_trigger_done(s, subs);
0866         }
0867         break;
0868     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0869     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0870         /* TODO */
0871     default:
0872         return -EINVAL;
0873     }
0874     return 0;
0875 }
0876 
0877 
0878 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
0879 {
0880     struct pcxhr_rmh rmh;
0881     int err;
0882 
0883     pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
0884     if (start) {
0885         /* last dsp time invalid */
0886         mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
0887         rmh.cmd[0] |= mgr->granularity;
0888     }
0889     err = pcxhr_send_msg(mgr, &rmh);
0890     if (err < 0)
0891         dev_err(&mgr->pci->dev, "error %s err(%x)\n", __func__,
0892                err);
0893     return err;
0894 }
0895 
0896 /*
0897  *  prepare callback for all pcms
0898  */
0899 static int pcxhr_prepare(struct snd_pcm_substream *subs)
0900 {
0901     struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
0902     struct pcxhr_mgr *mgr = chip->mgr;
0903     int err = 0;
0904 
0905     dev_dbg(chip->card->dev,
0906         "%s : period_size(%lx) periods(%x) buffer_size(%lx)\n", __func__,
0907             subs->runtime->period_size, subs->runtime->periods,
0908             subs->runtime->buffer_size);
0909 
0910     mutex_lock(&mgr->setup_mutex);
0911 
0912     do {
0913         /* only the first stream can choose the sample rate */
0914         /* set the clock only once (first stream) */
0915         if (mgr->sample_rate != subs->runtime->rate) {
0916             err = pcxhr_set_clock(mgr, subs->runtime->rate);
0917             if (err)
0918                 break;
0919             if (mgr->sample_rate == 0)
0920                 /* start the DSP-timer */
0921                 err = pcxhr_hardware_timer(mgr, 1);
0922             mgr->sample_rate = subs->runtime->rate;
0923         }
0924     } while(0); /* do only once (so we can use break instead of goto) */
0925 
0926     mutex_unlock(&mgr->setup_mutex);
0927 
0928     return err;
0929 }
0930 
0931 
0932 /*
0933  *  HW_PARAMS callback for all pcms
0934  */
0935 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
0936                struct snd_pcm_hw_params *hw)
0937 {
0938     struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
0939     struct pcxhr_mgr *mgr = chip->mgr;
0940     struct pcxhr_stream *stream = subs->runtime->private_data;
0941 
0942     mutex_lock(&mgr->setup_mutex);
0943 
0944     /* set up channels */
0945     stream->channels = params_channels(hw);
0946     /* set up format for the stream */
0947     stream->format = params_format(hw);
0948 
0949     mutex_unlock(&mgr->setup_mutex);
0950 
0951     return 0;
0952 }
0953 
0954 
0955 /*
0956  *  CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
0957  */
0958 static const struct snd_pcm_hardware pcxhr_caps =
0959 {
0960     .info             = (SNDRV_PCM_INFO_MMAP |
0961                  SNDRV_PCM_INFO_INTERLEAVED |
0962                  SNDRV_PCM_INFO_MMAP_VALID |
0963                  SNDRV_PCM_INFO_SYNC_START),
0964     .formats      = (SNDRV_PCM_FMTBIT_U8 |
0965                  SNDRV_PCM_FMTBIT_S16_LE |
0966                  SNDRV_PCM_FMTBIT_S16_BE |
0967                  SNDRV_PCM_FMTBIT_S24_3LE |
0968                  SNDRV_PCM_FMTBIT_S24_3BE |
0969                  SNDRV_PCM_FMTBIT_FLOAT_LE),
0970     .rates            = (SNDRV_PCM_RATE_CONTINUOUS |
0971                  SNDRV_PCM_RATE_8000_192000),
0972     .rate_min         = 8000,
0973     .rate_max         = 192000,
0974     .channels_min     = 1,
0975     .channels_max     = 2,
0976     .buffer_bytes_max = (32*1024),
0977     /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
0978     .period_bytes_min = (2*PCXHR_GRANULARITY),
0979     .period_bytes_max = (16*1024),
0980     .periods_min      = 2,
0981     .periods_max      = (32*1024/PCXHR_GRANULARITY),
0982 };
0983 
0984 
0985 static int pcxhr_open(struct snd_pcm_substream *subs)
0986 {
0987     struct snd_pcxhr       *chip = snd_pcm_substream_chip(subs);
0988     struct pcxhr_mgr       *mgr = chip->mgr;
0989     struct snd_pcm_runtime *runtime = subs->runtime;
0990     struct pcxhr_stream    *stream;
0991     int err;
0992 
0993     mutex_lock(&mgr->setup_mutex);
0994 
0995     /* copy the struct snd_pcm_hardware struct */
0996     runtime->hw = pcxhr_caps;
0997 
0998     if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
0999         dev_dbg(chip->card->dev, "%s playback chip%d subs%d\n",
1000                 __func__, chip->chip_idx, subs->number);
1001         stream = &chip->playback_stream[subs->number];
1002     } else {
1003         dev_dbg(chip->card->dev, "%s capture chip%d subs%d\n",
1004                 __func__, chip->chip_idx, subs->number);
1005         if (mgr->mono_capture)
1006             runtime->hw.channels_max = 1;
1007         else
1008             runtime->hw.channels_min = 2;
1009         stream = &chip->capture_stream[subs->number];
1010     }
1011     if (stream->status != PCXHR_STREAM_STATUS_FREE){
1012         /* streams in use */
1013         dev_err(chip->card->dev, "%s chip%d subs%d in use\n",
1014                __func__, chip->chip_idx, subs->number);
1015         mutex_unlock(&mgr->setup_mutex);
1016         return -EBUSY;
1017     }
1018 
1019     /* float format support is in some cases buggy on stereo cards */
1020     if (mgr->is_hr_stereo)
1021         runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1022 
1023     /* buffer-size should better be multiple of period-size */
1024     err = snd_pcm_hw_constraint_integer(runtime,
1025                         SNDRV_PCM_HW_PARAM_PERIODS);
1026     if (err < 0) {
1027         mutex_unlock(&mgr->setup_mutex);
1028         return err;
1029     }
1030 
1031     /* if a sample rate is already used or fixed by external clock,
1032      * the stream cannot change
1033      */
1034     if (mgr->sample_rate)
1035         runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
1036     else {
1037         if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
1038             int external_rate;
1039             if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
1040                              &external_rate) ||
1041                 external_rate == 0) {
1042                 /* cannot detect the external clock rate */
1043                 mutex_unlock(&mgr->setup_mutex);
1044                 return -EBUSY;
1045             }
1046             runtime->hw.rate_min = external_rate;
1047             runtime->hw.rate_max = external_rate;
1048         }
1049     }
1050 
1051     stream->status      = PCXHR_STREAM_STATUS_OPEN;
1052     stream->substream   = subs;
1053     stream->channels    = 0; /* not configured yet */
1054 
1055     runtime->private_data = stream;
1056 
1057     /* better get a divisor of granularity values (96 or 192) */
1058     snd_pcm_hw_constraint_step(runtime, 0,
1059                    SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
1060     snd_pcm_hw_constraint_step(runtime, 0,
1061                    SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
1062     snd_pcm_set_sync(subs);
1063 
1064     mgr->ref_count_rate++;
1065 
1066     mutex_unlock(&mgr->setup_mutex);
1067     return 0;
1068 }
1069 
1070 
1071 static int pcxhr_close(struct snd_pcm_substream *subs)
1072 {
1073     struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1074     struct pcxhr_mgr *mgr = chip->mgr;
1075     struct pcxhr_stream *stream = subs->runtime->private_data;
1076 
1077     mutex_lock(&mgr->setup_mutex);
1078 
1079     dev_dbg(chip->card->dev, "%s chip%d subs%d\n", __func__,
1080             chip->chip_idx, subs->number);
1081 
1082     /* sample rate released */
1083     if (--mgr->ref_count_rate == 0) {
1084         mgr->sample_rate = 0;   /* the sample rate is no more locked */
1085         pcxhr_hardware_timer(mgr, 0);   /* stop the DSP-timer */
1086     }
1087 
1088     stream->status    = PCXHR_STREAM_STATUS_FREE;
1089     stream->substream = NULL;
1090 
1091     mutex_unlock(&mgr->setup_mutex);
1092 
1093     return 0;
1094 }
1095 
1096 
1097 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
1098 {
1099     u_int32_t timer_period_frag;
1100     int timer_buf_periods;
1101     struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1102     struct snd_pcm_runtime *runtime = subs->runtime;
1103     struct pcxhr_stream *stream  = runtime->private_data;
1104 
1105     mutex_lock(&chip->mgr->lock);
1106 
1107     /* get the period fragment and the nb of periods in the buffer */
1108     timer_period_frag = stream->timer_period_frag;
1109     timer_buf_periods = stream->timer_buf_periods;
1110 
1111     mutex_unlock(&chip->mgr->lock);
1112 
1113     return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
1114                    timer_period_frag);
1115 }
1116 
1117 
1118 static const struct snd_pcm_ops pcxhr_ops = {
1119     .open      = pcxhr_open,
1120     .close     = pcxhr_close,
1121     .prepare   = pcxhr_prepare,
1122     .hw_params = pcxhr_hw_params,
1123     .trigger   = pcxhr_trigger,
1124     .pointer   = pcxhr_stream_pointer,
1125 };
1126 
1127 /*
1128  */
1129 int pcxhr_create_pcm(struct snd_pcxhr *chip)
1130 {
1131     int err;
1132     struct snd_pcm *pcm;
1133     char name[32];
1134 
1135     snprintf(name, sizeof(name), "pcxhr %d", chip->chip_idx);
1136     err = snd_pcm_new(chip->card, name, 0,
1137               chip->nb_streams_play,
1138               chip->nb_streams_capt, &pcm);
1139     if (err < 0) {
1140         dev_err(chip->card->dev, "cannot create pcm %s\n", name);
1141         return err;
1142     }
1143     pcm->private_data = chip;
1144 
1145     if (chip->nb_streams_play)
1146         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
1147     if (chip->nb_streams_capt)
1148         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
1149 
1150     pcm->info_flags = 0;
1151     pcm->nonatomic = true;
1152     strcpy(pcm->name, name);
1153 
1154     snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1155                        &chip->mgr->pci->dev,
1156                        32*1024, 32*1024);
1157     chip->pcm = pcm;
1158     return 0;
1159 }
1160 
1161 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1162 {
1163     kfree(chip);
1164     return 0;
1165 }
1166 
1167 static int pcxhr_chip_dev_free(struct snd_device *device)
1168 {
1169     struct snd_pcxhr *chip = device->device_data;
1170     return pcxhr_chip_free(chip);
1171 }
1172 
1173 
1174 /*
1175  */
1176 static int pcxhr_create(struct pcxhr_mgr *mgr,
1177             struct snd_card *card, int idx)
1178 {
1179     int err;
1180     struct snd_pcxhr *chip;
1181     static const struct snd_device_ops ops = {
1182         .dev_free = pcxhr_chip_dev_free,
1183     };
1184 
1185     chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1186     if (!chip)
1187         return -ENOMEM;
1188 
1189     chip->card = card;
1190     chip->chip_idx = idx;
1191     chip->mgr = mgr;
1192     card->sync_irq = mgr->irq;
1193 
1194     if (idx < mgr->playback_chips)
1195         /* stereo or mono streams */
1196         chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1197 
1198     if (idx < mgr->capture_chips) {
1199         if (mgr->mono_capture)
1200             chip->nb_streams_capt = 2;  /* 2 mono streams */
1201         else
1202             chip->nb_streams_capt = 1;  /* or 1 stereo stream */
1203     }
1204 
1205     err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1206     if (err < 0) {
1207         pcxhr_chip_free(chip);
1208         return err;
1209     }
1210 
1211     mgr->chip[idx] = chip;
1212 
1213     return 0;
1214 }
1215 
1216 /* proc interface */
1217 static void pcxhr_proc_info(struct snd_info_entry *entry,
1218                 struct snd_info_buffer *buffer)
1219 {
1220     struct snd_pcxhr *chip = entry->private_data;
1221     struct pcxhr_mgr *mgr = chip->mgr;
1222 
1223     snd_iprintf(buffer, "\n%s\n", mgr->name);
1224 
1225     /* stats available when embedded DSP is running */
1226     if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1227         struct pcxhr_rmh rmh;
1228         short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1229         short ver_min = (mgr->dsp_version >> 8) & 0xff;
1230         short ver_build = mgr->dsp_version & 0xff;
1231         snd_iprintf(buffer, "module version %s\n",
1232                 PCXHR_DRIVER_VERSION_STRING);
1233         snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1234                 ver_maj, ver_min, ver_build);
1235         if (mgr->board_has_analog)
1236             snd_iprintf(buffer, "analog io available\n");
1237         else
1238             snd_iprintf(buffer, "digital only board\n");
1239 
1240         /* calc cpu load of the dsp */
1241         pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1242         if( ! pcxhr_send_msg(mgr, &rmh) ) {
1243             int cur = rmh.stat[0];
1244             int ref = rmh.stat[1];
1245             if (ref > 0) {
1246                 if (mgr->sample_rate_real != 0 &&
1247                     mgr->sample_rate_real != 48000) {
1248                     ref = (ref * 48000) /
1249                       mgr->sample_rate_real;
1250                     if (mgr->sample_rate_real >=
1251                         PCXHR_IRQ_TIMER_FREQ)
1252                         ref *= 2;
1253                 }
1254                 cur = 100 - (100 * cur) / ref;
1255                 snd_iprintf(buffer, "cpu load    %d%%\n", cur);
1256                 snd_iprintf(buffer, "buffer pool %d/%d\n",
1257                         rmh.stat[2], rmh.stat[3]);
1258             }
1259         }
1260         snd_iprintf(buffer, "dma granularity : %d\n",
1261                 mgr->granularity);
1262         snd_iprintf(buffer, "dsp time errors : %d\n",
1263                 mgr->dsp_time_err);
1264         snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1265                 mgr->async_err_pipe_xrun);
1266         snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1267                 mgr->async_err_stream_xrun);
1268         snd_iprintf(buffer, "dsp async last other error : %x\n",
1269                 mgr->async_err_other_last);
1270         /* debug zone dsp */
1271         rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1272         rmh.cmd_len = 1;
1273         rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1274         rmh.dsp_stat = 0;
1275         rmh.cmd_idx = CMD_LAST_INDEX;
1276         if( ! pcxhr_send_msg(mgr, &rmh) ) {
1277             int i;
1278             if (rmh.stat_len > 8)
1279                 rmh.stat_len = 8;
1280             for (i = 0; i < rmh.stat_len; i++)
1281                 snd_iprintf(buffer, "debug[%02d] = %06x\n",
1282                         i,  rmh.stat[i]);
1283         }
1284     } else
1285         snd_iprintf(buffer, "no firmware loaded\n");
1286     snd_iprintf(buffer, "\n");
1287 }
1288 static void pcxhr_proc_sync(struct snd_info_entry *entry,
1289                 struct snd_info_buffer *buffer)
1290 {
1291     struct snd_pcxhr *chip = entry->private_data;
1292     struct pcxhr_mgr *mgr = chip->mgr;
1293     static const char *textsHR22[3] = {
1294         "Internal", "AES Sync", "AES 1"
1295     };
1296     static const char *textsPCXHR[7] = {
1297         "Internal", "Word", "AES Sync",
1298         "AES 1", "AES 2", "AES 3", "AES 4"
1299     };
1300     const char **texts;
1301     int max_clock;
1302     if (mgr->is_hr_stereo) {
1303         texts = textsHR22;
1304         max_clock = HR22_CLOCK_TYPE_MAX;
1305     } else {
1306         texts = textsPCXHR;
1307         max_clock = PCXHR_CLOCK_TYPE_MAX;
1308     }
1309 
1310     snd_iprintf(buffer, "\n%s\n", mgr->name);
1311     snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1312             texts[mgr->cur_clock_type]);
1313     snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1314             mgr->sample_rate_real);
1315     /* commands available when embedded DSP is running */
1316     if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1317         int i, err, sample_rate;
1318         for (i = 1; i <= max_clock; i++) {
1319             err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1320             if (err)
1321                 break;
1322             snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1323                     texts[i], sample_rate);
1324         }
1325     } else
1326         snd_iprintf(buffer, "no firmware loaded\n");
1327     snd_iprintf(buffer, "\n");
1328 }
1329 
1330 static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
1331                  struct snd_info_buffer *buffer)
1332 {
1333     struct snd_pcxhr *chip = entry->private_data;
1334     struct pcxhr_mgr *mgr = chip->mgr;
1335     /* commands available when embedded DSP is running */
1336     if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1337         /* gpio ports on stereo boards only available */
1338         int value = 0;
1339         hr222_read_gpio(mgr, 1, &value);    /* GPI */
1340         snd_iprintf(buffer, "GPI: 0x%x\n", value);
1341         hr222_read_gpio(mgr, 0, &value);    /* GP0 */
1342         snd_iprintf(buffer, "GPO: 0x%x\n", value);
1343     } else
1344         snd_iprintf(buffer, "no firmware loaded\n");
1345     snd_iprintf(buffer, "\n");
1346 }
1347 static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
1348                  struct snd_info_buffer *buffer)
1349 {
1350     struct snd_pcxhr *chip = entry->private_data;
1351     struct pcxhr_mgr *mgr = chip->mgr;
1352     char line[64];
1353     int value;
1354     /* commands available when embedded DSP is running */
1355     if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
1356         return;
1357     while (!snd_info_get_line(buffer, line, sizeof(line))) {
1358         if (sscanf(line, "GPO: 0x%x", &value) != 1)
1359             continue;
1360         hr222_write_gpo(mgr, value);    /* GP0 */
1361     }
1362 }
1363 
1364 /* Access to the results of the CMD_GET_TIME_CODE RMH */
1365 #define TIME_CODE_VALID_MASK    0x00800000
1366 #define TIME_CODE_NEW_MASK  0x00400000
1367 #define TIME_CODE_BACK_MASK 0x00200000
1368 #define TIME_CODE_WAIT_MASK 0x00100000
1369 
1370 /* Values for the CMD_MANAGE_SIGNAL RMH */
1371 #define MANAGE_SIGNAL_TIME_CODE 0x01
1372 #define MANAGE_SIGNAL_MIDI  0x02
1373 
1374 /* linear time code read proc*/
1375 static void pcxhr_proc_ltc(struct snd_info_entry *entry,
1376                struct snd_info_buffer *buffer)
1377 {
1378     struct snd_pcxhr *chip = entry->private_data;
1379     struct pcxhr_mgr *mgr = chip->mgr;
1380     struct pcxhr_rmh rmh;
1381     unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm;
1382     int err;
1383     /* commands available when embedded DSP is running */
1384     if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) {
1385         snd_iprintf(buffer, "no firmware loaded\n");
1386         return;
1387     }
1388     if (!mgr->capture_ltc) {
1389         pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL);
1390         rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE;
1391         err = pcxhr_send_msg(mgr, &rmh);
1392         if (err) {
1393             snd_iprintf(buffer, "ltc not activated (%d)\n", err);
1394             return;
1395         }
1396         if (mgr->is_hr_stereo)
1397             hr222_manage_timecode(mgr, 1);
1398         else
1399             pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE,
1400                             REG_CONT_VALSMPTE, NULL);
1401         mgr->capture_ltc = 1;
1402     }
1403     pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE);
1404     err = pcxhr_send_msg(mgr, &rmh);
1405     if (err) {
1406         snd_iprintf(buffer, "ltc read error (err=%d)\n", err);
1407         return ;
1408     }
1409     ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf);
1410     ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf);
1411     ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf);
1412     ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf);
1413 
1414     snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n",
1415                 ltcHrs, ltcMin, ltcSec, ltcFrm);
1416     snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff,
1417                 rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff);
1418     /*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n",
1419                 rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/
1420     if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) {
1421         snd_iprintf(buffer, "warning: linear timecode not valid\n");
1422     }
1423 }
1424 
1425 static void pcxhr_proc_init(struct snd_pcxhr *chip)
1426 {
1427     snd_card_ro_proc_new(chip->card, "info", chip, pcxhr_proc_info);
1428     snd_card_ro_proc_new(chip->card, "sync", chip, pcxhr_proc_sync);
1429     /* gpio available on stereo sound cards only */
1430     if (chip->mgr->is_hr_stereo)
1431         snd_card_rw_proc_new(chip->card, "gpio", chip,
1432                      pcxhr_proc_gpio_read,
1433                      pcxhr_proc_gpo_write);
1434     snd_card_ro_proc_new(chip->card, "ltc", chip, pcxhr_proc_ltc);
1435 }
1436 /* end of proc interface */
1437 
1438 /*
1439  * release all the cards assigned to a manager instance
1440  */
1441 static int pcxhr_free(struct pcxhr_mgr *mgr)
1442 {
1443     unsigned int i;
1444 
1445     for (i = 0; i < mgr->num_cards; i++) {
1446         if (mgr->chip[i])
1447             snd_card_free(mgr->chip[i]->card);
1448     }
1449 
1450     /* reset board if some firmware was loaded */
1451     if(mgr->dsp_loaded) {
1452         pcxhr_reset_board(mgr);
1453         dev_dbg(&mgr->pci->dev, "reset pcxhr !\n");
1454     }
1455 
1456     /* release irq  */
1457     if (mgr->irq >= 0)
1458         free_irq(mgr->irq, mgr);
1459 
1460     pci_release_regions(mgr->pci);
1461 
1462     /* free hostport purgebuffer */
1463     if (mgr->hostport.area) {
1464         snd_dma_free_pages(&mgr->hostport);
1465         mgr->hostport.area = NULL;
1466     }
1467 
1468     kfree(mgr->prmh);
1469 
1470     pci_disable_device(mgr->pci);
1471     kfree(mgr);
1472     return 0;
1473 }
1474 
1475 /*
1476  *    probe function - creates the card manager
1477  */
1478 static int pcxhr_probe(struct pci_dev *pci,
1479                const struct pci_device_id *pci_id)
1480 {
1481     static int dev;
1482     struct pcxhr_mgr *mgr;
1483     unsigned int i;
1484     int err;
1485     size_t size;
1486     char *card_name;
1487 
1488     if (dev >= SNDRV_CARDS)
1489         return -ENODEV;
1490     if (! enable[dev]) {
1491         dev++;
1492         return -ENOENT;
1493     }
1494 
1495     /* enable PCI device */
1496     err = pci_enable_device(pci);
1497     if (err < 0)
1498         return err;
1499     pci_set_master(pci);
1500 
1501     /* check if we can restrict PCI DMA transfers to 32 bits */
1502     if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) {
1503         dev_err(&pci->dev,
1504             "architecture does not support 32bit PCI busmaster DMA\n");
1505         pci_disable_device(pci);
1506         return -ENXIO;
1507     }
1508 
1509     /* alloc card manager */
1510     mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1511     if (! mgr) {
1512         pci_disable_device(pci);
1513         return -ENOMEM;
1514     }
1515 
1516     if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
1517         kfree(mgr);
1518         pci_disable_device(pci);
1519         return -ENODEV;
1520     }
1521     card_name =
1522         pcxhr_board_params[pci_id->driver_data].board_name;
1523     mgr->playback_chips =
1524         pcxhr_board_params[pci_id->driver_data].playback_chips;
1525     mgr->capture_chips  =
1526         pcxhr_board_params[pci_id->driver_data].capture_chips;
1527     mgr->fw_file_set =
1528         pcxhr_board_params[pci_id->driver_data].fw_file_set;
1529     mgr->firmware_num  =
1530         pcxhr_board_params[pci_id->driver_data].firmware_num;
1531     mgr->mono_capture = mono[dev];
1532     mgr->is_hr_stereo = (mgr->playback_chips == 1);
1533     mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1534     mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1535 
1536     if (mgr->is_hr_stereo)
1537         mgr->granularity = PCXHR_GRANULARITY_HR22;
1538     else
1539         mgr->granularity = PCXHR_GRANULARITY;
1540 
1541     /* resource assignment */
1542     err = pci_request_regions(pci, card_name);
1543     if (err < 0) {
1544         kfree(mgr);
1545         pci_disable_device(pci);
1546         return err;
1547     }
1548     for (i = 0; i < 3; i++)
1549         mgr->port[i] = pci_resource_start(pci, i);
1550 
1551     mgr->pci = pci;
1552     mgr->irq = -1;
1553 
1554     if (request_threaded_irq(pci->irq, pcxhr_interrupt,
1555                  pcxhr_threaded_irq, IRQF_SHARED,
1556                  KBUILD_MODNAME, mgr)) {
1557         dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq);
1558         pcxhr_free(mgr);
1559         return -EBUSY;
1560     }
1561     mgr->irq = pci->irq;
1562 
1563     snprintf(mgr->name, sizeof(mgr->name),
1564          "Digigram at 0x%lx & 0x%lx, 0x%lx irq %i",
1565          mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1566 
1567     /* ISR lock  */
1568     mutex_init(&mgr->lock);
1569     mutex_init(&mgr->msg_lock);
1570 
1571     /* init setup mutex*/
1572     mutex_init(&mgr->setup_mutex);
1573 
1574     mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1575                 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1576                        PCXHR_SIZE_MAX_STATUS),
1577                 GFP_KERNEL);
1578     if (! mgr->prmh) {
1579         pcxhr_free(mgr);
1580         return -ENOMEM;
1581     }
1582 
1583     for (i=0; i < PCXHR_MAX_CARDS; i++) {
1584         struct snd_card *card;
1585         char tmpid[16];
1586         int idx;
1587 
1588         if (i >= max(mgr->playback_chips, mgr->capture_chips))
1589             break;
1590         mgr->num_cards++;
1591 
1592         if (index[dev] < 0)
1593             idx = index[dev];
1594         else
1595             idx = index[dev] + i;
1596 
1597         snprintf(tmpid, sizeof(tmpid), "%s-%d",
1598              id[dev] ? id[dev] : card_name, i);
1599         err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE,
1600                    0, &card);
1601 
1602         if (err < 0) {
1603             dev_err(&pci->dev, "cannot allocate the card %d\n", i);
1604             pcxhr_free(mgr);
1605             return err;
1606         }
1607 
1608         strcpy(card->driver, DRIVER_NAME);
1609         snprintf(card->shortname, sizeof(card->shortname),
1610              "Digigram [PCM #%d]", i);
1611         snprintf(card->longname, sizeof(card->longname),
1612              "%s [PCM #%d]", mgr->name, i);
1613 
1614         err = pcxhr_create(mgr, card, i);
1615         if (err < 0) {
1616             snd_card_free(card);
1617             pcxhr_free(mgr);
1618             return err;
1619         }
1620 
1621         if (i == 0)
1622             /* init proc interface only for chip0 */
1623             pcxhr_proc_init(mgr->chip[i]);
1624 
1625         err = snd_card_register(card);
1626         if (err < 0) {
1627             pcxhr_free(mgr);
1628             return err;
1629         }
1630     }
1631 
1632     /* create hostport purgebuffer */
1633     size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1634     if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
1635                 size, &mgr->hostport) < 0) {
1636         pcxhr_free(mgr);
1637         return -ENOMEM;
1638     }
1639     /* init purgebuffer */
1640     memset(mgr->hostport.area, 0, size);
1641 
1642     /* create a DSP loader */
1643     err = pcxhr_setup_firmware(mgr);
1644     if (err < 0) {
1645         pcxhr_free(mgr);
1646         return err;
1647     }
1648 
1649     pci_set_drvdata(pci, mgr);
1650     dev++;
1651     return 0;
1652 }
1653 
1654 static void pcxhr_remove(struct pci_dev *pci)
1655 {
1656     pcxhr_free(pci_get_drvdata(pci));
1657 }
1658 
1659 static struct pci_driver pcxhr_driver = {
1660     .name = KBUILD_MODNAME,
1661     .id_table = pcxhr_ids,
1662     .probe = pcxhr_probe,
1663     .remove = pcxhr_remove,
1664 };
1665 
1666 module_pci_driver(pcxhr_driver);
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