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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * C-Media CMI8788 driver - PCM code
0004  *
0005  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
0006  */
0007 
0008 #include <linux/pci.h>
0009 #include <sound/control.h>
0010 #include <sound/core.h>
0011 #include <sound/pcm.h>
0012 #include <sound/pcm_params.h>
0013 #include "oxygen.h"
0014 
0015 /* most DMA channels have a 16-bit counter for 32-bit words */
0016 #define BUFFER_BYTES_MAX        ((1 << 16) * 4)
0017 /* the multichannel DMA channel has a 24-bit counter */
0018 #define BUFFER_BYTES_MAX_MULTICH    ((1 << 24) * 4)
0019 
0020 #define FIFO_BYTES          256
0021 #define FIFO_BYTES_MULTICH      1024
0022 
0023 #define PERIOD_BYTES_MIN        64
0024 
0025 #define DEFAULT_BUFFER_BYTES        (BUFFER_BYTES_MAX / 2)
0026 #define DEFAULT_BUFFER_BYTES_MULTICH    (1024 * 1024)
0027 
0028 static const struct snd_pcm_hardware oxygen_stereo_hardware = {
0029     .info = SNDRV_PCM_INFO_MMAP |
0030         SNDRV_PCM_INFO_MMAP_VALID |
0031         SNDRV_PCM_INFO_INTERLEAVED |
0032         SNDRV_PCM_INFO_PAUSE |
0033         SNDRV_PCM_INFO_SYNC_START |
0034         SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
0035     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0036            SNDRV_PCM_FMTBIT_S32_LE,
0037     .rates = SNDRV_PCM_RATE_32000 |
0038          SNDRV_PCM_RATE_44100 |
0039          SNDRV_PCM_RATE_48000 |
0040          SNDRV_PCM_RATE_64000 |
0041          SNDRV_PCM_RATE_88200 |
0042          SNDRV_PCM_RATE_96000 |
0043          SNDRV_PCM_RATE_176400 |
0044          SNDRV_PCM_RATE_192000,
0045     .rate_min = 32000,
0046     .rate_max = 192000,
0047     .channels_min = 2,
0048     .channels_max = 2,
0049     .buffer_bytes_max = BUFFER_BYTES_MAX,
0050     .period_bytes_min = PERIOD_BYTES_MIN,
0051     .period_bytes_max = BUFFER_BYTES_MAX,
0052     .periods_min = 1,
0053     .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
0054     .fifo_size = FIFO_BYTES,
0055 };
0056 static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
0057     .info = SNDRV_PCM_INFO_MMAP |
0058         SNDRV_PCM_INFO_MMAP_VALID |
0059         SNDRV_PCM_INFO_INTERLEAVED |
0060         SNDRV_PCM_INFO_PAUSE |
0061         SNDRV_PCM_INFO_SYNC_START |
0062         SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
0063     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0064            SNDRV_PCM_FMTBIT_S32_LE,
0065     .rates = SNDRV_PCM_RATE_32000 |
0066          SNDRV_PCM_RATE_44100 |
0067          SNDRV_PCM_RATE_48000 |
0068          SNDRV_PCM_RATE_64000 |
0069          SNDRV_PCM_RATE_88200 |
0070          SNDRV_PCM_RATE_96000 |
0071          SNDRV_PCM_RATE_176400 |
0072          SNDRV_PCM_RATE_192000,
0073     .rate_min = 32000,
0074     .rate_max = 192000,
0075     .channels_min = 2,
0076     .channels_max = 8,
0077     .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
0078     .period_bytes_min = PERIOD_BYTES_MIN,
0079     .period_bytes_max = BUFFER_BYTES_MAX_MULTICH,
0080     .periods_min = 1,
0081     .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
0082     .fifo_size = FIFO_BYTES_MULTICH,
0083 };
0084 static const struct snd_pcm_hardware oxygen_ac97_hardware = {
0085     .info = SNDRV_PCM_INFO_MMAP |
0086         SNDRV_PCM_INFO_MMAP_VALID |
0087         SNDRV_PCM_INFO_INTERLEAVED |
0088         SNDRV_PCM_INFO_PAUSE |
0089         SNDRV_PCM_INFO_SYNC_START |
0090         SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
0091     .formats = SNDRV_PCM_FMTBIT_S16_LE,
0092     .rates = SNDRV_PCM_RATE_48000,
0093     .rate_min = 48000,
0094     .rate_max = 48000,
0095     .channels_min = 2,
0096     .channels_max = 2,
0097     .buffer_bytes_max = BUFFER_BYTES_MAX,
0098     .period_bytes_min = PERIOD_BYTES_MIN,
0099     .period_bytes_max = BUFFER_BYTES_MAX,
0100     .periods_min = 1,
0101     .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
0102     .fifo_size = FIFO_BYTES,
0103 };
0104 
0105 static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
0106     [PCM_A] = &oxygen_stereo_hardware,
0107     [PCM_B] = &oxygen_stereo_hardware,
0108     [PCM_C] = &oxygen_stereo_hardware,
0109     [PCM_SPDIF] = &oxygen_stereo_hardware,
0110     [PCM_MULTICH] = &oxygen_multichannel_hardware,
0111     [PCM_AC97] = &oxygen_ac97_hardware,
0112 };
0113 
0114 static inline unsigned int
0115 oxygen_substream_channel(struct snd_pcm_substream *substream)
0116 {
0117     return (unsigned int)(uintptr_t)substream->runtime->private_data;
0118 }
0119 
0120 static int oxygen_open(struct snd_pcm_substream *substream,
0121                unsigned int channel)
0122 {
0123     struct oxygen *chip = snd_pcm_substream_chip(substream);
0124     struct snd_pcm_runtime *runtime = substream->runtime;
0125     int err;
0126 
0127     runtime->private_data = (void *)(uintptr_t)channel;
0128     if (channel == PCM_B && chip->has_ac97_1 &&
0129         (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
0130         runtime->hw = oxygen_ac97_hardware;
0131     else
0132         runtime->hw = *oxygen_hardware[channel];
0133     switch (channel) {
0134     case PCM_C:
0135         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) {
0136             runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
0137                            SNDRV_PCM_RATE_64000);
0138             runtime->hw.rate_min = 44100;
0139         }
0140         fallthrough;
0141     case PCM_A:
0142     case PCM_B:
0143         runtime->hw.fifo_size = 0;
0144         break;
0145     case PCM_MULTICH:
0146         runtime->hw.channels_max = chip->model.dac_channels_pcm;
0147         break;
0148     }
0149     if (chip->model.pcm_hardware_filter)
0150         chip->model.pcm_hardware_filter(channel, &runtime->hw);
0151     err = snd_pcm_hw_constraint_step(runtime, 0,
0152                      SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
0153     if (err < 0)
0154         return err;
0155     err = snd_pcm_hw_constraint_step(runtime, 0,
0156                      SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
0157     if (err < 0)
0158         return err;
0159     if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
0160         err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
0161         if (err < 0)
0162             return err;
0163     }
0164     if (runtime->hw.channels_max > 2) {
0165         err = snd_pcm_hw_constraint_step(runtime, 0,
0166                          SNDRV_PCM_HW_PARAM_CHANNELS,
0167                          2);
0168         if (err < 0)
0169             return err;
0170     }
0171     snd_pcm_set_sync(substream);
0172     chip->streams[channel] = substream;
0173 
0174     mutex_lock(&chip->mutex);
0175     chip->pcm_active |= 1 << channel;
0176     if (channel == PCM_SPDIF) {
0177         chip->spdif_pcm_bits = chip->spdif_bits;
0178         chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
0179             ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
0180         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
0181                    SNDRV_CTL_EVENT_MASK_INFO,
0182                    &chip->controls[CONTROL_SPDIF_PCM]->id);
0183     }
0184     mutex_unlock(&chip->mutex);
0185 
0186     return 0;
0187 }
0188 
0189 static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
0190 {
0191     return oxygen_open(substream, PCM_A);
0192 }
0193 
0194 static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
0195 {
0196     return oxygen_open(substream, PCM_B);
0197 }
0198 
0199 static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
0200 {
0201     return oxygen_open(substream, PCM_C);
0202 }
0203 
0204 static int oxygen_spdif_open(struct snd_pcm_substream *substream)
0205 {
0206     return oxygen_open(substream, PCM_SPDIF);
0207 }
0208 
0209 static int oxygen_multich_open(struct snd_pcm_substream *substream)
0210 {
0211     return oxygen_open(substream, PCM_MULTICH);
0212 }
0213 
0214 static int oxygen_ac97_open(struct snd_pcm_substream *substream)
0215 {
0216     return oxygen_open(substream, PCM_AC97);
0217 }
0218 
0219 static int oxygen_close(struct snd_pcm_substream *substream)
0220 {
0221     struct oxygen *chip = snd_pcm_substream_chip(substream);
0222     unsigned int channel = oxygen_substream_channel(substream);
0223 
0224     mutex_lock(&chip->mutex);
0225     chip->pcm_active &= ~(1 << channel);
0226     if (channel == PCM_SPDIF) {
0227         chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
0228             SNDRV_CTL_ELEM_ACCESS_INACTIVE;
0229         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
0230                    SNDRV_CTL_EVENT_MASK_INFO,
0231                    &chip->controls[CONTROL_SPDIF_PCM]->id);
0232     }
0233     if (channel == PCM_SPDIF || channel == PCM_MULTICH)
0234         oxygen_update_spdif_source(chip);
0235     mutex_unlock(&chip->mutex);
0236 
0237     chip->streams[channel] = NULL;
0238     return 0;
0239 }
0240 
0241 static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
0242 {
0243     if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
0244         return OXYGEN_FORMAT_24;
0245     else
0246         return OXYGEN_FORMAT_16;
0247 }
0248 
0249 static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
0250 {
0251     switch (params_rate(hw_params)) {
0252     case 32000:
0253         return OXYGEN_RATE_32000;
0254     case 44100:
0255         return OXYGEN_RATE_44100;
0256     default: /* 48000 */
0257         return OXYGEN_RATE_48000;
0258     case 64000:
0259         return OXYGEN_RATE_64000;
0260     case 88200:
0261         return OXYGEN_RATE_88200;
0262     case 96000:
0263         return OXYGEN_RATE_96000;
0264     case 176400:
0265         return OXYGEN_RATE_176400;
0266     case 192000:
0267         return OXYGEN_RATE_192000;
0268     }
0269 }
0270 
0271 static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
0272 {
0273     if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
0274         return OXYGEN_I2S_BITS_24;
0275     else
0276         return OXYGEN_I2S_BITS_16;
0277 }
0278 
0279 static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
0280 {
0281     switch (params_channels(hw_params)) {
0282     default: /* 2 */
0283         return OXYGEN_PLAY_CHANNELS_2;
0284     case 4:
0285         return OXYGEN_PLAY_CHANNELS_4;
0286     case 6:
0287         return OXYGEN_PLAY_CHANNELS_6;
0288     case 8:
0289         return OXYGEN_PLAY_CHANNELS_8;
0290     }
0291 }
0292 
0293 static const unsigned int channel_base_registers[PCM_COUNT] = {
0294     [PCM_A] = OXYGEN_DMA_A_ADDRESS,
0295     [PCM_B] = OXYGEN_DMA_B_ADDRESS,
0296     [PCM_C] = OXYGEN_DMA_C_ADDRESS,
0297     [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
0298     [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
0299     [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
0300 };
0301 
0302 static int oxygen_hw_params(struct snd_pcm_substream *substream,
0303                 struct snd_pcm_hw_params *hw_params)
0304 {
0305     struct oxygen *chip = snd_pcm_substream_chip(substream);
0306     unsigned int channel = oxygen_substream_channel(substream);
0307 
0308     oxygen_write32(chip, channel_base_registers[channel],
0309                (u32)substream->runtime->dma_addr);
0310     if (channel == PCM_MULTICH) {
0311         oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
0312                    params_buffer_bytes(hw_params) / 4 - 1);
0313         oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
0314                    params_period_bytes(hw_params) / 4 - 1);
0315     } else {
0316         oxygen_write16(chip, channel_base_registers[channel] + 4,
0317                    params_buffer_bytes(hw_params) / 4 - 1);
0318         oxygen_write16(chip, channel_base_registers[channel] + 6,
0319                    params_period_bytes(hw_params) / 4 - 1);
0320     }
0321     return 0;
0322 }
0323 
0324 static u16 get_mclk(struct oxygen *chip, unsigned int channel,
0325             struct snd_pcm_hw_params *params)
0326 {
0327     unsigned int mclks, shift;
0328 
0329     if (channel == PCM_MULTICH)
0330         mclks = chip->model.dac_mclks;
0331     else
0332         mclks = chip->model.adc_mclks;
0333 
0334     if (params_rate(params) <= 48000)
0335         shift = 0;
0336     else if (params_rate(params) <= 96000)
0337         shift = 2;
0338     else
0339         shift = 4;
0340 
0341     return OXYGEN_I2S_MCLK(mclks >> shift);
0342 }
0343 
0344 static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
0345                   struct snd_pcm_hw_params *hw_params)
0346 {
0347     struct oxygen *chip = snd_pcm_substream_chip(substream);
0348     int err;
0349 
0350     err = oxygen_hw_params(substream, hw_params);
0351     if (err < 0)
0352         return err;
0353 
0354     spin_lock_irq(&chip->reg_lock);
0355     oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
0356                  oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
0357                  OXYGEN_REC_FORMAT_A_MASK);
0358     oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
0359                   oxygen_rate(hw_params) |
0360                   chip->model.adc_i2s_format |
0361                   get_mclk(chip, PCM_A, hw_params) |
0362                   oxygen_i2s_bits(hw_params),
0363                   OXYGEN_I2S_RATE_MASK |
0364                   OXYGEN_I2S_FORMAT_MASK |
0365                   OXYGEN_I2S_MCLK_MASK |
0366                   OXYGEN_I2S_BITS_MASK);
0367     spin_unlock_irq(&chip->reg_lock);
0368 
0369     mutex_lock(&chip->mutex);
0370     chip->model.set_adc_params(chip, hw_params);
0371     mutex_unlock(&chip->mutex);
0372     return 0;
0373 }
0374 
0375 static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
0376                   struct snd_pcm_hw_params *hw_params)
0377 {
0378     struct oxygen *chip = snd_pcm_substream_chip(substream);
0379     int is_ac97;
0380     int err;
0381 
0382     err = oxygen_hw_params(substream, hw_params);
0383     if (err < 0)
0384         return err;
0385 
0386     is_ac97 = chip->has_ac97_1 &&
0387         (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
0388 
0389     spin_lock_irq(&chip->reg_lock);
0390     oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
0391                  oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
0392                  OXYGEN_REC_FORMAT_B_MASK);
0393     if (!is_ac97)
0394         oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
0395                       oxygen_rate(hw_params) |
0396                       chip->model.adc_i2s_format |
0397                       get_mclk(chip, PCM_B, hw_params) |
0398                       oxygen_i2s_bits(hw_params),
0399                       OXYGEN_I2S_RATE_MASK |
0400                       OXYGEN_I2S_FORMAT_MASK |
0401                       OXYGEN_I2S_MCLK_MASK |
0402                       OXYGEN_I2S_BITS_MASK);
0403     spin_unlock_irq(&chip->reg_lock);
0404 
0405     if (!is_ac97) {
0406         mutex_lock(&chip->mutex);
0407         chip->model.set_adc_params(chip, hw_params);
0408         mutex_unlock(&chip->mutex);
0409     }
0410     return 0;
0411 }
0412 
0413 static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
0414                   struct snd_pcm_hw_params *hw_params)
0415 {
0416     struct oxygen *chip = snd_pcm_substream_chip(substream);
0417     bool is_spdif;
0418     int err;
0419 
0420     err = oxygen_hw_params(substream, hw_params);
0421     if (err < 0)
0422         return err;
0423 
0424     is_spdif = chip->model.device_config & CAPTURE_1_FROM_SPDIF;
0425 
0426     spin_lock_irq(&chip->reg_lock);
0427     oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
0428                  oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
0429                  OXYGEN_REC_FORMAT_C_MASK);
0430     if (!is_spdif)
0431         oxygen_write16_masked(chip, OXYGEN_I2S_C_FORMAT,
0432                       oxygen_rate(hw_params) |
0433                       chip->model.adc_i2s_format |
0434                       get_mclk(chip, PCM_B, hw_params) |
0435                       oxygen_i2s_bits(hw_params),
0436                       OXYGEN_I2S_RATE_MASK |
0437                       OXYGEN_I2S_FORMAT_MASK |
0438                       OXYGEN_I2S_MCLK_MASK |
0439                       OXYGEN_I2S_BITS_MASK);
0440     spin_unlock_irq(&chip->reg_lock);
0441 
0442     if (!is_spdif) {
0443         mutex_lock(&chip->mutex);
0444         chip->model.set_adc_params(chip, hw_params);
0445         mutex_unlock(&chip->mutex);
0446     }
0447     return 0;
0448 }
0449 
0450 static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
0451                   struct snd_pcm_hw_params *hw_params)
0452 {
0453     struct oxygen *chip = snd_pcm_substream_chip(substream);
0454     int err;
0455 
0456     err = oxygen_hw_params(substream, hw_params);
0457     if (err < 0)
0458         return err;
0459 
0460     mutex_lock(&chip->mutex);
0461     spin_lock_irq(&chip->reg_lock);
0462     oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
0463                 OXYGEN_SPDIF_OUT_ENABLE);
0464     oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
0465                  oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
0466                  OXYGEN_SPDIF_FORMAT_MASK);
0467     oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
0468                   oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
0469                   OXYGEN_SPDIF_OUT_RATE_MASK);
0470     oxygen_update_spdif_source(chip);
0471     spin_unlock_irq(&chip->reg_lock);
0472     mutex_unlock(&chip->mutex);
0473     return 0;
0474 }
0475 
0476 static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
0477                     struct snd_pcm_hw_params *hw_params)
0478 {
0479     struct oxygen *chip = snd_pcm_substream_chip(substream);
0480     int err;
0481 
0482     err = oxygen_hw_params(substream, hw_params);
0483     if (err < 0)
0484         return err;
0485 
0486     mutex_lock(&chip->mutex);
0487     spin_lock_irq(&chip->reg_lock);
0488     oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
0489                  oxygen_play_channels(hw_params),
0490                  OXYGEN_PLAY_CHANNELS_MASK);
0491     oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
0492                  oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
0493                  OXYGEN_MULTICH_FORMAT_MASK);
0494     oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
0495                   oxygen_rate(hw_params) |
0496                   chip->model.dac_i2s_format |
0497                   get_mclk(chip, PCM_MULTICH, hw_params) |
0498                   oxygen_i2s_bits(hw_params),
0499                   OXYGEN_I2S_RATE_MASK |
0500                   OXYGEN_I2S_FORMAT_MASK |
0501                   OXYGEN_I2S_MCLK_MASK |
0502                   OXYGEN_I2S_BITS_MASK);
0503     oxygen_update_spdif_source(chip);
0504     spin_unlock_irq(&chip->reg_lock);
0505 
0506     chip->model.set_dac_params(chip, hw_params);
0507     oxygen_update_dac_routing(chip);
0508     mutex_unlock(&chip->mutex);
0509     return 0;
0510 }
0511 
0512 static int oxygen_hw_free(struct snd_pcm_substream *substream)
0513 {
0514     struct oxygen *chip = snd_pcm_substream_chip(substream);
0515     unsigned int channel = oxygen_substream_channel(substream);
0516     unsigned int channel_mask = 1 << channel;
0517 
0518     spin_lock_irq(&chip->reg_lock);
0519     chip->interrupt_mask &= ~channel_mask;
0520     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
0521 
0522     oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
0523     oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
0524     spin_unlock_irq(&chip->reg_lock);
0525 
0526     return 0;
0527 }
0528 
0529 static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
0530 {
0531     struct oxygen *chip = snd_pcm_substream_chip(substream);
0532 
0533     spin_lock_irq(&chip->reg_lock);
0534     oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
0535                 OXYGEN_SPDIF_OUT_ENABLE);
0536     spin_unlock_irq(&chip->reg_lock);
0537     return oxygen_hw_free(substream);
0538 }
0539 
0540 static int oxygen_prepare(struct snd_pcm_substream *substream)
0541 {
0542     struct oxygen *chip = snd_pcm_substream_chip(substream);
0543     unsigned int channel = oxygen_substream_channel(substream);
0544     unsigned int channel_mask = 1 << channel;
0545 
0546     spin_lock_irq(&chip->reg_lock);
0547     oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
0548     oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
0549 
0550     if (substream->runtime->no_period_wakeup)
0551         chip->interrupt_mask &= ~channel_mask;
0552     else
0553         chip->interrupt_mask |= channel_mask;
0554     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
0555     spin_unlock_irq(&chip->reg_lock);
0556     return 0;
0557 }
0558 
0559 static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
0560 {
0561     struct oxygen *chip = snd_pcm_substream_chip(substream);
0562     struct snd_pcm_substream *s;
0563     unsigned int mask = 0;
0564     int pausing;
0565 
0566     switch (cmd) {
0567     case SNDRV_PCM_TRIGGER_STOP:
0568     case SNDRV_PCM_TRIGGER_START:
0569     case SNDRV_PCM_TRIGGER_SUSPEND:
0570         pausing = 0;
0571         break;
0572     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0573     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0574         pausing = 1;
0575         break;
0576     default:
0577         return -EINVAL;
0578     }
0579 
0580     snd_pcm_group_for_each_entry(s, substream) {
0581         if (snd_pcm_substream_chip(s) == chip) {
0582             mask |= 1 << oxygen_substream_channel(s);
0583             snd_pcm_trigger_done(s, substream);
0584         }
0585     }
0586 
0587     spin_lock(&chip->reg_lock);
0588     if (!pausing) {
0589         if (cmd == SNDRV_PCM_TRIGGER_START)
0590             chip->pcm_running |= mask;
0591         else
0592             chip->pcm_running &= ~mask;
0593         oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
0594     } else {
0595         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
0596             oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
0597         else
0598             oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
0599     }
0600     spin_unlock(&chip->reg_lock);
0601     return 0;
0602 }
0603 
0604 static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
0605 {
0606     struct oxygen *chip = snd_pcm_substream_chip(substream);
0607     struct snd_pcm_runtime *runtime = substream->runtime;
0608     unsigned int channel = oxygen_substream_channel(substream);
0609     u32 curr_addr;
0610 
0611     /* no spinlock, this read should be atomic */
0612     curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
0613     return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
0614 }
0615 
0616 static const struct snd_pcm_ops oxygen_rec_a_ops = {
0617     .open      = oxygen_rec_a_open,
0618     .close     = oxygen_close,
0619     .hw_params = oxygen_rec_a_hw_params,
0620     .hw_free   = oxygen_hw_free,
0621     .prepare   = oxygen_prepare,
0622     .trigger   = oxygen_trigger,
0623     .pointer   = oxygen_pointer,
0624 };
0625 
0626 static const struct snd_pcm_ops oxygen_rec_b_ops = {
0627     .open      = oxygen_rec_b_open,
0628     .close     = oxygen_close,
0629     .hw_params = oxygen_rec_b_hw_params,
0630     .hw_free   = oxygen_hw_free,
0631     .prepare   = oxygen_prepare,
0632     .trigger   = oxygen_trigger,
0633     .pointer   = oxygen_pointer,
0634 };
0635 
0636 static const struct snd_pcm_ops oxygen_rec_c_ops = {
0637     .open      = oxygen_rec_c_open,
0638     .close     = oxygen_close,
0639     .hw_params = oxygen_rec_c_hw_params,
0640     .hw_free   = oxygen_hw_free,
0641     .prepare   = oxygen_prepare,
0642     .trigger   = oxygen_trigger,
0643     .pointer   = oxygen_pointer,
0644 };
0645 
0646 static const struct snd_pcm_ops oxygen_spdif_ops = {
0647     .open      = oxygen_spdif_open,
0648     .close     = oxygen_close,
0649     .hw_params = oxygen_spdif_hw_params,
0650     .hw_free   = oxygen_spdif_hw_free,
0651     .prepare   = oxygen_prepare,
0652     .trigger   = oxygen_trigger,
0653     .pointer   = oxygen_pointer,
0654 };
0655 
0656 static const struct snd_pcm_ops oxygen_multich_ops = {
0657     .open      = oxygen_multich_open,
0658     .close     = oxygen_close,
0659     .hw_params = oxygen_multich_hw_params,
0660     .hw_free   = oxygen_hw_free,
0661     .prepare   = oxygen_prepare,
0662     .trigger   = oxygen_trigger,
0663     .pointer   = oxygen_pointer,
0664 };
0665 
0666 static const struct snd_pcm_ops oxygen_ac97_ops = {
0667     .open      = oxygen_ac97_open,
0668     .close     = oxygen_close,
0669     .hw_params = oxygen_hw_params,
0670     .hw_free   = oxygen_hw_free,
0671     .prepare   = oxygen_prepare,
0672     .trigger   = oxygen_trigger,
0673     .pointer   = oxygen_pointer,
0674 };
0675 
0676 int oxygen_pcm_init(struct oxygen *chip)
0677 {
0678     struct snd_pcm *pcm;
0679     int outs, ins;
0680     int err;
0681 
0682     outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
0683     ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
0684                           CAPTURE_0_FROM_I2S_2));
0685     if (outs | ins) {
0686         err = snd_pcm_new(chip->card, "Multichannel",
0687                   0, outs, ins, &pcm);
0688         if (err < 0)
0689             return err;
0690         if (outs)
0691             snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
0692                     &oxygen_multich_ops);
0693         if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
0694             snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0695                     &oxygen_rec_a_ops);
0696         else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
0697             snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0698                     &oxygen_rec_b_ops);
0699         pcm->private_data = chip;
0700         strcpy(pcm->name, "Multichannel");
0701         if (outs)
0702             snd_pcm_set_managed_buffer(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
0703                            SNDRV_DMA_TYPE_DEV,
0704                            &chip->pci->dev,
0705                            DEFAULT_BUFFER_BYTES_MULTICH,
0706                            BUFFER_BYTES_MAX_MULTICH);
0707         if (ins)
0708             snd_pcm_set_managed_buffer(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
0709                            SNDRV_DMA_TYPE_DEV,
0710                            &chip->pci->dev,
0711                            DEFAULT_BUFFER_BYTES,
0712                            BUFFER_BYTES_MAX);
0713     }
0714 
0715     outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
0716     ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
0717     if (outs | ins) {
0718         err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
0719         if (err < 0)
0720             return err;
0721         if (outs)
0722             snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
0723                     &oxygen_spdif_ops);
0724         if (ins)
0725             snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0726                     &oxygen_rec_c_ops);
0727         pcm->private_data = chip;
0728         strcpy(pcm->name, "Digital");
0729         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
0730                            &chip->pci->dev,
0731                            DEFAULT_BUFFER_BYTES,
0732                            BUFFER_BYTES_MAX);
0733     }
0734 
0735     if (chip->has_ac97_1) {
0736         outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
0737         ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
0738     } else {
0739         outs = 0;
0740         ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
0741     }
0742     if (outs | ins) {
0743         err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
0744                   2, outs, ins, &pcm);
0745         if (err < 0)
0746             return err;
0747         if (outs) {
0748             snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
0749                     &oxygen_ac97_ops);
0750             oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
0751                          OXYGEN_REC_B_ROUTE_AC97_1,
0752                          OXYGEN_REC_B_ROUTE_MASK);
0753         }
0754         if (ins)
0755             snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0756                     &oxygen_rec_b_ops);
0757         pcm->private_data = chip;
0758         strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
0759         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
0760                            &chip->pci->dev,
0761                            DEFAULT_BUFFER_BYTES,
0762                            BUFFER_BYTES_MAX);
0763     }
0764 
0765     ins = !!(chip->model.device_config & CAPTURE_3_FROM_I2S_3);
0766     if (ins) {
0767         err = snd_pcm_new(chip->card, "Analog3", 3, 0, ins, &pcm);
0768         if (err < 0)
0769             return err;
0770         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0771                 &oxygen_rec_c_ops);
0772         oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
0773                      OXYGEN_REC_C_ROUTE_I2S_ADC_3,
0774                      OXYGEN_REC_C_ROUTE_MASK);
0775         pcm->private_data = chip;
0776         strcpy(pcm->name, "Analog 3");
0777         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
0778                            &chip->pci->dev,
0779                            DEFAULT_BUFFER_BYTES,
0780                            BUFFER_BYTES_MAX);
0781     }
0782     return 0;
0783 }
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