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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * C-Media CMI8788 driver - main driver module
0004  *
0005  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
0006  */
0007 
0008 #include <linux/delay.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/mutex.h>
0011 #include <linux/pci.h>
0012 #include <linux/slab.h>
0013 #include <linux/module.h>
0014 #include <sound/ac97_codec.h>
0015 #include <sound/asoundef.h>
0016 #include <sound/core.h>
0017 #include <sound/info.h>
0018 #include <sound/mpu401.h>
0019 #include <sound/pcm.h>
0020 #include "oxygen.h"
0021 #include "cm9780.h"
0022 
0023 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
0024 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
0025 MODULE_LICENSE("GPL v2");
0026 
0027 #define DRIVER "oxygen"
0028 
0029 static inline int oxygen_uart_input_ready(struct oxygen *chip)
0030 {
0031     return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
0032 }
0033 
0034 static void oxygen_read_uart(struct oxygen *chip)
0035 {
0036     if (unlikely(!oxygen_uart_input_ready(chip))) {
0037         /* no data, but read it anyway to clear the interrupt */
0038         oxygen_read8(chip, OXYGEN_MPU401);
0039         return;
0040     }
0041     do {
0042         u8 data = oxygen_read8(chip, OXYGEN_MPU401);
0043         if (data == MPU401_ACK)
0044             continue;
0045         if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
0046             chip->uart_input_count = 0;
0047         chip->uart_input[chip->uart_input_count++] = data;
0048     } while (oxygen_uart_input_ready(chip));
0049     if (chip->model.uart_input)
0050         chip->model.uart_input(chip);
0051 }
0052 
0053 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
0054 {
0055     struct oxygen *chip = dev_id;
0056     unsigned int status, clear, elapsed_streams, i;
0057 
0058     status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
0059     if (!status)
0060         return IRQ_NONE;
0061 
0062     spin_lock(&chip->reg_lock);
0063 
0064     clear = status & (OXYGEN_CHANNEL_A |
0065               OXYGEN_CHANNEL_B |
0066               OXYGEN_CHANNEL_C |
0067               OXYGEN_CHANNEL_SPDIF |
0068               OXYGEN_CHANNEL_MULTICH |
0069               OXYGEN_CHANNEL_AC97 |
0070               OXYGEN_INT_SPDIF_IN_DETECT |
0071               OXYGEN_INT_GPIO |
0072               OXYGEN_INT_AC97);
0073     if (clear) {
0074         if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
0075             chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
0076         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
0077                    chip->interrupt_mask & ~clear);
0078         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
0079                    chip->interrupt_mask);
0080     }
0081 
0082     elapsed_streams = status & chip->pcm_running;
0083 
0084     spin_unlock(&chip->reg_lock);
0085 
0086     for (i = 0; i < PCM_COUNT; ++i)
0087         if ((elapsed_streams & (1 << i)) && chip->streams[i])
0088             snd_pcm_period_elapsed(chip->streams[i]);
0089 
0090     if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
0091         spin_lock(&chip->reg_lock);
0092         i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
0093         if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
0094              OXYGEN_SPDIF_RATE_INT)) {
0095             /* write the interrupt bit(s) to clear */
0096             oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
0097             schedule_work(&chip->spdif_input_bits_work);
0098         }
0099         spin_unlock(&chip->reg_lock);
0100     }
0101 
0102     if (status & OXYGEN_INT_GPIO)
0103         schedule_work(&chip->gpio_work);
0104 
0105     if (status & OXYGEN_INT_MIDI) {
0106         if (chip->midi)
0107             snd_mpu401_uart_interrupt(0, chip->midi->private_data);
0108         else
0109             oxygen_read_uart(chip);
0110     }
0111 
0112     if (status & OXYGEN_INT_AC97)
0113         wake_up(&chip->ac97_waitqueue);
0114 
0115     return IRQ_HANDLED;
0116 }
0117 
0118 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
0119 {
0120     struct oxygen *chip = container_of(work, struct oxygen,
0121                        spdif_input_bits_work);
0122     u32 reg;
0123 
0124     /*
0125      * This function gets called when there is new activity on the SPDIF
0126      * input, or when we lose lock on the input signal, or when the rate
0127      * changes.
0128      */
0129     msleep(1);
0130     spin_lock_irq(&chip->reg_lock);
0131     reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
0132     if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
0133             OXYGEN_SPDIF_LOCK_STATUS))
0134         == OXYGEN_SPDIF_SENSE_STATUS) {
0135         /*
0136          * If we detect activity on the SPDIF input but cannot lock to
0137          * a signal, the clock bit is likely to be wrong.
0138          */
0139         reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
0140         oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
0141         spin_unlock_irq(&chip->reg_lock);
0142         msleep(1);
0143         spin_lock_irq(&chip->reg_lock);
0144         reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
0145         if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
0146                 OXYGEN_SPDIF_LOCK_STATUS))
0147             == OXYGEN_SPDIF_SENSE_STATUS) {
0148             /* nothing detected with either clock; give up */
0149             if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
0150                 == OXYGEN_SPDIF_IN_CLOCK_192) {
0151                 /*
0152                  * Reset clock to <= 96 kHz because this is
0153                  * more likely to be received next time.
0154                  */
0155                 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
0156                 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
0157                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
0158             }
0159         }
0160     }
0161     spin_unlock_irq(&chip->reg_lock);
0162 
0163     if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
0164         spin_lock_irq(&chip->reg_lock);
0165         chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
0166         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
0167                    chip->interrupt_mask);
0168         spin_unlock_irq(&chip->reg_lock);
0169 
0170         /*
0171          * We don't actually know that any channel status bits have
0172          * changed, but let's send a notification just to be sure.
0173          */
0174         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
0175                    &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
0176     }
0177 }
0178 
0179 static void oxygen_gpio_changed(struct work_struct *work)
0180 {
0181     struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
0182 
0183     if (chip->model.gpio_changed)
0184         chip->model.gpio_changed(chip);
0185 }
0186 
0187 static void oxygen_proc_read(struct snd_info_entry *entry,
0188                  struct snd_info_buffer *buffer)
0189 {
0190     struct oxygen *chip = entry->private_data;
0191     int i, j;
0192 
0193     switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
0194     case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
0195     case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
0196     case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
0197     default:                     i = '?'; break;
0198     }
0199     snd_iprintf(buffer, "CMI878%c:\n", i);
0200     for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
0201         snd_iprintf(buffer, "%02x:", i);
0202         for (j = 0; j < 0x10; ++j)
0203             snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
0204         snd_iprintf(buffer, "\n");
0205     }
0206     if (mutex_lock_interruptible(&chip->mutex) < 0)
0207         return;
0208     if (chip->has_ac97_0) {
0209         snd_iprintf(buffer, "\nAC97:\n");
0210         for (i = 0; i < 0x80; i += 0x10) {
0211             snd_iprintf(buffer, "%02x:", i);
0212             for (j = 0; j < 0x10; j += 2)
0213                 snd_iprintf(buffer, " %04x",
0214                         oxygen_read_ac97(chip, 0, i + j));
0215             snd_iprintf(buffer, "\n");
0216         }
0217     }
0218     if (chip->has_ac97_1) {
0219         snd_iprintf(buffer, "\nAC97 2:\n");
0220         for (i = 0; i < 0x80; i += 0x10) {
0221             snd_iprintf(buffer, "%02x:", i);
0222             for (j = 0; j < 0x10; j += 2)
0223                 snd_iprintf(buffer, " %04x",
0224                         oxygen_read_ac97(chip, 1, i + j));
0225             snd_iprintf(buffer, "\n");
0226         }
0227     }
0228     mutex_unlock(&chip->mutex);
0229     if (chip->model.dump_registers)
0230         chip->model.dump_registers(chip, buffer);
0231 }
0232 
0233 static void oxygen_proc_init(struct oxygen *chip)
0234 {
0235     snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read);
0236 }
0237 
0238 static const struct pci_device_id *
0239 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
0240 {
0241     u16 subdevice;
0242 
0243     /*
0244      * Make sure the EEPROM pins are available, i.e., not used for SPI.
0245      * (This function is called before we initialize or use SPI.)
0246      */
0247     oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
0248                OXYGEN_FUNCTION_ENABLE_SPI_4_5);
0249     /*
0250      * Read the subsystem device ID directly from the EEPROM, because the
0251      * chip didn't if the first EEPROM word was overwritten.
0252      */
0253     subdevice = oxygen_read_eeprom(chip, 2);
0254     /* use default ID if EEPROM is missing */
0255     if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
0256         subdevice = 0x8788;
0257     /*
0258      * We use only the subsystem device ID for searching because it is
0259      * unique even without the subsystem vendor ID, which may have been
0260      * overwritten in the EEPROM.
0261      */
0262     for (; ids->vendor; ++ids)
0263         if (ids->subdevice == subdevice &&
0264             ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
0265             return ids;
0266     return NULL;
0267 }
0268 
0269 static void oxygen_restore_eeprom(struct oxygen *chip,
0270                   const struct pci_device_id *id)
0271 {
0272     u16 eeprom_id;
0273 
0274     eeprom_id = oxygen_read_eeprom(chip, 0);
0275     if (eeprom_id != OXYGEN_EEPROM_ID &&
0276         (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
0277         /*
0278          * This function gets called only when a known card model has
0279          * been detected, i.e., we know there is a valid subsystem
0280          * product ID at index 2 in the EEPROM.  Therefore, we have
0281          * been able to deduce the correct subsystem vendor ID, and
0282          * this is enough information to restore the original EEPROM
0283          * contents.
0284          */
0285         oxygen_write_eeprom(chip, 1, id->subvendor);
0286         oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
0287 
0288         oxygen_set_bits8(chip, OXYGEN_MISC,
0289                  OXYGEN_MISC_WRITE_PCI_SUBID);
0290         pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
0291                       id->subvendor);
0292         pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
0293                       id->subdevice);
0294         oxygen_clear_bits8(chip, OXYGEN_MISC,
0295                    OXYGEN_MISC_WRITE_PCI_SUBID);
0296 
0297         dev_info(chip->card->dev, "EEPROM ID restored\n");
0298     }
0299 }
0300 
0301 static void configure_pcie_bridge(struct pci_dev *pci)
0302 {
0303     enum { PEX811X, PI7C9X110, XIO2001 };
0304     static const struct pci_device_id bridge_ids[] = {
0305         { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
0306         { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
0307         { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
0308         { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
0309         { }
0310     };
0311     struct pci_dev *bridge;
0312     const struct pci_device_id *id;
0313     u32 tmp;
0314 
0315     if (!pci->bus || !pci->bus->self)
0316         return;
0317     bridge = pci->bus->self;
0318 
0319     id = pci_match_id(bridge_ids, bridge);
0320     if (!id)
0321         return;
0322 
0323     switch (id->driver_data) {
0324     case PEX811X:   /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
0325         pci_read_config_dword(bridge, 0x48, &tmp);
0326         tmp |= 1;   /* enable blind prefetching */
0327         tmp |= 1 << 11; /* enable beacon generation */
0328         pci_write_config_dword(bridge, 0x48, tmp);
0329 
0330         pci_write_config_dword(bridge, 0x84, 0x0c);
0331         pci_read_config_dword(bridge, 0x88, &tmp);
0332         tmp &= ~(7 << 27);
0333         tmp |= 2 << 27; /* set prefetch size to 128 bytes */
0334         pci_write_config_dword(bridge, 0x88, tmp);
0335         break;
0336 
0337     case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
0338         pci_read_config_dword(bridge, 0x40, &tmp);
0339         tmp |= 1;   /* park the PCI arbiter to the sound chip */
0340         pci_write_config_dword(bridge, 0x40, tmp);
0341         break;
0342 
0343     case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */
0344         pci_read_config_dword(bridge, 0xe8, &tmp);
0345         tmp &= ~0xf;    /* request length limit: 64 bytes */
0346         tmp &= ~(0xf << 8);
0347         tmp |= 1 << 8;  /* request count limit: one buffer */
0348         pci_write_config_dword(bridge, 0xe8, tmp);
0349         break;
0350     }
0351 }
0352 
0353 static void oxygen_init(struct oxygen *chip)
0354 {
0355     unsigned int i;
0356 
0357     chip->dac_routing = 1;
0358     for (i = 0; i < 8; ++i)
0359         chip->dac_volume[i] = chip->model.dac_volume_min;
0360     chip->dac_mute = 1;
0361     chip->spdif_playback_enable = 0;
0362     chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
0363         (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
0364     chip->spdif_pcm_bits = chip->spdif_bits;
0365 
0366     if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
0367         oxygen_set_bits8(chip, OXYGEN_MISC,
0368                  OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
0369 
0370     i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
0371     chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
0372     chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
0373 
0374     oxygen_write8_masked(chip, OXYGEN_FUNCTION,
0375                  OXYGEN_FUNCTION_RESET_CODEC |
0376                  chip->model.function_flags,
0377                  OXYGEN_FUNCTION_RESET_CODEC |
0378                  OXYGEN_FUNCTION_2WIRE_SPI_MASK |
0379                  OXYGEN_FUNCTION_ENABLE_SPI_4_5);
0380     oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
0381     oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
0382     oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
0383               OXYGEN_PLAY_CHANNELS_2 |
0384               OXYGEN_DMA_A_BURST_8 |
0385               OXYGEN_DMA_MULTICH_BURST_8);
0386     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
0387     oxygen_write8_masked(chip, OXYGEN_MISC,
0388                  chip->model.misc_flags,
0389                  OXYGEN_MISC_WRITE_PCI_SUBID |
0390                  OXYGEN_MISC_REC_C_FROM_SPDIF |
0391                  OXYGEN_MISC_REC_B_FROM_AC97 |
0392                  OXYGEN_MISC_REC_A_FROM_MULTICH |
0393                  OXYGEN_MISC_MIDI);
0394     oxygen_write8(chip, OXYGEN_REC_FORMAT,
0395               (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
0396               (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
0397               (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
0398     oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
0399               (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
0400               (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
0401     oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
0402     oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
0403                OXYGEN_RATE_48000 |
0404                chip->model.dac_i2s_format |
0405                OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
0406                OXYGEN_I2S_BITS_16 |
0407                OXYGEN_I2S_MASTER |
0408                OXYGEN_I2S_BCLK_64);
0409     if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
0410         oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
0411                    OXYGEN_RATE_48000 |
0412                    chip->model.adc_i2s_format |
0413                    OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
0414                    OXYGEN_I2S_BITS_16 |
0415                    OXYGEN_I2S_MASTER |
0416                    OXYGEN_I2S_BCLK_64);
0417     else
0418         oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
0419                    OXYGEN_I2S_MASTER |
0420                    OXYGEN_I2S_MUTE_MCLK);
0421     if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
0422                      CAPTURE_2_FROM_I2S_2))
0423         oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
0424                    OXYGEN_RATE_48000 |
0425                    chip->model.adc_i2s_format |
0426                    OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
0427                    OXYGEN_I2S_BITS_16 |
0428                    OXYGEN_I2S_MASTER |
0429                    OXYGEN_I2S_BCLK_64);
0430     else
0431         oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
0432                    OXYGEN_I2S_MASTER |
0433                    OXYGEN_I2S_MUTE_MCLK);
0434     if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
0435         oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
0436                    OXYGEN_RATE_48000 |
0437                    chip->model.adc_i2s_format |
0438                    OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
0439                    OXYGEN_I2S_BITS_16 |
0440                    OXYGEN_I2S_MASTER |
0441                    OXYGEN_I2S_BCLK_64);
0442     else
0443         oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
0444                    OXYGEN_I2S_MASTER |
0445                    OXYGEN_I2S_MUTE_MCLK);
0446     oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
0447                 OXYGEN_SPDIF_OUT_ENABLE |
0448                 OXYGEN_SPDIF_LOOPBACK);
0449     if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
0450         oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
0451                       OXYGEN_SPDIF_SENSE_MASK |
0452                       OXYGEN_SPDIF_LOCK_MASK |
0453                       OXYGEN_SPDIF_RATE_MASK |
0454                       OXYGEN_SPDIF_LOCK_PAR |
0455                       OXYGEN_SPDIF_IN_CLOCK_96,
0456                       OXYGEN_SPDIF_SENSE_MASK |
0457                       OXYGEN_SPDIF_LOCK_MASK |
0458                       OXYGEN_SPDIF_RATE_MASK |
0459                       OXYGEN_SPDIF_SENSE_PAR |
0460                       OXYGEN_SPDIF_LOCK_PAR |
0461                       OXYGEN_SPDIF_IN_CLOCK_MASK);
0462     else
0463         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
0464                     OXYGEN_SPDIF_SENSE_MASK |
0465                     OXYGEN_SPDIF_LOCK_MASK |
0466                     OXYGEN_SPDIF_RATE_MASK);
0467     oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
0468     oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
0469                OXYGEN_2WIRE_LENGTH_8 |
0470                OXYGEN_2WIRE_INTERRUPT_MASK |
0471                OXYGEN_2WIRE_SPEED_STANDARD);
0472     oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
0473     oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
0474     oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
0475     oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
0476                OXYGEN_PLAY_MULTICH_I2S_DAC |
0477                OXYGEN_PLAY_SPDIF_SPDIF |
0478                (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
0479                (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
0480                (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
0481                (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
0482     oxygen_write8(chip, OXYGEN_REC_ROUTING,
0483               OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
0484               OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
0485               OXYGEN_REC_C_ROUTE_SPDIF);
0486     oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
0487     oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
0488               (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
0489               (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
0490               (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
0491               (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
0492 
0493     if (chip->has_ac97_0 | chip->has_ac97_1)
0494         oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
0495                   OXYGEN_AC97_INT_READ_DONE |
0496                   OXYGEN_AC97_INT_WRITE_DONE);
0497     else
0498         oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
0499     oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
0500     oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
0501     if (!(chip->has_ac97_0 | chip->has_ac97_1))
0502         oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
0503                   OXYGEN_AC97_CLOCK_DISABLE);
0504     if (!chip->has_ac97_0) {
0505         oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
0506                   OXYGEN_AC97_NO_CODEC_0);
0507     } else {
0508         oxygen_write_ac97(chip, 0, AC97_RESET, 0);
0509         msleep(1);
0510         oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
0511                      CM9780_GPIO0IO | CM9780_GPIO1IO);
0512         oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
0513                      CM9780_BSTSEL | CM9780_STRO_MIC |
0514                      CM9780_MIX2FR | CM9780_PCBSW);
0515         oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
0516                      CM9780_RSOE | CM9780_CBOE |
0517                      CM9780_SSOE | CM9780_FROE |
0518                      CM9780_MIC2MIC | CM9780_LI2LI);
0519         oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
0520         oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
0521         oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
0522         oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
0523         oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
0524         oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
0525         oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
0526         oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
0527         oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
0528         oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
0529         oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
0530                        CM9780_GPO0);
0531         /* power down unused ADCs and DACs */
0532         oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
0533                      AC97_PD_PR0 | AC97_PD_PR1);
0534         oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
0535                      AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
0536     }
0537     if (chip->has_ac97_1) {
0538         oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
0539                   OXYGEN_AC97_CODEC1_SLOT3 |
0540                   OXYGEN_AC97_CODEC1_SLOT4);
0541         oxygen_write_ac97(chip, 1, AC97_RESET, 0);
0542         msleep(1);
0543         oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
0544         oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
0545         oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
0546         oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
0547         oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
0548         oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
0549         oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
0550         oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
0551         oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
0552         oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
0553         oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
0554         oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
0555     }
0556 }
0557 
0558 static void oxygen_shutdown(struct oxygen *chip)
0559 {
0560     spin_lock_irq(&chip->reg_lock);
0561     chip->interrupt_mask = 0;
0562     chip->pcm_running = 0;
0563     oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
0564     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
0565     spin_unlock_irq(&chip->reg_lock);
0566 }
0567 
0568 static void oxygen_card_free(struct snd_card *card)
0569 {
0570     struct oxygen *chip = card->private_data;
0571 
0572     oxygen_shutdown(chip);
0573     flush_work(&chip->spdif_input_bits_work);
0574     flush_work(&chip->gpio_work);
0575     chip->model.cleanup(chip);
0576     mutex_destroy(&chip->mutex);
0577 }
0578 
0579 static int __oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
0580              struct module *owner,
0581              const struct pci_device_id *ids,
0582              int (*get_model)(struct oxygen *chip,
0583                       const struct pci_device_id *id
0584                      )
0585             )
0586 {
0587     struct snd_card *card;
0588     struct oxygen *chip;
0589     const struct pci_device_id *pci_id;
0590     int err;
0591 
0592     err = snd_devm_card_new(&pci->dev, index, id, owner,
0593                 sizeof(*chip), &card);
0594     if (err < 0)
0595         return err;
0596 
0597     chip = card->private_data;
0598     chip->card = card;
0599     chip->pci = pci;
0600     chip->irq = -1;
0601     spin_lock_init(&chip->reg_lock);
0602     mutex_init(&chip->mutex);
0603     INIT_WORK(&chip->spdif_input_bits_work,
0604           oxygen_spdif_input_bits_changed);
0605     INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
0606     init_waitqueue_head(&chip->ac97_waitqueue);
0607 
0608     err = pcim_enable_device(pci);
0609     if (err < 0)
0610         return err;
0611 
0612     err = pci_request_regions(pci, DRIVER);
0613     if (err < 0) {
0614         dev_err(card->dev, "cannot reserve PCI resources\n");
0615         return err;
0616     }
0617 
0618     if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
0619         pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
0620         dev_err(card->dev, "invalid PCI I/O range\n");
0621         return -ENXIO;
0622     }
0623     chip->addr = pci_resource_start(pci, 0);
0624 
0625     pci_id = oxygen_search_pci_id(chip, ids);
0626     if (!pci_id)
0627         return -ENODEV;
0628 
0629     oxygen_restore_eeprom(chip, pci_id);
0630     err = get_model(chip, pci_id);
0631     if (err < 0)
0632         return err;
0633 
0634     if (chip->model.model_data_size) {
0635         chip->model_data = devm_kzalloc(&pci->dev,
0636                         chip->model.model_data_size,
0637                         GFP_KERNEL);
0638         if (!chip->model_data)
0639             return -ENOMEM;
0640     }
0641 
0642     pci_set_master(pci);
0643     card->private_free = oxygen_card_free;
0644 
0645     configure_pcie_bridge(pci);
0646     oxygen_init(chip);
0647     chip->model.init(chip);
0648 
0649     err = devm_request_irq(&pci->dev, pci->irq, oxygen_interrupt,
0650                    IRQF_SHARED, KBUILD_MODNAME, chip);
0651     if (err < 0) {
0652         dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
0653         return err;
0654     }
0655     chip->irq = pci->irq;
0656     card->sync_irq = chip->irq;
0657 
0658     strcpy(card->driver, chip->model.chip);
0659     strcpy(card->shortname, chip->model.shortname);
0660     sprintf(card->longname, "%s at %#lx, irq %i",
0661         chip->model.longname, chip->addr, chip->irq);
0662     strcpy(card->mixername, chip->model.chip);
0663     snd_component_add(card, chip->model.chip);
0664 
0665     err = oxygen_pcm_init(chip);
0666     if (err < 0)
0667         return err;
0668 
0669     err = oxygen_mixer_init(chip);
0670     if (err < 0)
0671         return err;
0672 
0673     if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
0674         unsigned int info_flags =
0675                 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
0676         if (chip->model.device_config & MIDI_OUTPUT)
0677             info_flags |= MPU401_INFO_OUTPUT;
0678         if (chip->model.device_config & MIDI_INPUT)
0679             info_flags |= MPU401_INFO_INPUT;
0680         err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
0681                       chip->addr + OXYGEN_MPU401,
0682                       info_flags, -1, &chip->midi);
0683         if (err < 0)
0684             return err;
0685     }
0686 
0687     oxygen_proc_init(chip);
0688 
0689     spin_lock_irq(&chip->reg_lock);
0690     if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
0691         chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
0692     if (chip->has_ac97_0 | chip->has_ac97_1)
0693         chip->interrupt_mask |= OXYGEN_INT_AC97;
0694     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
0695     spin_unlock_irq(&chip->reg_lock);
0696 
0697     err = snd_card_register(card);
0698     if (err < 0)
0699         return err;
0700 
0701     pci_set_drvdata(pci, card);
0702     return 0;
0703 }
0704 
0705 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
0706              struct module *owner,
0707              const struct pci_device_id *ids,
0708              int (*get_model)(struct oxygen *chip,
0709                       const struct pci_device_id *id))
0710 {
0711     return snd_card_free_on_error(&pci->dev,
0712                       __oxygen_pci_probe(pci, index, id, owner, ids, get_model));
0713 }
0714 EXPORT_SYMBOL(oxygen_pci_probe);
0715 
0716 #ifdef CONFIG_PM_SLEEP
0717 static int oxygen_pci_suspend(struct device *dev)
0718 {
0719     struct snd_card *card = dev_get_drvdata(dev);
0720     struct oxygen *chip = card->private_data;
0721     unsigned int saved_interrupt_mask;
0722 
0723     snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
0724 
0725     if (chip->model.suspend)
0726         chip->model.suspend(chip);
0727 
0728     spin_lock_irq(&chip->reg_lock);
0729     saved_interrupt_mask = chip->interrupt_mask;
0730     chip->interrupt_mask = 0;
0731     oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
0732     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
0733     spin_unlock_irq(&chip->reg_lock);
0734 
0735     flush_work(&chip->spdif_input_bits_work);
0736     flush_work(&chip->gpio_work);
0737     chip->interrupt_mask = saved_interrupt_mask;
0738     return 0;
0739 }
0740 
0741 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
0742     0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
0743     0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
0744 };
0745 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
0746     { 0x18284fa2, 0x03060000 },
0747     { 0x00007fa6, 0x00200000 }
0748 };
0749 
0750 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
0751 {
0752     return bitmap[bit / 32] & (1 << (bit & 31));
0753 }
0754 
0755 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
0756 {
0757     unsigned int i;
0758 
0759     oxygen_write_ac97(chip, codec, AC97_RESET, 0);
0760     msleep(1);
0761     for (i = 1; i < 0x40; ++i)
0762         if (is_bit_set(ac97_registers_to_restore[codec], i))
0763             oxygen_write_ac97(chip, codec, i * 2,
0764                       chip->saved_ac97_registers[codec][i]);
0765 }
0766 
0767 static int oxygen_pci_resume(struct device *dev)
0768 {
0769     struct snd_card *card = dev_get_drvdata(dev);
0770     struct oxygen *chip = card->private_data;
0771     unsigned int i;
0772 
0773     oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
0774     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
0775     for (i = 0; i < OXYGEN_IO_SIZE; ++i)
0776         if (is_bit_set(registers_to_restore, i))
0777             oxygen_write8(chip, i, chip->saved_registers._8[i]);
0778     if (chip->has_ac97_0)
0779         oxygen_restore_ac97(chip, 0);
0780     if (chip->has_ac97_1)
0781         oxygen_restore_ac97(chip, 1);
0782 
0783     if (chip->model.resume)
0784         chip->model.resume(chip);
0785 
0786     oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
0787 
0788     snd_power_change_state(card, SNDRV_CTL_POWER_D0);
0789     return 0;
0790 }
0791 
0792 SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
0793 EXPORT_SYMBOL(oxygen_pci_pm);
0794 #endif /* CONFIG_PM_SLEEP */
0795 
0796 void oxygen_pci_shutdown(struct pci_dev *pci)
0797 {
0798     struct snd_card *card = pci_get_drvdata(pci);
0799     struct oxygen *chip = card->private_data;
0800 
0801     oxygen_shutdown(chip);
0802     chip->model.cleanup(chip);
0803 }
0804 EXPORT_SYMBOL(oxygen_pci_shutdown);
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