pci/oxygen/oxygen_io.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * C-Media CMI8788 driver - helper functions
0004  *
0005  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
0006  */
0007
0008 #include <linux/delay.h>
0009 #include <linux/sched.h>
0010 #include <linux/export.h>
0011 #include <linux/io.h>
0012 #include <sound/core.h>
0013 #include <sound/mpu401.h>
0014 #include "oxygen.h"
0015
0016 u8 oxygen_read8(struct oxygen *chip, unsigned int reg)
0017 {
0018     return inb(chip->addr + reg);
0019 }
0020 EXPORT_SYMBOL(oxygen_read8);
0021
0022 u16 oxygen_read16(struct oxygen *chip, unsigned int reg)
0023 {
0024     return inw(chip->addr + reg);
0025 }
0026 EXPORT_SYMBOL(oxygen_read16);
0027
0028 u32 oxygen_read32(struct oxygen *chip, unsigned int reg)
0029 {
0030     return inl(chip->addr + reg);
0031 }
0032 EXPORT_SYMBOL(oxygen_read32);
0033
0034 void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value)
0035 {
0036     outb(value, chip->addr + reg);
0037     chip->saved_registers._8[reg] = value;
0038 }
0039 EXPORT_SYMBOL(oxygen_write8);
0040
0041 void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value)
0042 {
0043     outw(value, chip->addr + reg);
0044     chip->saved_registers._16[reg / 2] = cpu_to_le16(value);
0045 }
0046 EXPORT_SYMBOL(oxygen_write16);
0047
0048 void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value)
0049 {
0050     outl(value, chip->addr + reg);
0051     chip->saved_registers._32[reg / 4] = cpu_to_le32(value);
0052 }
0053 EXPORT_SYMBOL(oxygen_write32);
0054
0055 void oxygen_write8_masked(struct oxygen *chip, unsigned int reg,
0056               u8 value, u8 mask)
0057 {
0058     u8 tmp = inb(chip->addr + reg);
0059     tmp &= ~mask;
0060     tmp |= value & mask;
0061     outb(tmp, chip->addr + reg);
0062     chip->saved_registers._8[reg] = tmp;
0063 }
0064 EXPORT_SYMBOL(oxygen_write8_masked);
0065
0066 void oxygen_write16_masked(struct oxygen *chip, unsigned int reg,
0067                u16 value, u16 mask)
0068 {
0069     u16 tmp = inw(chip->addr + reg);
0070     tmp &= ~mask;
0071     tmp |= value & mask;
0072     outw(tmp, chip->addr + reg);
0073     chip->saved_registers._16[reg / 2] = cpu_to_le16(tmp);
0074 }
0075 EXPORT_SYMBOL(oxygen_write16_masked);
0076
0077 void oxygen_write32_masked(struct oxygen *chip, unsigned int reg,
0078                u32 value, u32 mask)
0079 {
0080     u32 tmp = inl(chip->addr + reg);
0081     tmp &= ~mask;
0082     tmp |= value & mask;
0083     outl(tmp, chip->addr + reg);
0084     chip->saved_registers._32[reg / 4] = cpu_to_le32(tmp);
0085 }
0086 EXPORT_SYMBOL(oxygen_write32_masked);
0087
0088 static int oxygen_ac97_wait(struct oxygen *chip, unsigned int mask)
0089 {
0090     u8 status = 0;
0091
0092     /*
0093      * Reading the status register also clears the bits, so we have to save
0094      * the read bits in status.
0095      */
0096     wait_event_timeout(chip->ac97_waitqueue,
0097                ({ status |= oxygen_read8(chip, OXYGEN_AC97_INTERRUPT_STATUS);
0098                   status & mask; }),
0099                msecs_to_jiffies(1) + 1);
0100     /*
0101      * Check even after a timeout because this function should not require
0102      * the AC'97 interrupt to be enabled.
0103      */
0104     status |= oxygen_read8(chip, OXYGEN_AC97_INTERRUPT_STATUS);
0105     return status & mask ? 0 : -EIO;
0106 }
0107
0108 /*
0109  * About 10% of AC'97 register reads or writes fail to complete, but even those
0110  * where the controller indicates completion aren't guaranteed to have actually
0111  * happened.
0112  *
0113  * It's hard to assign blame to either the controller or the codec because both
0114  * were made by C-Media ...
0115  */
0116
0117 void oxygen_write_ac97(struct oxygen *chip, unsigned int codec,
0118                unsigned int index, u16 data)
0119 {
0120     unsigned int count, succeeded;
0121     u32 reg;
0122
0123     reg = data;
0124     reg |= index << OXYGEN_AC97_REG_ADDR_SHIFT;
0125     reg |= OXYGEN_AC97_REG_DIR_WRITE;
0126     reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT;
0127     succeeded = 0;
0128     for (count = 5; count > 0; --count) {
0129         udelay(5);
0130         oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
0131         /* require two "completed" writes, just to be sure */
0132         if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_WRITE_DONE) >= 0 &&
0133             ++succeeded >= 2) {
0134             chip->saved_ac97_registers[codec][index / 2] = data;
0135             return;
0136         }
0137     }
0138     dev_err(chip->card->dev, "AC'97 write timeout\n");
0139 }
0140 EXPORT_SYMBOL(oxygen_write_ac97);
0141
0142 u16 oxygen_read_ac97(struct oxygen *chip, unsigned int codec,
0143              unsigned int index)
0144 {
0145     unsigned int count;
0146     unsigned int last_read = UINT_MAX;
0147     u32 reg;
0148
0149     reg = index << OXYGEN_AC97_REG_ADDR_SHIFT;
0150     reg |= OXYGEN_AC97_REG_DIR_READ;
0151     reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT;
0152     for (count = 5; count > 0; --count) {
0153         udelay(5);
0154         oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
0155         udelay(10);
0156         if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_READ_DONE) >= 0) {
0157             u16 value = oxygen_read16(chip, OXYGEN_AC97_REGS);
0158             /* we require two consecutive reads of the same value */
0159             if (value == last_read)
0160                 return value;
0161             last_read = value;
0162             /*
0163              * Invert the register value bits to make sure that two
0164              * consecutive unsuccessful reads do not return the same
0165              * value.
0166              */
0167             reg ^= 0xffff;
0168         }
0169     }
0170     dev_err(chip->card->dev, "AC'97 read timeout on codec %u\n", codec);
0171     return 0;
0172 }
0173 EXPORT_SYMBOL(oxygen_read_ac97);
0174
0175 void oxygen_write_ac97_masked(struct oxygen *chip, unsigned int codec,
0176                   unsigned int index, u16 data, u16 mask)
0177 {
0178     u16 value = oxygen_read_ac97(chip, codec, index);
0179     value &= ~mask;
0180     value |= data & mask;
0181     oxygen_write_ac97(chip, codec, index, value);
0182 }
0183 EXPORT_SYMBOL(oxygen_write_ac97_masked);
0184
0185 static int oxygen_wait_spi(struct oxygen *chip)
0186 {
0187     unsigned int count;
0188
0189     /*
0190      * Higher timeout to be sure: 200 us;
0191      * actual transaction should not need more than 40 us.
0192      */
0193     for (count = 50; count > 0; count--) {
0194         udelay(4);
0195         if ((oxygen_read8(chip, OXYGEN_SPI_CONTROL) &
0196                         OXYGEN_SPI_BUSY) == 0)
0197             return 0;
0198     }
0199     dev_err(chip->card->dev, "oxygen: SPI wait timeout\n");
0200     return -EIO;
0201 }
0202
0203 int oxygen_write_spi(struct oxygen *chip, u8 control, unsigned int data)
0204 {
0205     /*
0206      * We need to wait AFTER initiating the SPI transaction,
0207      * otherwise read operations will not work.
0208      */
0209     oxygen_write8(chip, OXYGEN_SPI_DATA1, data);
0210     oxygen_write8(chip, OXYGEN_SPI_DATA2, data >> 8);
0211     if (control & OXYGEN_SPI_DATA_LENGTH_3)
0212         oxygen_write8(chip, OXYGEN_SPI_DATA3, data >> 16);
0213     oxygen_write8(chip, OXYGEN_SPI_CONTROL, control);
0214     return oxygen_wait_spi(chip);
0215 }
0216 EXPORT_SYMBOL(oxygen_write_spi);
0217
0218 void oxygen_write_i2c(struct oxygen *chip, u8 device, u8 map, u8 data)
0219 {
0220     /* should not need more than about 300 us */
0221     msleep(1);
0222
0223     oxygen_write8(chip, OXYGEN_2WIRE_MAP, map);
0224     oxygen_write8(chip, OXYGEN_2WIRE_DATA, data);
0225     oxygen_write8(chip, OXYGEN_2WIRE_CONTROL,
0226               device | OXYGEN_2WIRE_DIR_WRITE);
0227 }
0228 EXPORT_SYMBOL(oxygen_write_i2c);
0229
0230 static void _write_uart(struct oxygen *chip, unsigned int port, u8 data)
0231 {
0232     if (oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_TX_FULL)
0233         msleep(1);
0234     oxygen_write8(chip, OXYGEN_MPU401 + port, data);
0235 }
0236
0237 void oxygen_reset_uart(struct oxygen *chip)
0238 {
0239     _write_uart(chip, 1, MPU401_RESET);
0240     msleep(1); /* wait for ACK */
0241     _write_uart(chip, 1, MPU401_ENTER_UART);
0242 }
0243 EXPORT_SYMBOL(oxygen_reset_uart);
0244
0245 void oxygen_write_uart(struct oxygen *chip, u8 data)
0246 {
0247     _write_uart(chip, 0, data);
0248 }
0249 EXPORT_SYMBOL(oxygen_write_uart);
0250
0251 u16 oxygen_read_eeprom(struct oxygen *chip, unsigned int index)
0252 {
0253     unsigned int timeout;
0254
0255     oxygen_write8(chip, OXYGEN_EEPROM_CONTROL,
0256               index | OXYGEN_EEPROM_DIR_READ);
0257     for (timeout = 0; timeout < 100; ++timeout) {
0258         udelay(1);
0259         if (!(oxygen_read8(chip, OXYGEN_EEPROM_STATUS)
0260               & OXYGEN_EEPROM_BUSY))
0261             break;
0262     }
0263     return oxygen_read16(chip, OXYGEN_EEPROM_DATA);
0264 }
0265
0266 void oxygen_write_eeprom(struct oxygen *chip, unsigned int index, u16 value)
0267 {
0268     unsigned int timeout;
0269
0270     oxygen_write16(chip, OXYGEN_EEPROM_DATA, value);
0271     oxygen_write8(chip, OXYGEN_EEPROM_CONTROL,
0272               index | OXYGEN_EEPROM_DIR_WRITE);
0273     for (timeout = 0; timeout < 10; ++timeout) {
0274         msleep(1);
0275         if (!(oxygen_read8(chip, OXYGEN_EEPROM_STATUS)
0276               & OXYGEN_EEPROM_BUSY))
0277             return;
0278     }
0279     dev_err(chip->card->dev, "EEPROM write timeout\n");
0280 }