pci/mixart/mixart_hwdep.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Driver for Digigram miXart soundcards
0004  *
0005  * definitions and makros for basic card access
0006  *
0007  * Copyright (c) 2003 by Digigram <alsa@digigram.com>
0008  */
0009
0010 #ifndef __SOUND_MIXART_HWDEP_H
0011 #define __SOUND_MIXART_HWDEP_H
0012
0013 #include <sound/hwdep.h>
0014
0015 #ifndef readl_be
0016 #define readl_be(x) be32_to_cpu((__force __be32)__raw_readl(x))
0017 #endif
0018
0019 #ifndef writel_be
0020 #define writel_be(data,addr) __raw_writel((__force u32)cpu_to_be32(data),addr)
0021 #endif
0022
0023 #ifndef readl_le
0024 #define readl_le(x) le32_to_cpu((__force __le32)__raw_readl(x))
0025 #endif
0026
0027 #ifndef writel_le
0028 #define writel_le(data,addr) __raw_writel((__force u32)cpu_to_le32(data),addr)
0029 #endif
0030
0031 #define MIXART_MEM(mgr,x)   ((mgr)->mem[0].virt + (x))
0032 #define MIXART_REG(mgr,x)   ((mgr)->mem[1].virt + (x))
0033
0034
0035 /* Daughter board Type */
0036 #define DAUGHTER_TYPE_MASK     0x0F
0037 #define DAUGHTER_VER_MASK      0xF0
0038 #define DAUGHTER_TYPEVER_MASK  (DAUGHTER_TYPE_MASK|DAUGHTER_VER_MASK)
0039
0040 #define MIXART_DAUGHTER_TYPE_NONE     0x00
0041 #define MIXART_DAUGHTER_TYPE_COBRANET 0x08
0042 #define MIXART_DAUGHTER_TYPE_AES      0x0E
0043
0044
0045
0046 #define MIXART_BA0_SIZE     (16 * 1024 * 1024) /* 16M */
0047 #define MIXART_BA1_SIZE     (4  * 1024)        /* 4k */
0048
0049 /*
0050  * -----------BAR 0 --------------------------------------------------------------------------------------------------------
0051  */
0052 #define  MIXART_PSEUDOREG                          0x2000                    /* base address for pseudoregister */
0053
0054 #define  MIXART_PSEUDOREG_BOARDNUMBER              MIXART_PSEUDOREG+0        /* board number */
0055
0056 /* perfmeter (available when elf loaded)*/
0057 #define  MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET  MIXART_PSEUDOREG+0x70     /* streaming load */
0058 #define  MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET  MIXART_PSEUDOREG+0x78     /* system load (reference)*/
0059 #define  MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET  MIXART_PSEUDOREG+0x7C     /* mailbox load */
0060 #define  MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET  MIXART_PSEUDOREG+0x74     /* interrupt handling  load */
0061
0062 /* motherboard xilinx loader info */
0063 #define  MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET    MIXART_PSEUDOREG+0x9C     /* 0x00600000 */
0064 #define  MIXART_PSEUDOREG_MXLX_SIZE_OFFSET         MIXART_PSEUDOREG+0xA0     /* xilinx size in bytes */
0065 #define  MIXART_PSEUDOREG_MXLX_STATUS_OFFSET       MIXART_PSEUDOREG+0xA4     /* status = EMBEBBED_STAT_XXX */
0066
0067 /* elf loader info */
0068 #define  MIXART_PSEUDOREG_ELF_STATUS_OFFSET        MIXART_PSEUDOREG+0xB0     /* status = EMBEBBED_STAT_XXX */
0069
0070 /*
0071 *  after the elf code is loaded, and the flowtable info was passed to it,
0072 *  the driver polls on this address, until it shows 1 (presence) or 2 (absence)
0073 *  once it is non-zero, the daughter board type may be read
0074 */
0075 #define  MIXART_PSEUDOREG_DBRD_PRESENCE_OFFSET     MIXART_PSEUDOREG+0x990
0076
0077 /* Global info structure */
0078 #define  MIXART_PSEUDOREG_DBRD_TYPE_OFFSET         MIXART_PSEUDOREG+0x994    /* Type and version of daughterboard  */
0079
0080
0081 /* daughterboard xilinx loader info */
0082 #define  MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET    MIXART_PSEUDOREG+0x998    /* get the address here where to write the file */
0083 #define  MIXART_PSEUDOREG_DXLX_SIZE_OFFSET         MIXART_PSEUDOREG+0x99C    /* xilinx size in bytes */
0084 #define  MIXART_PSEUDOREG_DXLX_STATUS_OFFSET       MIXART_PSEUDOREG+0x9A0    /* status = EMBEBBED_STAT_XXX */
0085
0086 /*  */
0087 #define  MIXART_FLOWTABLE_PTR                      0x3000                    /* pointer to flow table */
0088
0089 /* mailbox addresses  */
0090
0091 /* message DRV -> EMB */
0092 #define MSG_INBOUND_POST_HEAD       0x010008    /* DRV posts MF + increment4 */
0093 #define MSG_INBOUND_POST_TAIL       0x01000C    /* EMB gets MF + increment4 */
0094 /* message EMB -> DRV */
0095 #define MSG_OUTBOUND_POST_TAIL      0x01001C    /* DRV gets MF + increment4 */
0096 #define MSG_OUTBOUND_POST_HEAD      0x010018    /* EMB posts MF + increment4 */
0097 /* Get Free Frames */
0098 #define MSG_INBOUND_FREE_TAIL       0x010004    /* DRV gets MFA + increment4 */
0099 #define MSG_OUTBOUND_FREE_TAIL      0x010014    /* EMB gets MFA + increment4 */
0100 /* Put Free Frames */
0101 #define MSG_OUTBOUND_FREE_HEAD      0x010010    /* DRV puts MFA + increment4 */
0102 #define MSG_INBOUND_FREE_HEAD       0x010000    /* EMB puts MFA + increment4 */
0103
0104 /* firmware addresses of the message fifos */
0105 #define MSG_BOUND_STACK_SIZE        0x004000    /* size of each following stack */
0106 /* posted messages */
0107 #define MSG_OUTBOUND_POST_STACK     0x108000    /* stack of messages to the DRV */
0108 #define MSG_INBOUND_POST_STACK      0x104000    /* stack of messages to the EMB */
0109 /* available empty messages */
0110 #define MSG_OUTBOUND_FREE_STACK     0x10C000    /* stack of free enveloped for EMB */
0111 #define MSG_INBOUND_FREE_STACK      0x100000    /* stack of free enveloped for DRV */
0112
0113
0114 /* defines for mailbox message frames */
0115 #define MSG_FRAME_OFFSET            0x64
0116 #define MSG_FRAME_SIZE              0x6400
0117 #define MSG_FRAME_NUMBER            32
0118 #define MSG_FROM_AGENT_ITMF_OFFSET  (MSG_FRAME_OFFSET + (MSG_FRAME_SIZE * MSG_FRAME_NUMBER))
0119 #define MSG_TO_AGENT_ITMF_OFFSET    (MSG_FROM_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
0120 #define MSG_HOST_RSC_PROTECTION     (MSG_TO_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
0121 #define MSG_AGENT_RSC_PROTECTION    (MSG_HOST_RSC_PROTECTION + 4)
0122
0123
0124 /*
0125  * -----------BAR 1 --------------------------------------------------------------------------------------------------------
0126  */
0127
0128 /* interrupt addresses and constants */
0129 #define MIXART_PCI_OMIMR_OFFSET                 0x34    /* outbound message interrupt mask register */
0130 #define MIXART_PCI_OMISR_OFFSET                 0x30    /* outbound message interrupt status register */
0131 #define MIXART_PCI_ODBR_OFFSET                  0x60    /* outbound doorbell register */
0132
0133 #define MIXART_BA1_BRUTAL_RESET_OFFSET          0x68    /* write 1 in LSBit to reset board */
0134
0135 #define MIXART_HOST_ALL_INTERRUPT_MASKED        0x02B   /* 0000 0010 1011 */
0136 #define MIXART_ALLOW_OUTBOUND_DOORBELL          0x023   /* 0000 0010 0011 */
0137 #define MIXART_OIDI                             0x008   /* 0000 0000 1000 */
0138
0139
0140 int snd_mixart_setup_firmware(struct mixart_mgr *mgr);
0141
0142 #endif /* __SOUND_MIXART_HWDEP_H */