pci/lx6464es/lx_defs.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* -*- linux-c -*- *
0003  *
0004  * ALSA driver for the digigram lx6464es interface
0005  * adapted upstream headers
0006  *
0007  * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
0008  */
0009
0010 #ifndef LX_DEFS_H
0011 #define LX_DEFS_H
0012
0013 /* code adapted from ethersound.h */
0014 #define XES_FREQ_COUNT8_MASK    0x00001FFF /* compteur 25MHz entre 8 ech. */
0015 #define XES_FREQ_COUNT8_44_MIN  0x00001288 /* 25M /
0016                         * [ 44k - ( 44.1k + 48k ) / 2 ]
0017                         * * 8 */
0018 #define XES_FREQ_COUNT8_44_MAX  0x000010F0 /* 25M / [ ( 44.1k + 48k ) / 2 ]
0019                         * * 8 */
0020 #define XES_FREQ_COUNT8_48_MAX  0x00000F08 /* 25M /
0021                         * [ 48k + ( 44.1k + 48k ) / 2 ]
0022                         * * 8 */
0023
0024 /* code adapted from LXES_registers.h */
0025
0026 #define IOCR_OUTPUTS_OFFSET 0   /* (rw) offset for the number of OUTs in the
0027                  * ConfES register. */
0028 #define IOCR_INPUTS_OFFSET  8   /* (rw) offset for the number of INs in the
0029                  * ConfES register. */
0030 #define FREQ_RATIO_OFFSET  19   /* (rw) offset for frequency ratio in the
0031                  * ConfES register. */
0032 #define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:
0033                      * sample rate = frequency rate. */
0034
0035 #define CONFES_READ_PART_MASK   0x00070000
0036 #define CONFES_WRITE_PART_MASK  0x00F80000
0037
0038 /* code adapted from if_drv_mb.h */
0039
0040 #define MASK_SYS_STATUS_ERROR   (1L << 31) /* events that lead to a PCI irq if
0041                         * not yet pending */
0042 #define MASK_SYS_STATUS_URUN    (1L << 30)
0043 #define MASK_SYS_STATUS_ORUN    (1L << 29)
0044 #define MASK_SYS_STATUS_EOBO    (1L << 28)
0045 #define MASK_SYS_STATUS_EOBI    (1L << 27)
0046 #define MASK_SYS_STATUS_FREQ    (1L << 26)
0047 #define MASK_SYS_STATUS_ESA (1L << 25) /* reserved, this is set by the
0048                         * XES */
0049 #define MASK_SYS_STATUS_TIMER   (1L << 24)
0050
0051 #define MASK_SYS_ASYNC_EVENTS   (MASK_SYS_STATUS_ERROR |        \
0052                  MASK_SYS_STATUS_URUN  |        \
0053                  MASK_SYS_STATUS_ORUN  |        \
0054                  MASK_SYS_STATUS_EOBO  |        \
0055                  MASK_SYS_STATUS_EOBI  |        \
0056                  MASK_SYS_STATUS_FREQ  |        \
0057                  MASK_SYS_STATUS_ESA)
0058
0059 #define MASK_SYS_PCI_EVENTS     (MASK_SYS_ASYNC_EVENTS |    \
0060                      MASK_SYS_STATUS_TIMER)
0061
0062 #define MASK_SYS_TIMER_COUNT    0x0000FFFF
0063
0064 #define MASK_SYS_STATUS_EOT_PLX     (1L << 22) /* event that remains
0065                             * internal: reserved fo end
0066                             * of plx dma */
0067 #define MASK_SYS_STATUS_XES     (1L << 21) /* event that remains
0068                             * internal: pending XES
0069                             * IRQ */
0070 #define MASK_SYS_STATUS_CMD_DONE    (1L << 20) /* alternate command
0071                             * management: notify driver
0072                             * instead of polling */
0073
0074
0075 #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
0076
0077 #define MICROBLAZE_IBL_MIN       32
0078 #define MICROBLAZE_IBL_DEFAULT          128
0079 #define MICROBLAZE_IBL_MAX      512
0080 /* #define MASK_GRANULARITY     (2*MICROBLAZE_IBL_MAX-1) */
0081
0082
0083
0084 /* command opcodes, see reference for details */
0085
0086 /*
0087  the capture bit position in the object_id field in driver commands
0088  depends upon the number of managed channels. For now, 64 IN + 64 OUT are
0089  supported. HOwever, the communication protocol forsees 1024 channels, hence
0090  bit 10 indicates a capture (input) object).
0091 */
0092 #define ID_IS_CAPTURE (1L << 10)
0093 #define ID_OFFSET   13  /* object ID is at the 13th bit in the
0094                  * 1st command word.*/
0095 #define ID_CH_MASK    0x3F
0096 #define OPCODE_OFFSET   24  /* offset of the command opcode in the first
0097                  * command word.*/
0098
0099 enum cmd_mb_opcodes {
0100     CMD_00_INFO_DEBUG           = 0x00,
0101     CMD_01_GET_SYS_CFG      = 0x01,
0102     CMD_02_SET_GRANULARITY      = 0x02,
0103     CMD_03_SET_TIMER_IRQ        = 0x03,
0104     CMD_04_GET_EVENT        = 0x04,
0105     CMD_05_GET_PIPES        = 0x05,
0106
0107     CMD_06_ALLOCATE_PIPE            = 0x06,
0108     CMD_07_RELEASE_PIPE     = 0x07,
0109     CMD_08_ASK_BUFFERS      = 0x08,
0110     CMD_09_STOP_PIPE        = 0x09,
0111     CMD_0A_GET_PIPE_SPL_COUNT   = 0x0a,
0112     CMD_0B_TOGGLE_PIPE_STATE    = 0x0b,
0113
0114     CMD_0C_DEF_STREAM       = 0x0c,
0115     CMD_0D_SET_MUTE         = 0x0d,
0116     CMD_0E_GET_STREAM_SPL_COUNT     = 0x0e,
0117     CMD_0F_UPDATE_BUFFER        = 0x0f,
0118     CMD_10_GET_BUFFER       = 0x10,
0119     CMD_11_CANCEL_BUFFER        = 0x11,
0120     CMD_12_GET_PEAK         = 0x12,
0121     CMD_13_SET_STREAM_STATE     = 0x13,
0122     CMD_14_INVALID          = 0x14,
0123 };
0124
0125 /* pipe states */
0126 enum pipe_state_t {
0127     PSTATE_IDLE = 0,    /* the pipe is not processed in the XES_IRQ
0128                  * (free or stopped, or paused). */
0129     PSTATE_RUN  = 1,    /* sustained play/record state. */
0130     PSTATE_PURGE    = 2,    /* the ES channels are now off, render pipes do
0131                  * not DMA, record pipe do a last DMA. */
0132     PSTATE_ACQUIRE  = 3,    /* the ES channels are now on, render pipes do
0133                  * not yet increase their sample count, record
0134                  * pipes do not DMA. */
0135     PSTATE_CLOSING  = 4,    /* the pipe is releasing, and may not yet
0136                  * receive an "alloc" command. */
0137 };
0138
0139 /* stream states */
0140 enum stream_state_t {
0141     SSTATE_STOP =  0x00,       /* setting to stop resets the stream spl
0142                     * count.*/
0143     SSTATE_RUN  = (0x01 << 0), /* start DMA and spl count handling. */
0144     SSTATE_PAUSE    = (0x01 << 1), /* pause DMA and spl count handling. */
0145 };
0146
0147 /* buffer flags */
0148 enum buffer_flags {
0149     BF_VALID    = 0x80, /* set if the buffer is valid, clear if free.*/
0150     BF_CURRENT  = 0x40, /* set if this is the current buffer (there is
0151                  * always a current buffer).*/
0152     BF_NOTIFY_EOB   = 0x20, /* set if this buffer must cause a PCI event
0153                  * when finished.*/
0154     BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0]
0155                  * by the end of this buffer.*/
0156     BF_64BITS_ADR   = 0x08, /* set if the hi part of the address is valid.*/
0157     BF_xx       = 0x04, /* future extension.*/
0158     BF_EOB      = 0x02, /* set if finished, but not yet free.*/
0159     BF_PAUSE    = 0x01, /* pause stream at buffer end.*/
0160     BF_ZERO     = 0x00, /* no flags (init).*/
0161 };
0162
0163 /*
0164 *   Stream Flags definitions
0165 */
0166 enum stream_flags {
0167     SF_ZERO     = 0x00000000, /* no flags (stream invalid). */
0168     SF_VALID    = 0x10000000, /* the stream has a valid DMA_conf
0169                        * info (setstreamformat). */
0170     SF_XRUN     = 0x20000000, /* the stream is un x-run state. */
0171     SF_START    = 0x40000000, /* the DMA is running.*/
0172     SF_ASIO     = 0x80000000, /* ASIO.*/
0173 };
0174
0175
0176 #define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */
0177 #define PSTATE_OFFSET             28 /* 4 MSBits are status bits */
0178
0179
0180 #define MASK_STREAM_HAS_MAPPING (1L << 12)
0181 #define MASK_STREAM_IS_ASIO (1L <<  9)
0182 #define STREAM_FMT_OFFSET   10   /* the stream fmt bits start at the 10th
0183                       * bit in the command word. */
0184
0185 #define STREAM_FMT_16b          0x02
0186 #define STREAM_FMT_intel        0x01
0187
0188 #define FREQ_FIELD_OFFSET   15  /* offset of the freq field in the response
0189                      * word */
0190
0191 #define BUFF_FLAGS_OFFSET     24 /*  offset of the buffer flags in the
0192                       *  response word. */
0193 #define MASK_DATA_SIZE    0x00FFFFFF /* this must match the field size of
0194                       * datasize in the buffer_t structure. */
0195
0196 #define MASK_BUFFER_ID          0xFF /* the cancel command awaits a buffer ID,
0197                       * may be 0xFF for "current". */
0198
0199
0200 /* code adapted from PcxErr_e.h */
0201
0202 /* Bits masks */
0203
0204 #define ERROR_MASK              0x8000
0205
0206 #define SOURCE_MASK             0x7800
0207
0208 #define E_SOURCE_BOARD          0x4000 /* 8 >> 1 */
0209 #define E_SOURCE_DRV            0x2000 /* 4 >> 1 */
0210 #define E_SOURCE_API            0x1000 /* 2 >> 1 */
0211 /* Error tools */
0212 #define E_SOURCE_TOOLS          0x0800 /* 1 >> 1 */
0213 /* Error pcxaudio */
0214 #define E_SOURCE_AUDIO          0x1800 /* 3 >> 1 */
0215 /* Error virtual pcx */
0216 #define E_SOURCE_VPCX           0x2800 /* 5 >> 1 */
0217 /* Error dispatcher */
0218 #define E_SOURCE_DISPATCHER     0x3000 /* 6 >> 1 */
0219 /* Error from CobraNet firmware */
0220 #define E_SOURCE_COBRANET       0x3800 /* 7 >> 1 */
0221
0222 #define E_SOURCE_USER           0x7800
0223
0224 #define CLASS_MASK              0x0700
0225
0226 #define CODE_MASK               0x00FF
0227
0228 /* Bits values */
0229
0230 /* Values for the error/warning bit */
0231 #define ERROR_VALUE             0x8000
0232 #define WARNING_VALUE           0x0000
0233
0234 /* Class values */
0235 #define E_CLASS_GENERAL                  0x0000
0236 #define E_CLASS_INVALID_CMD              0x0100
0237 #define E_CLASS_INVALID_STD_OBJECT       0x0200
0238 #define E_CLASS_RSRC_IMPOSSIBLE          0x0300
0239 #define E_CLASS_WRONG_CONTEXT            0x0400
0240 #define E_CLASS_BAD_SPECIFIC_PARAMETER   0x0500
0241 #define E_CLASS_REAL_TIME_ERROR          0x0600
0242 #define E_CLASS_DIRECTSHOW               0x0700
0243 #define E_CLASS_FREE                     0x0700
0244
0245
0246 /* Complete DRV error code for the general class */
0247 #define ED_GN           (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_GENERAL)
0248 #define ED_CONCURRENCY                  (ED_GN | 0x01)
0249 #define ED_DSP_CRASHED                  (ED_GN | 0x02)
0250 #define ED_UNKNOWN_BOARD                (ED_GN | 0x03)
0251 #define ED_NOT_INSTALLED                (ED_GN | 0x04)
0252 #define ED_CANNOT_OPEN_SVC_MANAGER      (ED_GN | 0x05)
0253 #define ED_CANNOT_READ_REGISTRY         (ED_GN | 0x06)
0254 #define ED_DSP_VERSION_MISMATCH         (ED_GN | 0x07)
0255 #define ED_UNAVAILABLE_FEATURE          (ED_GN | 0x08)
0256 #define ED_CANCELLED                    (ED_GN | 0x09)
0257 #define ED_NO_RESPONSE_AT_IRQA          (ED_GN | 0x10)
0258 #define ED_INVALID_ADDRESS              (ED_GN | 0x11)
0259 #define ED_DSP_CORRUPTED                (ED_GN | 0x12)
0260 #define ED_PENDING_OPERATION            (ED_GN | 0x13)
0261 #define ED_NET_ALLOCATE_MEMORY_IMPOSSIBLE   (ED_GN | 0x14)
0262 #define ED_NET_REGISTER_ERROR               (ED_GN | 0x15)
0263 #define ED_NET_THREAD_ERROR                 (ED_GN | 0x16)
0264 #define ED_NET_OPEN_ERROR                   (ED_GN | 0x17)
0265 #define ED_NET_CLOSE_ERROR                  (ED_GN | 0x18)
0266 #define ED_NET_NO_MORE_PACKET               (ED_GN | 0x19)
0267 #define ED_NET_NO_MORE_BUFFER               (ED_GN | 0x1A)
0268 #define ED_NET_SEND_ERROR                   (ED_GN | 0x1B)
0269 #define ED_NET_RECEIVE_ERROR                (ED_GN | 0x1C)
0270 #define ED_NET_WRONG_MSG_SIZE               (ED_GN | 0x1D)
0271 #define ED_NET_WAIT_ERROR                   (ED_GN | 0x1E)
0272 #define ED_NET_EEPROM_ERROR                 (ED_GN | 0x1F)
0273 #define ED_INVALID_RS232_COM_NUMBER         (ED_GN | 0x20)
0274 #define ED_INVALID_RS232_INIT               (ED_GN | 0x21)
0275 #define ED_FILE_ERROR                       (ED_GN | 0x22)
0276 #define ED_INVALID_GPIO_CMD                 (ED_GN | 0x23)
0277 #define ED_RS232_ALREADY_OPENED             (ED_GN | 0x24)
0278 #define ED_RS232_NOT_OPENED                 (ED_GN | 0x25)
0279 #define ED_GPIO_ALREADY_OPENED              (ED_GN | 0x26)
0280 #define ED_GPIO_NOT_OPENED                  (ED_GN | 0x27)
0281 #define ED_REGISTRY_ERROR                   (ED_GN | 0x28) /* <- NCX */
0282 #define ED_INVALID_SERVICE                  (ED_GN | 0x29) /* <- NCX */
0283
0284 #define ED_READ_FILE_ALREADY_OPENED     (ED_GN | 0x2a) /* <- Decalage
0285                                 * pour RCX
0286                                 * (old 0x28)
0287                                 * */
0288 #define ED_READ_FILE_INVALID_COMMAND        (ED_GN | 0x2b) /* ~ */
0289 #define ED_READ_FILE_INVALID_PARAMETER      (ED_GN | 0x2c) /* ~ */
0290 #define ED_READ_FILE_ALREADY_CLOSED     (ED_GN | 0x2d) /* ~ */
0291 #define ED_READ_FILE_NO_INFORMATION     (ED_GN | 0x2e) /* ~ */
0292 #define ED_READ_FILE_INVALID_HANDLE     (ED_GN | 0x2f) /* ~ */
0293 #define ED_READ_FILE_END_OF_FILE        (ED_GN | 0x30) /* ~ */
0294 #define ED_READ_FILE_ERROR              (ED_GN | 0x31) /* ~ */
0295
0296 #define ED_DSP_CRASHED_EXC_DSPSTACK_OVERFLOW (ED_GN | 0x32) /* <- Decalage pour
0297                                  * PCX (old 0x14) */
0298 #define ED_DSP_CRASHED_EXC_SYSSTACK_OVERFLOW (ED_GN | 0x33) /* ~ */
0299 #define ED_DSP_CRASHED_EXC_ILLEGAL           (ED_GN | 0x34) /* ~ */
0300 #define ED_DSP_CRASHED_EXC_TIMER_REENTRY     (ED_GN | 0x35) /* ~ */
0301 #define ED_DSP_CRASHED_EXC_FATAL_ERROR       (ED_GN | 0x36) /* ~ */
0302
0303 #define ED_FLASH_PCCARD_NOT_PRESENT          (ED_GN | 0x37)
0304
0305 #define ED_NO_CURRENT_CLOCK                  (ED_GN | 0x38)
0306
0307 /* Complete DRV error code for real time class */
0308 #define ED_RT           (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_REAL_TIME_ERROR)
0309 #define ED_DSP_TIMED_OUT                (ED_RT | 0x01)
0310 #define ED_DSP_CHK_TIMED_OUT            (ED_RT | 0x02)
0311 #define ED_STREAM_OVERRUN               (ED_RT | 0x03)
0312 #define ED_DSP_BUSY                     (ED_RT | 0x04)
0313 #define ED_DSP_SEMAPHORE_TIME_OUT       (ED_RT | 0x05)
0314 #define ED_BOARD_TIME_OUT               (ED_RT | 0x06)
0315 #define ED_XILINX_ERROR                 (ED_RT | 0x07)
0316 #define ED_COBRANET_ITF_NOT_RESPONDING  (ED_RT | 0x08)
0317
0318 /* Complete BOARD error code for the invaid standard object class */
0319 #define EB_ISO          (ERROR_VALUE | E_SOURCE_BOARD | \
0320              E_CLASS_INVALID_STD_OBJECT)
0321 #define EB_INVALID_EFFECT               (EB_ISO | 0x00)
0322 #define EB_INVALID_PIPE                 (EB_ISO | 0x40)
0323 #define EB_INVALID_STREAM               (EB_ISO | 0x80)
0324 #define EB_INVALID_AUDIO                (EB_ISO | 0xC0)
0325
0326 /* Complete BOARD error code for impossible resource allocation class */
0327 #define EB_RI           (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_RSRC_IMPOSSIBLE)
0328 #define EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE (EB_RI | 0x01)
0329 #define EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE           (EB_RI | 0x02)
0330
0331 #define EB_ALLOCATE_MEM_STREAM_IMPOSSIBLE       \
0332     EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE
0333 #define EB_ALLOCATE_MEM_PIPE_IMPOSSIBLE         \
0334     EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE
0335
0336 #define EB_ALLOCATE_DIFFERED_CMD_IMPOSSIBLE     (EB_RI | 0x03)
0337 #define EB_TOO_MANY_DIFFERED_CMD                (EB_RI | 0x04)
0338 #define EB_RBUFFERS_TABLE_OVERFLOW              (EB_RI | 0x05)
0339 #define EB_ALLOCATE_EFFECTS_IMPOSSIBLE          (EB_RI | 0x08)
0340 #define EB_ALLOCATE_EFFECT_POS_IMPOSSIBLE       (EB_RI | 0x09)
0341 #define EB_RBUFFER_NOT_AVAILABLE                (EB_RI | 0x0A)
0342 #define EB_ALLOCATE_CONTEXT_LIII_IMPOSSIBLE     (EB_RI | 0x0B)
0343 #define EB_STATUS_DIALOG_IMPOSSIBLE             (EB_RI | 0x1D)
0344 #define EB_CONTROL_CMD_IMPOSSIBLE               (EB_RI | 0x1E)
0345 #define EB_STATUS_SEND_IMPOSSIBLE               (EB_RI | 0x1F)
0346 #define EB_ALLOCATE_PIPE_IMPOSSIBLE             (EB_RI | 0x40)
0347 #define EB_ALLOCATE_STREAM_IMPOSSIBLE           (EB_RI | 0x80)
0348 #define EB_ALLOCATE_AUDIO_IMPOSSIBLE            (EB_RI | 0xC0)
0349
0350 /* Complete BOARD error code for wrong call context class */
0351 #define EB_WCC          (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_WRONG_CONTEXT)
0352 #define EB_CMD_REFUSED                  (EB_WCC | 0x00)
0353 #define EB_START_STREAM_REFUSED         (EB_WCC | 0xFC)
0354 #define EB_SPC_REFUSED                  (EB_WCC | 0xFD)
0355 #define EB_CSN_REFUSED                  (EB_WCC | 0xFE)
0356 #define EB_CSE_REFUSED                  (EB_WCC | 0xFF)
0357
0358
0359
0360
0361 #endif /* LX_DEFS_H */