pci/lx6464es/lx_core.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* -*- linux-c -*- *
0003  *
0004  * ALSA driver for the digigram lx6464es interface
0005  * low-level interface
0006  *
0007  * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
0008  */
0009
0010 #ifndef LX_CORE_H
0011 #define LX_CORE_H
0012
0013 #include <linux/interrupt.h>
0014
0015 #include "lx_defs.h"
0016
0017 #define REG_CRM_NUMBER      12
0018
0019 struct lx6464es;
0020
0021 /* low-level register access */
0022
0023 /* dsp register access */
0024 enum {
0025     eReg_BASE,
0026     eReg_CSM,
0027     eReg_CRM1,
0028     eReg_CRM2,
0029     eReg_CRM3,
0030     eReg_CRM4,
0031     eReg_CRM5,
0032     eReg_CRM6,
0033     eReg_CRM7,
0034     eReg_CRM8,
0035     eReg_CRM9,
0036     eReg_CRM10,
0037     eReg_CRM11,
0038     eReg_CRM12,
0039
0040     eReg_ICR,
0041     eReg_CVR,
0042     eReg_ISR,
0043     eReg_RXHTXH,
0044     eReg_RXMTXM,
0045     eReg_RHLTXL,
0046     eReg_RESETDSP,
0047
0048     eReg_CSUF,
0049     eReg_CSES,
0050     eReg_CRESMSB,
0051     eReg_CRESLSB,
0052     eReg_ADMACESMSB,
0053     eReg_ADMACESLSB,
0054     eReg_CONFES,
0055
0056     eMaxPortLx
0057 };
0058
0059 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port);
0060 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data);
0061
0062 /* plx register access */
0063 enum {
0064     ePLX_PCICR,
0065
0066     ePLX_MBOX0,
0067     ePLX_MBOX1,
0068     ePLX_MBOX2,
0069     ePLX_MBOX3,
0070     ePLX_MBOX4,
0071     ePLX_MBOX5,
0072     ePLX_MBOX6,
0073     ePLX_MBOX7,
0074
0075     ePLX_L2PCIDB,
0076     ePLX_IRQCS,
0077     ePLX_CHIPSC,
0078
0079     eMaxPort
0080 };
0081
0082 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port);
0083 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data);
0084
0085 /* rhm */
0086 struct lx_rmh {
0087     u16 cmd_len;    /* length of the command to send (WORDs) */
0088     u16 stat_len;   /* length of the status received (WORDs) */
0089     u16 dsp_stat;   /* status type, RMP_SSIZE_XXX */
0090     u16 cmd_idx;    /* index of the command */
0091     u32 cmd[REG_CRM_NUMBER];
0092     u32 stat[REG_CRM_NUMBER];
0093 };
0094
0095
0096 /* low-level dsp access */
0097 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version);
0098 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq);
0099 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran);
0100 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data);
0101 int lx_dsp_get_mac(struct lx6464es *chip);
0102
0103
0104 /* low-level pipe handling */
0105 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
0106              int channels);
0107 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture);
0108 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
0109              u64 *rsample_count);
0110 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate);
0111 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture);
0112 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture);
0113 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture);
0114
0115 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture);
0116 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture);
0117
0118 /* low-level stream handling */
0119 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
0120              u32 pipe, int is_capture);
0121 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
0122             int *rstate);
0123 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
0124                   u64 *r_bytepos);
0125
0126 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
0127             int is_capture, enum stream_state_t state);
0128
0129 static inline int lx_stream_start(struct lx6464es *chip, u32 pipe,
0130                   int is_capture)
0131 {
0132     snd_printdd("->lx_stream_start\n");
0133     return lx_stream_set_state(chip, pipe, is_capture, SSTATE_RUN);
0134 }
0135
0136 static inline int lx_stream_pause(struct lx6464es *chip, u32 pipe,
0137                   int is_capture)
0138 {
0139     snd_printdd("->lx_stream_pause\n");
0140     return lx_stream_set_state(chip, pipe, is_capture, SSTATE_PAUSE);
0141 }
0142
0143 static inline int lx_stream_stop(struct lx6464es *chip, u32 pipe,
0144                  int is_capture)
0145 {
0146     snd_printdd("->lx_stream_stop\n");
0147     return lx_stream_set_state(chip, pipe, is_capture, SSTATE_STOP);
0148 }
0149
0150 /* low-level buffer handling */
0151 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
0152           u32 *r_needed, u32 *r_freed, u32 *size_array);
0153 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
0154            u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
0155            u32 *r_buffer_index);
0156 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
0157            u32 *r_buffer_size);
0158 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
0159              u32 buffer_index);
0160
0161 /* low-level gain/peak handling */
0162 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute);
0163 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
0164            u32 *r_levels);
0165
0166
0167 /* interrupt handling */
0168 irqreturn_t lx_interrupt(int irq, void *dev_id);
0169 irqreturn_t lx_threaded_irq(int irq, void *dev_id);
0170 void lx_irq_enable(struct lx6464es *chip);
0171 void lx_irq_disable(struct lx6464es *chip);
0172
0173
0174 /* Stream Format Header Defines (for LIN and IEEE754) */
0175 #define HEADER_FMT_BASE     HEADER_FMT_BASE_LIN
0176 #define HEADER_FMT_BASE_LIN 0xFED00000
0177 #define HEADER_FMT_BASE_FLOAT   0xFAD00000
0178 #define HEADER_FMT_MONO     0x00000080 /* bit 23 in header_lo. WARNING: old
0179                         * bit 22 is ignored in float
0180                         * format */
0181 #define HEADER_FMT_INTEL    0x00008000
0182 #define HEADER_FMT_16BITS   0x00002000
0183 #define HEADER_FMT_24BITS   0x00004000
0184 #define HEADER_FMT_UPTO11   0x00000200 /* frequency is less or equ. to 11k.
0185                         * */
0186 #define HEADER_FMT_UPTO32   0x00000100 /* frequency is over 11k and less
0187                         * then 32k.*/
0188
0189
0190 #define BIT_FMP_HEADER          23
0191 #define BIT_FMP_SD              22
0192 #define BIT_FMP_MULTICHANNEL    19
0193
0194 #define START_STATE             1
0195 #define PAUSE_STATE             0
0196
0197
0198
0199
0200
0201 /* from PcxAll_e.h */
0202 /* Start/Pause condition for pipes (PCXStartPipe, PCXPausePipe) */
0203 #define START_PAUSE_IMMEDIATE           0
0204 #define START_PAUSE_ON_SYNCHRO          1
0205 #define START_PAUSE_ON_TIME_CODE        2
0206
0207
0208 /* Pipe / Stream state */
0209 #define START_STATE             1
0210 #define PAUSE_STATE             0
0211
0212 static inline void unpack_pointer(dma_addr_t ptr, u32 *r_low, u32 *r_high)
0213 {
0214     *r_low = (u32)(ptr & 0xffffffff);
0215 #if BITS_PER_LONG == 32
0216     *r_high = 0;
0217 #else
0218     *r_high = (u32)((u64)ptr>>32);
0219 #endif
0220 }
0221
0222 #endif /* LX_CORE_H */