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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* -*- linux-c -*- *
0003  *
0004  * ALSA driver for the digigram lx6464es interface
0005  * low-level interface
0006  *
0007  * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
0008  */
0009 
0010 /* #define RMH_DEBUG 1 */
0011 
0012 #include <linux/bitops.h>
0013 #include <linux/module.h>
0014 #include <linux/pci.h>
0015 #include <linux/delay.h>
0016 
0017 #include "lx6464es.h"
0018 #include "lx_core.h"
0019 
0020 /* low-level register access */
0021 
0022 static const unsigned long dsp_port_offsets[] = {
0023     0,
0024     0x400,
0025     0x401,
0026     0x402,
0027     0x403,
0028     0x404,
0029     0x405,
0030     0x406,
0031     0x407,
0032     0x408,
0033     0x409,
0034     0x40a,
0035     0x40b,
0036     0x40c,
0037 
0038     0x410,
0039     0x411,
0040     0x412,
0041     0x413,
0042     0x414,
0043     0x415,
0044     0x416,
0045 
0046     0x420,
0047     0x430,
0048     0x431,
0049     0x432,
0050     0x433,
0051     0x434,
0052     0x440
0053 };
0054 
0055 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
0056 {
0057     void __iomem *base_address = chip->port_dsp_bar;
0058     return base_address + dsp_port_offsets[port]*4;
0059 }
0060 
0061 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
0062 {
0063     void __iomem *address = lx_dsp_register(chip, port);
0064     return ioread32(address);
0065 }
0066 
0067 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data,
0068                    u32 len)
0069 {
0070     u32 __iomem *address = lx_dsp_register(chip, port);
0071     int i;
0072 
0073     /* we cannot use memcpy_fromio */
0074     for (i = 0; i != len; ++i)
0075         data[i] = ioread32(address + i);
0076 }
0077 
0078 
0079 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
0080 {
0081     void __iomem *address = lx_dsp_register(chip, port);
0082     iowrite32(data, address);
0083 }
0084 
0085 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port,
0086                 const u32 *data, u32 len)
0087 {
0088     u32 __iomem *address = lx_dsp_register(chip, port);
0089     int i;
0090 
0091     /* we cannot use memcpy_to */
0092     for (i = 0; i != len; ++i)
0093         iowrite32(data[i], address + i);
0094 }
0095 
0096 
0097 static const unsigned long plx_port_offsets[] = {
0098     0x04,
0099     0x40,
0100     0x44,
0101     0x48,
0102     0x4c,
0103     0x50,
0104     0x54,
0105     0x58,
0106     0x5c,
0107     0x64,
0108     0x68,
0109     0x6C
0110 };
0111 
0112 static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
0113 {
0114     void __iomem *base_address = chip->port_plx_remapped;
0115     return base_address + plx_port_offsets[port];
0116 }
0117 
0118 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
0119 {
0120     void __iomem *address = lx_plx_register(chip, port);
0121     return ioread32(address);
0122 }
0123 
0124 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
0125 {
0126     void __iomem *address = lx_plx_register(chip, port);
0127     iowrite32(data, address);
0128 }
0129 
0130 /* rmh */
0131 
0132 #ifdef CONFIG_SND_DEBUG
0133 #define CMD_NAME(a) a
0134 #else
0135 #define CMD_NAME(a) NULL
0136 #endif
0137 
0138 #define Reg_CSM_MR          0x00000002
0139 #define Reg_CSM_MC          0x00000001
0140 
0141 struct dsp_cmd_info {
0142     u32    dcCodeOp;    /* Op Code of the command (usually 1st 24-bits
0143                  * word).*/
0144     u16    dcCmdLength; /* Command length in words of 24 bits.*/
0145     u16    dcStatusType;    /* Status type: 0 for fixed length, 1 for
0146                  * random. */
0147     u16    dcStatusLength;  /* Status length (if fixed).*/
0148     char  *dcOpName;
0149 };
0150 
0151 /*
0152   Initialization and control data for the Microblaze interface
0153   - OpCode:
0154     the opcode field of the command set at the proper offset
0155   - CmdLength
0156     the number of command words
0157   - StatusType
0158     offset in the status registers: 0 means that the return value may be
0159     different from 0, and must be read
0160   - StatusLength
0161     the number of status words (in addition to the return value)
0162 */
0163 
0164 static const struct dsp_cmd_info dsp_commands[] =
0165 {
0166     { (CMD_00_INFO_DEBUG << OPCODE_OFFSET)          , 1 /*custom*/
0167       , 1   , 0 /**/            , CMD_NAME("INFO_DEBUG") },
0168     { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET)         , 1 /**/
0169       , 1      , 2 /**/         , CMD_NAME("GET_SYS_CFG") },
0170     { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET)         , 1 /**/
0171       , 1      , 0 /**/         , CMD_NAME("SET_GRANULARITY") },
0172     { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET)       , 1 /**/
0173       , 1      , 0 /**/         , CMD_NAME("SET_TIMER_IRQ") },
0174     { (CMD_04_GET_EVENT << OPCODE_OFFSET)           , 1 /**/
0175       , 1      , 0 /*up to 10*/     , CMD_NAME("GET_EVENT") },
0176     { (CMD_05_GET_PIPES << OPCODE_OFFSET)           , 1 /**/
0177       , 1      , 2 /*up to 4*/      , CMD_NAME("GET_PIPES") },
0178     { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET)       , 1 /**/
0179       , 0      , 0 /**/         , CMD_NAME("ALLOCATE_PIPE") },
0180     { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET)        , 1 /**/
0181       , 0      , 0 /**/         , CMD_NAME("RELEASE_PIPE") },
0182     { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET)         , 1 /**/
0183       , 1      , MAX_STREAM_BUFFER  , CMD_NAME("ASK_BUFFERS") },
0184     { (CMD_09_STOP_PIPE << OPCODE_OFFSET)           , 1 /**/
0185       , 0      , 0 /*up to 2*/      , CMD_NAME("STOP_PIPE") },
0186     { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET)          , 1 /**/
0187       , 1      , 1 /*up to 2*/      , CMD_NAME("GET_PIPE_SPL_COUNT") },
0188     { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET)           , 1 /*up to 5*/
0189       , 1      , 0 /**/         , CMD_NAME("TOGGLE_PIPE_STATE") },
0190     { (CMD_0C_DEF_STREAM << OPCODE_OFFSET)          , 1 /*up to 4*/
0191       , 1      , 0 /**/         , CMD_NAME("DEF_STREAM") },
0192     { (CMD_0D_SET_MUTE  << OPCODE_OFFSET)           , 3 /**/
0193       , 1      , 0 /**/         , CMD_NAME("SET_MUTE") },
0194     { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET)        , 1/**/
0195       , 1      , 2 /**/         , CMD_NAME("GET_STREAM_SPL_COUNT") },
0196     { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET)       , 3 /*up to 4*/
0197       , 0      , 1 /**/         , CMD_NAME("UPDATE_BUFFER") },
0198     { (CMD_10_GET_BUFFER << OPCODE_OFFSET)          , 1 /**/
0199       , 1      , 4 /**/         , CMD_NAME("GET_BUFFER") },
0200     { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET)       , 1 /**/
0201       , 1      , 1 /*up to 4*/      , CMD_NAME("CANCEL_BUFFER") },
0202     { (CMD_12_GET_PEAK << OPCODE_OFFSET)            , 1 /**/
0203       , 1      , 1 /**/         , CMD_NAME("GET_PEAK") },
0204     { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET)            , 1 /**/
0205       , 1      , 0 /**/         , CMD_NAME("SET_STREAM_STATE") },
0206 };
0207 
0208 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
0209 {
0210     snd_BUG_ON(cmd >= CMD_14_INVALID);
0211 
0212     rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
0213     rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
0214     rmh->stat_len = dsp_commands[cmd].dcStatusLength;
0215     rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
0216     rmh->cmd_idx = cmd;
0217     memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
0218 
0219 #ifdef CONFIG_SND_DEBUG
0220     memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
0221 #endif
0222 #ifdef RMH_DEBUG
0223     rmh->cmd_idx = cmd;
0224 #endif
0225 }
0226 
0227 #ifdef RMH_DEBUG
0228 #define LXRMH "lx6464es rmh: "
0229 static void lx_message_dump(struct lx_rmh *rmh)
0230 {
0231     u8 idx = rmh->cmd_idx;
0232     int i;
0233 
0234     snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
0235 
0236     for (i = 0; i != rmh->cmd_len; ++i)
0237         snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
0238 
0239     for (i = 0; i != rmh->stat_len; ++i)
0240         snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
0241     snd_printk("\n");
0242 }
0243 #else
0244 static inline void lx_message_dump(struct lx_rmh *rmh)
0245 {}
0246 #endif
0247 
0248 
0249 
0250 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
0251 #define XILINX_TIMEOUT_MS       40
0252 #define XILINX_POLL_NO_SLEEP    100
0253 #define XILINX_POLL_ITERATIONS  150
0254 
0255 
0256 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
0257 {
0258     u32 reg = ED_DSP_TIMED_OUT;
0259     int dwloop;
0260 
0261     if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
0262         dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg);
0263         return -EBUSY;
0264     }
0265 
0266     /* write command */
0267     lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
0268 
0269     /* MicoBlaze gogogo */
0270     lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
0271 
0272     /* wait for device to answer */
0273     for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
0274         if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
0275             if (rmh->dsp_stat == 0)
0276                 reg = lx_dsp_reg_read(chip, eReg_CRM1);
0277             else
0278                 reg = 0;
0279             goto polling_successful;
0280         } else
0281             udelay(1);
0282     }
0283     dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! "
0284            "polling failed\n");
0285 
0286 polling_successful:
0287     if ((reg & ERROR_VALUE) == 0) {
0288         /* read response */
0289         if (rmh->stat_len) {
0290             snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
0291             lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
0292                        rmh->stat_len);
0293         }
0294     } else
0295         dev_err(chip->card->dev, "rmh error: %08x\n", reg);
0296 
0297     /* clear Reg_CSM_MR */
0298     lx_dsp_reg_write(chip, eReg_CSM, 0);
0299 
0300     switch (reg) {
0301     case ED_DSP_TIMED_OUT:
0302         dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n");
0303         return -ETIMEDOUT;
0304 
0305     case ED_DSP_CRASHED:
0306         dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n");
0307         return -EAGAIN;
0308     }
0309 
0310     lx_message_dump(rmh);
0311 
0312     return reg;
0313 }
0314 
0315 
0316 /* low-level dsp access */
0317 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
0318 {
0319     u16 ret;
0320 
0321     mutex_lock(&chip->msg_lock);
0322 
0323     lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
0324     ret = lx_message_send_atomic(chip, &chip->rmh);
0325 
0326     *rdsp_version = chip->rmh.stat[1];
0327     mutex_unlock(&chip->msg_lock);
0328     return ret;
0329 }
0330 
0331 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
0332 {
0333     u16 ret = 0;
0334     u32 freq_raw = 0;
0335     u32 freq = 0;
0336     u32 frequency = 0;
0337 
0338     mutex_lock(&chip->msg_lock);
0339 
0340     lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
0341     ret = lx_message_send_atomic(chip, &chip->rmh);
0342 
0343     if (ret == 0) {
0344         freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
0345         freq = freq_raw & XES_FREQ_COUNT8_MASK;
0346 
0347         if ((freq < XES_FREQ_COUNT8_48_MAX) ||
0348             (freq > XES_FREQ_COUNT8_44_MIN))
0349             frequency = 0; /* unknown */
0350         else if (freq >= XES_FREQ_COUNT8_44_MAX)
0351             frequency = 44100;
0352         else
0353             frequency = 48000;
0354     }
0355 
0356     mutex_unlock(&chip->msg_lock);
0357 
0358     *rfreq = frequency * chip->freq_ratio;
0359 
0360     return ret;
0361 }
0362 
0363 int lx_dsp_get_mac(struct lx6464es *chip)
0364 {
0365     u32 macmsb, maclsb;
0366 
0367     macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
0368     maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
0369 
0370     /* todo: endianess handling */
0371     chip->mac_address[5] = ((u8 *)(&maclsb))[0];
0372     chip->mac_address[4] = ((u8 *)(&maclsb))[1];
0373     chip->mac_address[3] = ((u8 *)(&maclsb))[2];
0374     chip->mac_address[2] = ((u8 *)(&macmsb))[0];
0375     chip->mac_address[1] = ((u8 *)(&macmsb))[1];
0376     chip->mac_address[0] = ((u8 *)(&macmsb))[2];
0377 
0378     return 0;
0379 }
0380 
0381 
0382 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
0383 {
0384     int ret;
0385 
0386     mutex_lock(&chip->msg_lock);
0387 
0388     lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
0389     chip->rmh.cmd[0] |= gran;
0390 
0391     ret = lx_message_send_atomic(chip, &chip->rmh);
0392     mutex_unlock(&chip->msg_lock);
0393     return ret;
0394 }
0395 
0396 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
0397 {
0398     int ret;
0399 
0400     mutex_lock(&chip->msg_lock);
0401 
0402     lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
0403     chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
0404 
0405     ret = lx_message_send_atomic(chip, &chip->rmh);
0406 
0407     if (!ret)
0408         memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
0409 
0410     mutex_unlock(&chip->msg_lock);
0411     return ret;
0412 }
0413 
0414 #define PIPE_INFO_TO_CMD(capture, pipe)                 \
0415     ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
0416 
0417 
0418 
0419 /* low-level pipe handling */
0420 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
0421              int channels)
0422 {
0423     int err;
0424     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0425 
0426     mutex_lock(&chip->msg_lock);
0427     lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
0428 
0429     chip->rmh.cmd[0] |= pipe_cmd;
0430     chip->rmh.cmd[0] |= channels;
0431 
0432     err = lx_message_send_atomic(chip, &chip->rmh);
0433     mutex_unlock(&chip->msg_lock);
0434 
0435     if (err != 0)
0436         dev_err(chip->card->dev, "could not allocate pipe\n");
0437 
0438     return err;
0439 }
0440 
0441 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
0442 {
0443     int err;
0444     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0445 
0446     mutex_lock(&chip->msg_lock);
0447     lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
0448 
0449     chip->rmh.cmd[0] |= pipe_cmd;
0450 
0451     err = lx_message_send_atomic(chip, &chip->rmh);
0452     mutex_unlock(&chip->msg_lock);
0453 
0454     return err;
0455 }
0456 
0457 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
0458           u32 *r_needed, u32 *r_freed, u32 *size_array)
0459 {
0460     int err;
0461     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0462 
0463 #ifdef CONFIG_SND_DEBUG
0464     if (size_array)
0465         memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
0466 #endif
0467 
0468     *r_needed = 0;
0469     *r_freed = 0;
0470 
0471     mutex_lock(&chip->msg_lock);
0472     lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
0473 
0474     chip->rmh.cmd[0] |= pipe_cmd;
0475 
0476     err = lx_message_send_atomic(chip, &chip->rmh);
0477 
0478     if (!err) {
0479         int i;
0480         for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
0481             u32 stat = chip->rmh.stat[i];
0482             if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
0483                 /* finished */
0484                 *r_freed += 1;
0485                 if (size_array)
0486                     size_array[i] = stat & MASK_DATA_SIZE;
0487             } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
0488                    == 0)
0489                 /* free */
0490                 *r_needed += 1;
0491         }
0492 
0493         dev_dbg(chip->card->dev,
0494             "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
0495                 *r_needed, *r_freed);
0496         for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
0497             for (i = 0; i != chip->rmh.stat_len; ++i)
0498                 dev_dbg(chip->card->dev,
0499                     "  stat[%d]: %x, %x\n", i,
0500                         chip->rmh.stat[i],
0501                         chip->rmh.stat[i] & MASK_DATA_SIZE);
0502         }
0503     }
0504 
0505     mutex_unlock(&chip->msg_lock);
0506     return err;
0507 }
0508 
0509 
0510 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
0511 {
0512     int err;
0513     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0514 
0515     mutex_lock(&chip->msg_lock);
0516     lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
0517 
0518     chip->rmh.cmd[0] |= pipe_cmd;
0519 
0520     err = lx_message_send_atomic(chip, &chip->rmh);
0521 
0522     mutex_unlock(&chip->msg_lock);
0523     return err;
0524 }
0525 
0526 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
0527 {
0528     int err;
0529     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0530 
0531     mutex_lock(&chip->msg_lock);
0532     lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
0533 
0534     chip->rmh.cmd[0] |= pipe_cmd;
0535 
0536     err = lx_message_send_atomic(chip, &chip->rmh);
0537 
0538     mutex_unlock(&chip->msg_lock);
0539     return err;
0540 }
0541 
0542 
0543 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
0544 {
0545     int err;
0546 
0547     err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
0548     if (err < 0)
0549         return err;
0550 
0551     err = lx_pipe_toggle_state(chip, pipe, is_capture);
0552 
0553     return err;
0554 }
0555 
0556 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
0557 {
0558     int err = 0;
0559 
0560     err = lx_pipe_wait_for_start(chip, pipe, is_capture);
0561     if (err < 0)
0562         return err;
0563 
0564     err = lx_pipe_toggle_state(chip, pipe, is_capture);
0565 
0566     return err;
0567 }
0568 
0569 
0570 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
0571              u64 *rsample_count)
0572 {
0573     int err;
0574     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0575 
0576     mutex_lock(&chip->msg_lock);
0577     lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
0578 
0579     chip->rmh.cmd[0] |= pipe_cmd;
0580     chip->rmh.stat_len = 2; /* need all words here! */
0581 
0582     err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
0583 
0584     if (err != 0)
0585         dev_err(chip->card->dev,
0586             "could not query pipe's sample count\n");
0587     else {
0588         *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
0589                   << 24)     /* hi part */
0590             + chip->rmh.stat[1]; /* lo part */
0591     }
0592 
0593     mutex_unlock(&chip->msg_lock);
0594     return err;
0595 }
0596 
0597 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
0598 {
0599     int err;
0600     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0601 
0602     mutex_lock(&chip->msg_lock);
0603     lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
0604 
0605     chip->rmh.cmd[0] |= pipe_cmd;
0606 
0607     err = lx_message_send_atomic(chip, &chip->rmh);
0608 
0609     if (err != 0)
0610         dev_err(chip->card->dev, "could not query pipe's state\n");
0611     else
0612         *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
0613 
0614     mutex_unlock(&chip->msg_lock);
0615     return err;
0616 }
0617 
0618 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
0619                   int is_capture, u16 state)
0620 {
0621     int i;
0622 
0623     /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
0624      * timeout 50 ms */
0625     for (i = 0; i != 50; ++i) {
0626         u16 current_state;
0627         int err = lx_pipe_state(chip, pipe, is_capture, &current_state);
0628 
0629         if (err < 0)
0630             return err;
0631 
0632         if (!err && current_state == state)
0633             return 0;
0634 
0635         mdelay(1);
0636     }
0637 
0638     return -ETIMEDOUT;
0639 }
0640 
0641 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
0642 {
0643     return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
0644 }
0645 
0646 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
0647 {
0648     return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
0649 }
0650 
0651 /* low-level stream handling */
0652 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
0653                    int is_capture, enum stream_state_t state)
0654 {
0655     int err;
0656     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0657 
0658     mutex_lock(&chip->msg_lock);
0659     lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
0660 
0661     chip->rmh.cmd[0] |= pipe_cmd;
0662     chip->rmh.cmd[0] |= state;
0663 
0664     err = lx_message_send_atomic(chip, &chip->rmh);
0665     mutex_unlock(&chip->msg_lock);
0666 
0667     return err;
0668 }
0669 
0670 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
0671              u32 pipe, int is_capture)
0672 {
0673     int err;
0674     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0675     u32 channels = runtime->channels;
0676 
0677     mutex_lock(&chip->msg_lock);
0678     lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
0679 
0680     chip->rmh.cmd[0] |= pipe_cmd;
0681 
0682     if (runtime->sample_bits == 16)
0683         /* 16 bit format */
0684         chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
0685 
0686     if (snd_pcm_format_little_endian(runtime->format))
0687         /* little endian/intel format */
0688         chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
0689 
0690     chip->rmh.cmd[0] |= channels-1;
0691 
0692     err = lx_message_send_atomic(chip, &chip->rmh);
0693     mutex_unlock(&chip->msg_lock);
0694 
0695     return err;
0696 }
0697 
0698 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
0699             int *rstate)
0700 {
0701     int err;
0702     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0703 
0704     mutex_lock(&chip->msg_lock);
0705     lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
0706 
0707     chip->rmh.cmd[0] |= pipe_cmd;
0708 
0709     err = lx_message_send_atomic(chip, &chip->rmh);
0710 
0711     *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
0712 
0713     mutex_unlock(&chip->msg_lock);
0714     return err;
0715 }
0716 
0717 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
0718                   u64 *r_bytepos)
0719 {
0720     int err;
0721     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0722 
0723     mutex_lock(&chip->msg_lock);
0724     lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
0725 
0726     chip->rmh.cmd[0] |= pipe_cmd;
0727 
0728     err = lx_message_send_atomic(chip, &chip->rmh);
0729 
0730     *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
0731               << 32)         /* hi part */
0732         + chip->rmh.stat[1]; /* lo part */
0733 
0734     mutex_unlock(&chip->msg_lock);
0735     return err;
0736 }
0737 
0738 /* low-level buffer handling */
0739 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
0740            u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
0741            u32 *r_buffer_index)
0742 {
0743     int err;
0744     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0745 
0746     mutex_lock(&chip->msg_lock);
0747     lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
0748 
0749     chip->rmh.cmd[0] |= pipe_cmd;
0750     chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
0751 
0752     /* todo: pause request, circular buffer */
0753 
0754     chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
0755     chip->rmh.cmd[2] = buf_address_lo;
0756 
0757     if (buf_address_hi) {
0758         chip->rmh.cmd_len = 4;
0759         chip->rmh.cmd[3] = buf_address_hi;
0760         chip->rmh.cmd[0] |= BF_64BITS_ADR;
0761     }
0762 
0763     err = lx_message_send_atomic(chip, &chip->rmh);
0764 
0765     if (err == 0) {
0766         *r_buffer_index = chip->rmh.stat[0];
0767         goto done;
0768     }
0769 
0770     if (err == EB_RBUFFERS_TABLE_OVERFLOW)
0771         dev_err(chip->card->dev,
0772             "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
0773 
0774     if (err == EB_INVALID_STREAM)
0775         dev_err(chip->card->dev,
0776             "lx_buffer_give EB_INVALID_STREAM\n");
0777 
0778     if (err == EB_CMD_REFUSED)
0779         dev_err(chip->card->dev,
0780             "lx_buffer_give EB_CMD_REFUSED\n");
0781 
0782  done:
0783     mutex_unlock(&chip->msg_lock);
0784     return err;
0785 }
0786 
0787 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
0788            u32 *r_buffer_size)
0789 {
0790     int err;
0791     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0792 
0793     mutex_lock(&chip->msg_lock);
0794     lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
0795 
0796     chip->rmh.cmd[0] |= pipe_cmd;
0797     chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
0798                          * microblaze will seek for it */
0799 
0800     err = lx_message_send_atomic(chip, &chip->rmh);
0801 
0802     if (err == 0)
0803         *r_buffer_size = chip->rmh.stat[0]  & MASK_DATA_SIZE;
0804 
0805     mutex_unlock(&chip->msg_lock);
0806     return err;
0807 }
0808 
0809 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
0810              u32 buffer_index)
0811 {
0812     int err;
0813     u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
0814 
0815     mutex_lock(&chip->msg_lock);
0816     lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
0817 
0818     chip->rmh.cmd[0] |= pipe_cmd;
0819     chip->rmh.cmd[0] |= buffer_index;
0820 
0821     err = lx_message_send_atomic(chip, &chip->rmh);
0822 
0823     mutex_unlock(&chip->msg_lock);
0824     return err;
0825 }
0826 
0827 
0828 /* low-level gain/peak handling
0829  *
0830  * \todo: can we unmute capture/playback channels independently?
0831  *
0832  * */
0833 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
0834 {
0835     int err;
0836     /* bit set to 1: channel muted */
0837     u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
0838 
0839     mutex_lock(&chip->msg_lock);
0840     lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
0841 
0842     chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
0843 
0844     chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32);        /* hi part */
0845     chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
0846 
0847     dev_dbg(chip->card->dev,
0848         "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
0849            chip->rmh.cmd[2]);
0850 
0851     err = lx_message_send_atomic(chip, &chip->rmh);
0852 
0853     mutex_unlock(&chip->msg_lock);
0854     return err;
0855 }
0856 
0857 static const u32 peak_map[] = {
0858     0x00000109, /* -90.308dB */
0859     0x0000083B, /* -72.247dB */
0860     0x000020C4, /* -60.205dB */
0861     0x00008273, /* -48.030dB */
0862     0x00020756, /* -36.005dB */
0863     0x00040C37, /* -30.001dB */
0864     0x00081385, /* -24.002dB */
0865     0x00101D3F, /* -18.000dB */
0866     0x0016C310, /* -15.000dB */
0867     0x002026F2, /* -12.001dB */
0868     0x002D6A86, /* -9.000dB */
0869     0x004026E6, /* -6.004dB */
0870     0x005A9DF6, /* -3.000dB */
0871     0x0065AC8B, /* -2.000dB */
0872     0x00721481, /* -1.000dB */
0873     0x007FFFFF, /* FS */
0874 };
0875 
0876 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
0877            u32 *r_levels)
0878 {
0879     int err = 0;
0880     int i;
0881 
0882     mutex_lock(&chip->msg_lock);
0883     for (i = 0; i < channels; i += 4) {
0884         u32 s0, s1, s2, s3;
0885 
0886         lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
0887         chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
0888 
0889         err = lx_message_send_atomic(chip, &chip->rmh);
0890 
0891         if (err == 0) {
0892             s0 = peak_map[chip->rmh.stat[0] & 0x0F];
0893             s1 = peak_map[(chip->rmh.stat[0] >>  4) & 0xf];
0894             s2 = peak_map[(chip->rmh.stat[0] >>  8) & 0xf];
0895             s3 = peak_map[(chip->rmh.stat[0] >>  12) & 0xf];
0896         } else
0897             s0 = s1 = s2 = s3 = 0;
0898 
0899         r_levels[0] = s0;
0900         r_levels[1] = s1;
0901         r_levels[2] = s2;
0902         r_levels[3] = s3;
0903 
0904         r_levels += 4;
0905     }
0906 
0907     mutex_unlock(&chip->msg_lock);
0908     return err;
0909 }
0910 
0911 /* interrupt handling */
0912 #define PCX_IRQ_NONE 0
0913 #define IRQCS_ACTIVE_PCIDB  BIT(13)
0914 #define IRQCS_ENABLE_PCIIRQ BIT(8)
0915 #define IRQCS_ENABLE_PCIDB  BIT(9)
0916 
0917 static u32 lx_interrupt_test_ack(struct lx6464es *chip)
0918 {
0919     u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
0920 
0921     /* Test if PCI Doorbell interrupt is active */
0922     if (irqcs & IRQCS_ACTIVE_PCIDB) {
0923         u32 temp;
0924         irqcs = PCX_IRQ_NONE;
0925 
0926         while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
0927             /* RAZ interrupt */
0928             irqcs |= temp;
0929             lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
0930         }
0931 
0932         return irqcs;
0933     }
0934     return PCX_IRQ_NONE;
0935 }
0936 
0937 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
0938                 int *r_async_pending, int *r_async_escmd)
0939 {
0940     u32 irq_async;
0941     u32 irqsrc = lx_interrupt_test_ack(chip);
0942 
0943     if (irqsrc == PCX_IRQ_NONE)
0944         return 0;
0945 
0946     *r_irqsrc = irqsrc;
0947 
0948     irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
0949                              * (set by xilinx) + EOB */
0950 
0951     if (irq_async & MASK_SYS_STATUS_ESA) {
0952         irq_async &= ~MASK_SYS_STATUS_ESA;
0953         *r_async_escmd = 1;
0954     }
0955 
0956     if (irq_async) {
0957         /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */
0958         *r_async_pending = 1;
0959     }
0960 
0961     return 1;
0962 }
0963 
0964 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
0965                         int *r_freq_changed,
0966                         u64 *r_notified_in_pipe_mask,
0967                         u64 *r_notified_out_pipe_mask)
0968 {
0969     int err;
0970     u32 stat[9];        /* answer from CMD_04_GET_EVENT */
0971 
0972     /* We can optimize this to not read dumb events.
0973      * Answer words are in the following order:
0974      * Stat[0]  general status
0975      * Stat[1]  end of buffer OUT pF
0976      * Stat[2]  end of buffer OUT pf
0977      * Stat[3]  end of buffer IN pF
0978      * Stat[4]  end of buffer IN pf
0979      * Stat[5]  MSB underrun
0980      * Stat[6]  LSB underrun
0981      * Stat[7]  MSB overrun
0982      * Stat[8]  LSB overrun
0983      * */
0984 
0985     int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
0986     int eb_pending_in  = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
0987 
0988     *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
0989 
0990     err = lx_dsp_read_async_events(chip, stat);
0991     if (err < 0)
0992         return err;
0993 
0994     if (eb_pending_in) {
0995         *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
0996             + stat[4];
0997         dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n",
0998                 *r_notified_in_pipe_mask);
0999     }
1000     if (eb_pending_out) {
1001         *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1002             + stat[2];
1003         dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n",
1004                 *r_notified_out_pipe_mask);
1005     }
1006 
1007     /* todo: handle xrun notification */
1008 
1009     return err;
1010 }
1011 
1012 static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1013                        struct lx_stream *lx_stream)
1014 {
1015     struct snd_pcm_substream *substream = lx_stream->stream;
1016     const unsigned int is_capture = lx_stream->is_capture;
1017     int err;
1018 
1019     const u32 channels = substream->runtime->channels;
1020     const u32 bytes_per_frame = channels * 3;
1021     const u32 period_size = substream->runtime->period_size;
1022     const u32 period_bytes = period_size * bytes_per_frame;
1023     const u32 pos = lx_stream->frame_pos;
1024     const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1025         0 : pos + 1;
1026 
1027     dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1028     u32 buf_hi = 0;
1029     u32 buf_lo = 0;
1030     u32 buffer_index = 0;
1031 
1032     u32 needed, freed;
1033     u32 size_array[MAX_STREAM_BUFFER];
1034 
1035     dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n");
1036 
1037     mutex_lock(&chip->lock);
1038 
1039     err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1040     dev_dbg(chip->card->dev,
1041         "interrupt: needed %d, freed %d\n", needed, freed);
1042 
1043     unpack_pointer(buf, &buf_lo, &buf_hi);
1044     err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1045                  &buffer_index);
1046     dev_dbg(chip->card->dev,
1047         "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n",
1048             buffer_index, (unsigned long)buf, period_bytes);
1049 
1050     lx_stream->frame_pos = next_pos;
1051     mutex_unlock(&chip->lock);
1052 
1053     return err;
1054 }
1055 
1056 irqreturn_t lx_interrupt(int irq, void *dev_id)
1057 {
1058     struct lx6464es *chip = dev_id;
1059     int async_pending, async_escmd;
1060     u32 irqsrc;
1061     bool wake_thread = false;
1062 
1063     dev_dbg(chip->card->dev,
1064         "**************************************************\n");
1065 
1066     if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1067         dev_dbg(chip->card->dev, "IRQ_NONE\n");
1068         return IRQ_NONE; /* this device did not cause the interrupt */
1069     }
1070 
1071     if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1072         return IRQ_HANDLED;
1073 
1074     if (irqsrc & MASK_SYS_STATUS_EOBI)
1075         dev_dbg(chip->card->dev, "interrupt: EOBI\n");
1076 
1077     if (irqsrc & MASK_SYS_STATUS_EOBO)
1078         dev_dbg(chip->card->dev, "interrupt: EOBO\n");
1079 
1080     if (irqsrc & MASK_SYS_STATUS_URUN)
1081         dev_dbg(chip->card->dev, "interrupt: URUN\n");
1082 
1083     if (irqsrc & MASK_SYS_STATUS_ORUN)
1084         dev_dbg(chip->card->dev, "interrupt: ORUN\n");
1085 
1086     if (async_pending) {
1087         wake_thread = true;
1088         chip->irqsrc = irqsrc;
1089     }
1090 
1091     if (async_escmd) {
1092         /* backdoor for ethersound commands
1093          *
1094          * for now, we do not need this
1095          *
1096          * */
1097 
1098         dev_dbg(chip->card->dev, "interrupt requests escmd handling\n");
1099     }
1100 
1101     return wake_thread ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1102 }
1103 
1104 irqreturn_t lx_threaded_irq(int irq, void *dev_id)
1105 {
1106     struct lx6464es *chip = dev_id;
1107     u64 notified_in_pipe_mask = 0;
1108     u64 notified_out_pipe_mask = 0;
1109     int freq_changed;
1110     int err;
1111 
1112     /* handle async events */
1113     err = lx_interrupt_handle_async_events(chip, chip->irqsrc,
1114                            &freq_changed,
1115                            &notified_in_pipe_mask,
1116                            &notified_out_pipe_mask);
1117     if (err)
1118         dev_err(chip->card->dev, "error handling async events\n");
1119 
1120     if (notified_in_pipe_mask) {
1121         struct lx_stream *lx_stream = &chip->capture_stream;
1122 
1123         dev_dbg(chip->card->dev,
1124             "requesting audio transfer for capture\n");
1125         err = lx_interrupt_request_new_buffer(chip, lx_stream);
1126         if (err < 0)
1127             dev_err(chip->card->dev,
1128                 "cannot request new buffer for capture\n");
1129         snd_pcm_period_elapsed(lx_stream->stream);
1130     }
1131 
1132     if (notified_out_pipe_mask) {
1133         struct lx_stream *lx_stream = &chip->playback_stream;
1134 
1135         dev_dbg(chip->card->dev,
1136             "requesting audio transfer for playback\n");
1137         err = lx_interrupt_request_new_buffer(chip, lx_stream);
1138         if (err < 0)
1139             dev_err(chip->card->dev,
1140                 "cannot request new buffer for playback\n");
1141         snd_pcm_period_elapsed(lx_stream->stream);
1142     }
1143 
1144     return IRQ_HANDLED;
1145 }
1146 
1147 
1148 static void lx_irq_set(struct lx6464es *chip, int enable)
1149 {
1150     u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1151 
1152     /* enable/disable interrupts
1153      *
1154      * Set the Doorbell and PCI interrupt enable bits
1155      *
1156      * */
1157     if (enable)
1158         reg |=  (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1159     else
1160         reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1161     lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1162 }
1163 
1164 void lx_irq_enable(struct lx6464es *chip)
1165 {
1166     dev_dbg(chip->card->dev, "->lx_irq_enable\n");
1167     lx_irq_set(chip, 1);
1168 }
1169 
1170 void lx_irq_disable(struct lx6464es *chip)
1171 {
1172     dev_dbg(chip->card->dev, "->lx_irq_disable\n");
1173     lx_irq_set(chip, 0);
1174 }
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