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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *   ALSA modem driver for Intel ICH (i8x0) chipsets
0004  *
0005  *  Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
0006  *
0007  *   This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
0008  *   of ALSA ICH sound driver intel8x0.c .
0009  */      
0010 
0011 #include <linux/io.h>
0012 #include <linux/delay.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/init.h>
0015 #include <linux/pci.h>
0016 #include <linux/slab.h>
0017 #include <linux/module.h>
0018 #include <sound/core.h>
0019 #include <sound/pcm.h>
0020 #include <sound/ac97_codec.h>
0021 #include <sound/info.h>
0022 #include <sound/initval.h>
0023 
0024 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
0025 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
0026            "SiS 7013; NVidia MCP/2/2S/3 modems");
0027 MODULE_LICENSE("GPL");
0028 
0029 static int index = -2; /* Exclude the first card */
0030 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
0031 static int ac97_clock;
0032 
0033 module_param(index, int, 0444);
0034 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
0035 module_param(id, charp, 0444);
0036 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
0037 module_param(ac97_clock, int, 0444);
0038 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
0039 
0040 /* just for backward compatibility */
0041 static bool enable;
0042 module_param(enable, bool, 0444);
0043 
0044 /*
0045  *  Direct registers
0046  */
0047 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
0048 
0049 #define ICHREG(x) ICH_REG_##x
0050 
0051 #define DEFINE_REGSET(name,base) \
0052 enum { \
0053     ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
0054     ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
0055     ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
0056     ICH_REG_##name##_SR = base + 0x06,  /* byte - status register */ \
0057     ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
0058     ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
0059     ICH_REG_##name##_CR = base + 0x0b,  /* byte - control register */ \
0060 }
0061 
0062 /* busmaster blocks */
0063 DEFINE_REGSET(OFF, 0);      /* offset */
0064 
0065 /* values for each busmaster block */
0066 
0067 /* LVI */
0068 #define ICH_REG_LVI_MASK        0x1f
0069 
0070 /* SR */
0071 #define ICH_FIFOE           0x10    /* FIFO error */
0072 #define ICH_BCIS            0x08    /* buffer completion interrupt status */
0073 #define ICH_LVBCI           0x04    /* last valid buffer completion interrupt */
0074 #define ICH_CELV            0x02    /* current equals last valid */
0075 #define ICH_DCH             0x01    /* DMA controller halted */
0076 
0077 /* PIV */
0078 #define ICH_REG_PIV_MASK        0x1f    /* mask */
0079 
0080 /* CR */
0081 #define ICH_IOCE            0x10    /* interrupt on completion enable */
0082 #define ICH_FEIE            0x08    /* fifo error interrupt enable */
0083 #define ICH_LVBIE           0x04    /* last valid buffer interrupt enable */
0084 #define ICH_RESETREGS           0x02    /* reset busmaster registers */
0085 #define ICH_STARTBM         0x01    /* start busmaster operation */
0086 
0087 
0088 /* global block */
0089 #define ICH_REG_GLOB_CNT        0x3c    /* dword - global control */
0090 #define   ICH_TRIE      0x00000040  /* tertiary resume interrupt enable */
0091 #define   ICH_SRIE      0x00000020  /* secondary resume interrupt enable */
0092 #define   ICH_PRIE      0x00000010  /* primary resume interrupt enable */
0093 #define   ICH_ACLINK        0x00000008  /* AClink shut off */
0094 #define   ICH_AC97WARM      0x00000004  /* AC'97 warm reset */
0095 #define   ICH_AC97COLD      0x00000002  /* AC'97 cold reset */
0096 #define   ICH_GIE       0x00000001  /* GPI interrupt enable */
0097 #define ICH_REG_GLOB_STA        0x40    /* dword - global status */
0098 #define   ICH_TRI       0x20000000  /* ICH4: tertiary (AC_SDIN2) resume interrupt */
0099 #define   ICH_TCR       0x10000000  /* ICH4: tertiary (AC_SDIN2) codec ready */
0100 #define   ICH_BCS       0x08000000  /* ICH4: bit clock stopped */
0101 #define   ICH_SPINT     0x04000000  /* ICH4: S/PDIF interrupt */
0102 #define   ICH_P2INT     0x02000000  /* ICH4: PCM2-In interrupt */
0103 #define   ICH_M2INT     0x01000000  /* ICH4: Mic2-In interrupt */
0104 #define   ICH_SAMPLE_CAP    0x00c00000  /* ICH4: sample capability bits (RO) */
0105 #define   ICH_MULTICHAN_CAP 0x00300000  /* ICH4: multi-channel capability bits (RO) */
0106 #define   ICH_MD3       0x00020000  /* modem power down semaphore */
0107 #define   ICH_AD3       0x00010000  /* audio power down semaphore */
0108 #define   ICH_RCS       0x00008000  /* read completion status */
0109 #define   ICH_BIT3      0x00004000  /* bit 3 slot 12 */
0110 #define   ICH_BIT2      0x00002000  /* bit 2 slot 12 */
0111 #define   ICH_BIT1      0x00001000  /* bit 1 slot 12 */
0112 #define   ICH_SRI       0x00000800  /* secondary (AC_SDIN1) resume interrupt */
0113 #define   ICH_PRI       0x00000400  /* primary (AC_SDIN0) resume interrupt */
0114 #define   ICH_SCR       0x00000200  /* secondary (AC_SDIN1) codec ready */
0115 #define   ICH_PCR       0x00000100  /* primary (AC_SDIN0) codec ready */
0116 #define   ICH_MCINT     0x00000080  /* MIC capture interrupt */
0117 #define   ICH_POINT     0x00000040  /* playback interrupt */
0118 #define   ICH_PIINT     0x00000020  /* capture interrupt */
0119 #define   ICH_NVSPINT       0x00000010  /* nforce spdif interrupt */
0120 #define   ICH_MOINT     0x00000004  /* modem playback interrupt */
0121 #define   ICH_MIINT     0x00000002  /* modem capture interrupt */
0122 #define   ICH_GSCI      0x00000001  /* GPI status change interrupt */
0123 #define ICH_REG_ACC_SEMA        0x44    /* byte - codec write semaphore */
0124 #define   ICH_CAS       0x01        /* codec access semaphore */
0125 
0126 #define ICH_MAX_FRAGS       32      /* max hw frags */
0127 
0128 
0129 /*
0130  *  
0131  */
0132 
0133 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
0134 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
0135 
0136 #define get_ichdev(substream) (substream->runtime->private_data)
0137 
0138 struct ichdev {
0139     unsigned int ichd;          /* ich device number */
0140     unsigned long reg_offset;       /* offset to bmaddr */
0141     __le32 *bdbar;              /* CPU address (32bit) */
0142     unsigned int bdbar_addr;        /* PCI bus address (32bit) */
0143     struct snd_pcm_substream *substream;
0144     unsigned int physbuf;           /* physical address (32bit) */
0145         unsigned int size;
0146         unsigned int fragsize;
0147         unsigned int fragsize1;
0148         unsigned int position;
0149         int frags;
0150         int lvi;
0151         int lvi_frag;
0152     int civ;
0153     int ack;
0154     int ack_reload;
0155     unsigned int ack_bit;
0156     unsigned int roff_sr;
0157     unsigned int roff_picb;
0158     unsigned int int_sta_mask;      /* interrupt status mask */
0159     unsigned int ali_slot;          /* ALI DMA slot */
0160     struct snd_ac97 *ac97;
0161 };
0162 
0163 struct intel8x0m {
0164     unsigned int device_type;
0165 
0166     int irq;
0167 
0168     void __iomem *addr;
0169     void __iomem *bmaddr;
0170 
0171     struct pci_dev *pci;
0172     struct snd_card *card;
0173 
0174     int pcm_devs;
0175     struct snd_pcm *pcm[2];
0176     struct ichdev ichd[2];
0177 
0178     unsigned int in_ac97_init: 1;
0179 
0180     struct snd_ac97_bus *ac97_bus;
0181     struct snd_ac97 *ac97;
0182 
0183     spinlock_t reg_lock;
0184     
0185     struct snd_dma_buffer *bdbars;
0186     u32 bdbars_count;
0187     u32 int_sta_reg;        /* interrupt status register */
0188     u32 int_sta_mask;       /* interrupt status mask */
0189     unsigned int pcm_pos_shift;
0190 };
0191 
0192 static const struct pci_device_id snd_intel8x0m_ids[] = {
0193     { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL },   /* 82801AA */
0194     { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL },   /* 82901AB */
0195     { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL },   /* 82801BA */
0196     { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL },   /* ICH3 */
0197     { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */
0198     { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */
0199     { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL },   /* ICH6 */
0200     { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL },   /* ICH7 */
0201     { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL },   /* 440MX */
0202     { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */
0203     { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS },    /* SI7013 */
0204     { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */
0205     { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */
0206     { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */
0207     { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */
0208     { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */
0209 #if 0
0210     { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
0211 #endif
0212     { 0, }
0213 };
0214 
0215 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
0216 
0217 /*
0218  *  Lowlevel I/O - busmaster
0219  */
0220 
0221 static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
0222 {
0223     return ioread8(chip->bmaddr + offset);
0224 }
0225 
0226 static inline u16 igetword(struct intel8x0m *chip, u32 offset)
0227 {
0228     return ioread16(chip->bmaddr + offset);
0229 }
0230 
0231 static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
0232 {
0233     return ioread32(chip->bmaddr + offset);
0234 }
0235 
0236 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
0237 {
0238     iowrite8(val, chip->bmaddr + offset);
0239 }
0240 
0241 static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
0242 {
0243     iowrite16(val, chip->bmaddr + offset);
0244 }
0245 
0246 static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
0247 {
0248     iowrite32(val, chip->bmaddr + offset);
0249 }
0250 
0251 /*
0252  *  Lowlevel I/O - AC'97 registers
0253  */
0254 
0255 static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
0256 {
0257     return ioread16(chip->addr + offset);
0258 }
0259 
0260 static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
0261 {
0262     iowrite16(val, chip->addr + offset);
0263 }
0264 
0265 /*
0266  *  Basic I/O
0267  */
0268 
0269 /*
0270  * access to AC97 codec via normal i/o (for ICH and SIS7013)
0271  */
0272 
0273 /* return the GLOB_STA bit for the corresponding codec */
0274 static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
0275 {
0276     static const unsigned int codec_bit[3] = {
0277         ICH_PCR, ICH_SCR, ICH_TCR
0278     };
0279     if (snd_BUG_ON(codec >= 3))
0280         return ICH_PCR;
0281     return codec_bit[codec];
0282 }
0283 
0284 static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
0285 {
0286     int time;
0287     
0288     if (codec > 1)
0289         return -EIO;
0290     codec = get_ich_codec_bit(chip, codec);
0291 
0292     /* codec ready ? */
0293     if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
0294         return -EIO;
0295 
0296     /* Anyone holding a semaphore for 1 msec should be shot... */
0297     time = 100;
0298         do {
0299             if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
0300                 return 0;
0301         udelay(10);
0302     } while (time--);
0303 
0304     /* access to some forbidden (non existent) ac97 registers will not
0305      * reset the semaphore. So even if you don't get the semaphore, still
0306      * continue the access. We don't need the semaphore anyway. */
0307     dev_err(chip->card->dev,
0308         "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
0309             igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
0310     iagetword(chip, 0); /* clear semaphore flag */
0311     /* I don't care about the semaphore */
0312     return -EBUSY;
0313 }
0314  
0315 static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,
0316                       unsigned short reg,
0317                       unsigned short val)
0318 {
0319     struct intel8x0m *chip = ac97->private_data;
0320     
0321     if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
0322         if (! chip->in_ac97_init)
0323             dev_err(chip->card->dev,
0324                 "codec_write %d: semaphore is not ready for register 0x%x\n",
0325                 ac97->num, reg);
0326     }
0327     iaputword(chip, reg + ac97->num * 0x80, val);
0328 }
0329 
0330 static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,
0331                            unsigned short reg)
0332 {
0333     struct intel8x0m *chip = ac97->private_data;
0334     unsigned short res;
0335     unsigned int tmp;
0336 
0337     if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
0338         if (! chip->in_ac97_init)
0339             dev_err(chip->card->dev,
0340                 "codec_read %d: semaphore is not ready for register 0x%x\n",
0341                 ac97->num, reg);
0342         res = 0xffff;
0343     } else {
0344         res = iagetword(chip, reg + ac97->num * 0x80);
0345         tmp = igetdword(chip, ICHREG(GLOB_STA));
0346         if (tmp & ICH_RCS) {
0347             /* reset RCS and preserve other R/WC bits */
0348             iputdword(chip, ICHREG(GLOB_STA),
0349                   tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
0350             if (! chip->in_ac97_init)
0351                 dev_err(chip->card->dev,
0352                     "codec_read %d: read timeout for register 0x%x\n",
0353                     ac97->num, reg);
0354             res = 0xffff;
0355         }
0356     }
0357     if (reg == AC97_GPIO_STATUS)
0358         iagetword(chip, 0); /* clear semaphore */
0359     return res;
0360 }
0361 
0362 
0363 /*
0364  * DMA I/O
0365  */
0366 static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
0367 {
0368     int idx;
0369     __le32 *bdbar = ichdev->bdbar;
0370     unsigned long port = ichdev->reg_offset;
0371 
0372     iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
0373     if (ichdev->size == ichdev->fragsize) {
0374         ichdev->ack_reload = ichdev->ack = 2;
0375         ichdev->fragsize1 = ichdev->fragsize >> 1;
0376         for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
0377             bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
0378             bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
0379                              ichdev->fragsize1 >> chip->pcm_pos_shift);
0380             bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
0381             bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
0382                              ichdev->fragsize1 >> chip->pcm_pos_shift);
0383         }
0384         ichdev->frags = 2;
0385     } else {
0386         ichdev->ack_reload = ichdev->ack = 1;
0387         ichdev->fragsize1 = ichdev->fragsize;
0388         for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
0389             bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
0390             bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
0391                              ichdev->fragsize >> chip->pcm_pos_shift);
0392             /*
0393             dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
0394                    idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
0395             */
0396         }
0397         ichdev->frags = ichdev->size / ichdev->fragsize;
0398     }
0399     iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
0400     ichdev->civ = 0;
0401     iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
0402     ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
0403     ichdev->position = 0;
0404 #if 0
0405     dev_dbg(chip->card->dev,
0406         "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
0407            ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
0408            ichdev->fragsize1);
0409 #endif
0410     /* clear interrupts */
0411     iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
0412 }
0413 
0414 /*
0415  *  Interrupt handler
0416  */
0417 
0418 static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)
0419 {
0420     unsigned long port = ichdev->reg_offset;
0421     int civ, i, step;
0422     int ack = 0;
0423 
0424     civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
0425     if (civ == ichdev->civ) {
0426         // snd_printd("civ same %d\n", civ);
0427         step = 1;
0428         ichdev->civ++;
0429         ichdev->civ &= ICH_REG_LVI_MASK;
0430     } else {
0431         step = civ - ichdev->civ;
0432         if (step < 0)
0433             step += ICH_REG_LVI_MASK + 1;
0434         // if (step != 1)
0435         //  snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
0436         ichdev->civ = civ;
0437     }
0438 
0439     ichdev->position += step * ichdev->fragsize1;
0440     ichdev->position %= ichdev->size;
0441     ichdev->lvi += step;
0442     ichdev->lvi &= ICH_REG_LVI_MASK;
0443     iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
0444     for (i = 0; i < step; i++) {
0445         ichdev->lvi_frag++;
0446         ichdev->lvi_frag %= ichdev->frags;
0447         ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
0448                                  ichdev->lvi_frag *
0449                                  ichdev->fragsize1);
0450 #if 0
0451         dev_dbg(chip->card->dev,
0452             "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
0453                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
0454                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
0455                inl(port + 4), inb(port + ICH_REG_OFF_CR));
0456 #endif
0457         if (--ichdev->ack == 0) {
0458             ichdev->ack = ichdev->ack_reload;
0459             ack = 1;
0460         }
0461     }
0462     if (ack && ichdev->substream) {
0463         spin_unlock(&chip->reg_lock);
0464         snd_pcm_period_elapsed(ichdev->substream);
0465         spin_lock(&chip->reg_lock);
0466     }
0467     iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
0468 }
0469 
0470 static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)
0471 {
0472     struct intel8x0m *chip = dev_id;
0473     struct ichdev *ichdev;
0474     unsigned int status;
0475     unsigned int i;
0476 
0477     spin_lock(&chip->reg_lock);
0478     status = igetdword(chip, chip->int_sta_reg);
0479     if (status == 0xffffffff) { /* we are not yet resumed */
0480         spin_unlock(&chip->reg_lock);
0481         return IRQ_NONE;
0482     }
0483     if ((status & chip->int_sta_mask) == 0) {
0484         if (status)
0485             iputdword(chip, chip->int_sta_reg, status);
0486         spin_unlock(&chip->reg_lock);
0487         return IRQ_NONE;
0488     }
0489 
0490     for (i = 0; i < chip->bdbars_count; i++) {
0491         ichdev = &chip->ichd[i];
0492         if (status & ichdev->int_sta_mask)
0493             snd_intel8x0m_update(chip, ichdev);
0494     }
0495 
0496     /* ack them */
0497     iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
0498     spin_unlock(&chip->reg_lock);
0499     
0500     return IRQ_HANDLED;
0501 }
0502 
0503 /*
0504  *  PCM part
0505  */
0506 
0507 static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
0508 {
0509     struct intel8x0m *chip = snd_pcm_substream_chip(substream);
0510     struct ichdev *ichdev = get_ichdev(substream);
0511     unsigned char val = 0;
0512     unsigned long port = ichdev->reg_offset;
0513 
0514     switch (cmd) {
0515     case SNDRV_PCM_TRIGGER_START:
0516     case SNDRV_PCM_TRIGGER_RESUME:
0517         val = ICH_IOCE | ICH_STARTBM;
0518         break;
0519     case SNDRV_PCM_TRIGGER_STOP:
0520     case SNDRV_PCM_TRIGGER_SUSPEND:
0521         val = 0;
0522         break;
0523     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0524         val = ICH_IOCE;
0525         break;
0526     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0527         val = ICH_IOCE | ICH_STARTBM;
0528         break;
0529     default:
0530         return -EINVAL;
0531     }
0532     iputbyte(chip, port + ICH_REG_OFF_CR, val);
0533     if (cmd == SNDRV_PCM_TRIGGER_STOP) {
0534         /* wait until DMA stopped */
0535         while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
0536         /* reset whole DMA things */
0537         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
0538     }
0539     return 0;
0540 }
0541 
0542 static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)
0543 {
0544     struct intel8x0m *chip = snd_pcm_substream_chip(substream);
0545     struct ichdev *ichdev = get_ichdev(substream);
0546     size_t ptr1, ptr;
0547 
0548     ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
0549     if (ptr1 != 0)
0550         ptr = ichdev->fragsize1 - ptr1;
0551     else
0552         ptr = 0;
0553     ptr += ichdev->position;
0554     if (ptr >= ichdev->size)
0555         return 0;
0556     return bytes_to_frames(substream->runtime, ptr);
0557 }
0558 
0559 static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
0560 {
0561     struct intel8x0m *chip = snd_pcm_substream_chip(substream);
0562     struct snd_pcm_runtime *runtime = substream->runtime;
0563     struct ichdev *ichdev = get_ichdev(substream);
0564 
0565     ichdev->physbuf = runtime->dma_addr;
0566     ichdev->size = snd_pcm_lib_buffer_bytes(substream);
0567     ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
0568     snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
0569     snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
0570     snd_intel8x0m_setup_periods(chip, ichdev);
0571     return 0;
0572 }
0573 
0574 static const struct snd_pcm_hardware snd_intel8x0m_stream =
0575 {
0576     .info =         (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
0577                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
0578                  SNDRV_PCM_INFO_MMAP_VALID |
0579                  SNDRV_PCM_INFO_PAUSE |
0580                  SNDRV_PCM_INFO_RESUME),
0581     .formats =      SNDRV_PCM_FMTBIT_S16_LE,
0582     .rates =        SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
0583     .rate_min =     8000,
0584     .rate_max =     16000,
0585     .channels_min =     1,
0586     .channels_max =     1,
0587     .buffer_bytes_max = 64 * 1024,
0588     .period_bytes_min = 32,
0589     .period_bytes_max = 64 * 1024,
0590     .periods_min =      1,
0591     .periods_max =      1024,
0592     .fifo_size =        0,
0593 };
0594 
0595 
0596 static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
0597 {
0598     static const unsigned int rates[] = { 8000,  9600, 12000, 16000 };
0599     static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
0600         .count = ARRAY_SIZE(rates),
0601         .list = rates,
0602         .mask = 0,
0603     };
0604     struct snd_pcm_runtime *runtime = substream->runtime;
0605     int err;
0606 
0607     ichdev->substream = substream;
0608     runtime->hw = snd_intel8x0m_stream;
0609     err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
0610                      &hw_constraints_rates);
0611     if ( err < 0 )
0612         return err;
0613     runtime->private_data = ichdev;
0614     return 0;
0615 }
0616 
0617 static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
0618 {
0619     struct intel8x0m *chip = snd_pcm_substream_chip(substream);
0620 
0621     return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
0622 }
0623 
0624 static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
0625 {
0626     struct intel8x0m *chip = snd_pcm_substream_chip(substream);
0627 
0628     chip->ichd[ICHD_MDMOUT].substream = NULL;
0629     return 0;
0630 }
0631 
0632 static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
0633 {
0634     struct intel8x0m *chip = snd_pcm_substream_chip(substream);
0635 
0636     return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
0637 }
0638 
0639 static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
0640 {
0641     struct intel8x0m *chip = snd_pcm_substream_chip(substream);
0642 
0643     chip->ichd[ICHD_MDMIN].substream = NULL;
0644     return 0;
0645 }
0646 
0647 
0648 static const struct snd_pcm_ops snd_intel8x0m_playback_ops = {
0649     .open =     snd_intel8x0m_playback_open,
0650     .close =    snd_intel8x0m_playback_close,
0651     .prepare =  snd_intel8x0m_pcm_prepare,
0652     .trigger =  snd_intel8x0m_pcm_trigger,
0653     .pointer =  snd_intel8x0m_pcm_pointer,
0654 };
0655 
0656 static const struct snd_pcm_ops snd_intel8x0m_capture_ops = {
0657     .open =     snd_intel8x0m_capture_open,
0658     .close =    snd_intel8x0m_capture_close,
0659     .prepare =  snd_intel8x0m_pcm_prepare,
0660     .trigger =  snd_intel8x0m_pcm_trigger,
0661     .pointer =  snd_intel8x0m_pcm_pointer,
0662 };
0663 
0664 
0665 struct ich_pcm_table {
0666     char *suffix;
0667     const struct snd_pcm_ops *playback_ops;
0668     const struct snd_pcm_ops *capture_ops;
0669     size_t prealloc_size;
0670     size_t prealloc_max_size;
0671     int ac97_idx;
0672 };
0673 
0674 static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,
0675                   const struct ich_pcm_table *rec)
0676 {
0677     struct snd_pcm *pcm;
0678     int err;
0679     char name[32];
0680 
0681     if (rec->suffix)
0682         sprintf(name, "Intel ICH - %s", rec->suffix);
0683     else
0684         strcpy(name, "Intel ICH");
0685     err = snd_pcm_new(chip->card, name, device,
0686               rec->playback_ops ? 1 : 0,
0687               rec->capture_ops ? 1 : 0, &pcm);
0688     if (err < 0)
0689         return err;
0690 
0691     if (rec->playback_ops)
0692         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
0693     if (rec->capture_ops)
0694         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
0695 
0696     pcm->private_data = chip;
0697     pcm->info_flags = 0;
0698     pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
0699     if (rec->suffix)
0700         sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
0701     else
0702         strcpy(pcm->name, chip->card->shortname);
0703     chip->pcm[device] = pcm;
0704 
0705     snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
0706                        &chip->pci->dev,
0707                        rec->prealloc_size,
0708                        rec->prealloc_max_size);
0709 
0710     return 0;
0711 }
0712 
0713 static const struct ich_pcm_table intel_pcms[] = {
0714     {
0715         .suffix = "Modem",
0716         .playback_ops = &snd_intel8x0m_playback_ops,
0717         .capture_ops = &snd_intel8x0m_capture_ops,
0718         .prealloc_size = 32 * 1024,
0719         .prealloc_max_size = 64 * 1024,
0720     },
0721 };
0722 
0723 static int snd_intel8x0m_pcm(struct intel8x0m *chip)
0724 {
0725     int i, tblsize, device, err;
0726     const struct ich_pcm_table *tbl, *rec;
0727 
0728 #if 1
0729     tbl = intel_pcms;
0730     tblsize = 1;
0731 #else
0732     switch (chip->device_type) {
0733     case DEVICE_NFORCE:
0734         tbl = nforce_pcms;
0735         tblsize = ARRAY_SIZE(nforce_pcms);
0736         break;
0737     case DEVICE_ALI:
0738         tbl = ali_pcms;
0739         tblsize = ARRAY_SIZE(ali_pcms);
0740         break;
0741     default:
0742         tbl = intel_pcms;
0743         tblsize = 2;
0744         break;
0745     }
0746 #endif
0747     device = 0;
0748     for (i = 0; i < tblsize; i++) {
0749         rec = tbl + i;
0750         if (i > 0 && rec->ac97_idx) {
0751             /* activate PCM only when associated AC'97 codec */
0752             if (! chip->ichd[rec->ac97_idx].ac97)
0753                 continue;
0754         }
0755         err = snd_intel8x0m_pcm1(chip, device, rec);
0756         if (err < 0)
0757             return err;
0758         device++;
0759     }
0760 
0761     chip->pcm_devs = device;
0762     return 0;
0763 }
0764     
0765 
0766 /*
0767  *  Mixer part
0768  */
0769 
0770 static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
0771 {
0772     struct intel8x0m *chip = bus->private_data;
0773     chip->ac97_bus = NULL;
0774 }
0775 
0776 static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)
0777 {
0778     struct intel8x0m *chip = ac97->private_data;
0779     chip->ac97 = NULL;
0780 }
0781 
0782 
0783 static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)
0784 {
0785     struct snd_ac97_bus *pbus;
0786     struct snd_ac97_template ac97;
0787     struct snd_ac97 *x97;
0788     int err;
0789     unsigned int glob_sta = 0;
0790     static const struct snd_ac97_bus_ops ops = {
0791         .write = snd_intel8x0m_codec_write,
0792         .read = snd_intel8x0m_codec_read,
0793     };
0794 
0795     chip->in_ac97_init = 1;
0796     
0797     memset(&ac97, 0, sizeof(ac97));
0798     ac97.private_data = chip;
0799     ac97.private_free = snd_intel8x0m_mixer_free_ac97;
0800     ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
0801 
0802     glob_sta = igetdword(chip, ICHREG(GLOB_STA));
0803 
0804     err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
0805     if (err < 0)
0806         goto __err;
0807     pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;
0808     if (ac97_clock >= 8000 && ac97_clock <= 48000)
0809         pbus->clock = ac97_clock;
0810     chip->ac97_bus = pbus;
0811 
0812     ac97.pci = chip->pci;
0813     ac97.num = glob_sta & ICH_SCR ? 1 : 0;
0814     err = snd_ac97_mixer(pbus, &ac97, &x97);
0815     if (err < 0) {
0816         dev_err(chip->card->dev,
0817             "Unable to initialize codec #%d\n", ac97.num);
0818         if (ac97.num == 0)
0819             goto __err;
0820         return err;
0821     }
0822     chip->ac97 = x97;
0823     if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
0824         chip->ichd[ICHD_MDMIN].ac97 = x97;
0825         chip->ichd[ICHD_MDMOUT].ac97 = x97;
0826     }
0827 
0828     chip->in_ac97_init = 0;
0829     return 0;
0830 
0831  __err:
0832     /* clear the cold-reset bit for the next chance */
0833     if (chip->device_type != DEVICE_ALI)
0834         iputdword(chip, ICHREG(GLOB_CNT),
0835               igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
0836     return err;
0837 }
0838 
0839 
0840 /*
0841  *
0842  */
0843 
0844 static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
0845 {
0846     unsigned long end_time;
0847     unsigned int cnt, status, nstatus;
0848     
0849     /* put logic to right state */
0850     /* first clear status bits */
0851     status = ICH_RCS | ICH_MIINT | ICH_MOINT;
0852     cnt = igetdword(chip, ICHREG(GLOB_STA));
0853     iputdword(chip, ICHREG(GLOB_STA), cnt & status);
0854 
0855     /* ACLink on, 2 channels */
0856     cnt = igetdword(chip, ICHREG(GLOB_CNT));
0857     cnt &= ~(ICH_ACLINK);
0858     /* finish cold or do warm reset */
0859     cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
0860     iputdword(chip, ICHREG(GLOB_CNT), cnt);
0861     usleep_range(500, 1000); /* give warm reset some time */
0862     end_time = jiffies + HZ / 4;
0863     do {
0864         if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
0865             goto __ok;
0866         schedule_timeout_uninterruptible(1);
0867     } while (time_after_eq(end_time, jiffies));
0868     dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
0869            igetdword(chip, ICHREG(GLOB_CNT)));
0870     return -EIO;
0871 
0872       __ok:
0873     if (probing) {
0874         /* wait for any codec ready status.
0875          * Once it becomes ready it should remain ready
0876          * as long as we do not disable the ac97 link.
0877          */
0878         end_time = jiffies + HZ;
0879         do {
0880             status = igetdword(chip, ICHREG(GLOB_STA)) &
0881                 (ICH_PCR | ICH_SCR | ICH_TCR);
0882             if (status)
0883                 break;
0884             schedule_timeout_uninterruptible(1);
0885         } while (time_after_eq(end_time, jiffies));
0886         if (! status) {
0887             /* no codec is found */
0888             dev_err(chip->card->dev,
0889                 "codec_ready: codec is not ready [0x%x]\n",
0890                    igetdword(chip, ICHREG(GLOB_STA)));
0891             return -EIO;
0892         }
0893 
0894         /* up to two codecs (modem cannot be tertiary with ICH4) */
0895         nstatus = ICH_PCR | ICH_SCR;
0896 
0897         /* wait for other codecs ready status. */
0898         end_time = jiffies + HZ / 4;
0899         while (status != nstatus && time_after_eq(end_time, jiffies)) {
0900             schedule_timeout_uninterruptible(1);
0901             status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
0902         }
0903 
0904     } else {
0905         /* resume phase */
0906         status = 0;
0907         if (chip->ac97)
0908             status |= get_ich_codec_bit(chip, chip->ac97->num);
0909         /* wait until all the probed codecs are ready */
0910         end_time = jiffies + HZ;
0911         do {
0912             nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
0913                 (ICH_PCR | ICH_SCR | ICH_TCR);
0914             if (status == nstatus)
0915                 break;
0916             schedule_timeout_uninterruptible(1);
0917         } while (time_after_eq(end_time, jiffies));
0918     }
0919 
0920     if (chip->device_type == DEVICE_SIS) {
0921         /* unmute the output on SIS7012 */
0922         iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
0923     }
0924 
0925         return 0;
0926 }
0927 
0928 static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)
0929 {
0930     unsigned int i;
0931     int err;
0932     
0933     err = snd_intel8x0m_ich_chip_init(chip, probing);
0934     if (err < 0)
0935         return err;
0936     iagetword(chip, 0); /* clear semaphore flag */
0937 
0938     /* disable interrupts */
0939     for (i = 0; i < chip->bdbars_count; i++)
0940         iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
0941     /* reset channels */
0942     for (i = 0; i < chip->bdbars_count; i++)
0943         iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
0944     /* initialize Buffer Descriptor Lists */
0945     for (i = 0; i < chip->bdbars_count; i++)
0946         iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
0947     return 0;
0948 }
0949 
0950 static void snd_intel8x0m_free(struct snd_card *card)
0951 {
0952     struct intel8x0m *chip = card->private_data;
0953     unsigned int i;
0954 
0955     if (chip->irq < 0)
0956         goto __hw_end;
0957     /* disable interrupts */
0958     for (i = 0; i < chip->bdbars_count; i++)
0959         iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
0960     /* reset channels */
0961     for (i = 0; i < chip->bdbars_count; i++)
0962         iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
0963  __hw_end:
0964     if (chip->irq >= 0)
0965         free_irq(chip->irq, chip);
0966 }
0967 
0968 #ifdef CONFIG_PM_SLEEP
0969 /*
0970  * power management
0971  */
0972 static int intel8x0m_suspend(struct device *dev)
0973 {
0974     struct snd_card *card = dev_get_drvdata(dev);
0975     struct intel8x0m *chip = card->private_data;
0976 
0977     snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
0978     snd_ac97_suspend(chip->ac97);
0979     if (chip->irq >= 0) {
0980         free_irq(chip->irq, chip);
0981         chip->irq = -1;
0982         card->sync_irq = -1;
0983     }
0984     return 0;
0985 }
0986 
0987 static int intel8x0m_resume(struct device *dev)
0988 {
0989     struct pci_dev *pci = to_pci_dev(dev);
0990     struct snd_card *card = dev_get_drvdata(dev);
0991     struct intel8x0m *chip = card->private_data;
0992 
0993     if (request_irq(pci->irq, snd_intel8x0m_interrupt,
0994             IRQF_SHARED, KBUILD_MODNAME, chip)) {
0995         dev_err(dev, "unable to grab IRQ %d, disabling device\n",
0996             pci->irq);
0997         snd_card_disconnect(card);
0998         return -EIO;
0999     }
1000     chip->irq = pci->irq;
1001     card->sync_irq = chip->irq;
1002     snd_intel8x0m_chip_init(chip, 0);
1003     snd_ac97_resume(chip->ac97);
1004 
1005     snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1006     return 0;
1007 }
1008 
1009 static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);
1010 #define INTEL8X0M_PM_OPS    &intel8x0m_pm
1011 #else
1012 #define INTEL8X0M_PM_OPS    NULL
1013 #endif /* CONFIG_PM_SLEEP */
1014 
1015 static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1016                    struct snd_info_buffer *buffer)
1017 {
1018     struct intel8x0m *chip = entry->private_data;
1019     unsigned int tmp;
1020 
1021     snd_iprintf(buffer, "Intel8x0m\n\n");
1022     if (chip->device_type == DEVICE_ALI)
1023         return;
1024     tmp = igetdword(chip, ICHREG(GLOB_STA));
1025     snd_iprintf(buffer, "Global control        : 0x%08x\n",
1026             igetdword(chip, ICHREG(GLOB_CNT)));
1027     snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
1028     snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
1029             tmp & ICH_PCR ? " primary" : "",
1030             tmp & ICH_SCR ? " secondary" : "",
1031             tmp & ICH_TCR ? " tertiary" : "",
1032             (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1033 }
1034 
1035 static void snd_intel8x0m_proc_init(struct intel8x0m *chip)
1036 {
1037     snd_card_ro_proc_new(chip->card, "intel8x0m", chip,
1038                  snd_intel8x0m_proc_read);
1039 }
1040 
1041 struct ich_reg_info {
1042     unsigned int int_sta_mask;
1043     unsigned int offset;
1044 };
1045 
1046 static int snd_intel8x0m_init(struct snd_card *card,
1047                   struct pci_dev *pci,
1048                   unsigned long device_type)
1049 {
1050     struct intel8x0m *chip = card->private_data;
1051     int err;
1052     unsigned int i;
1053     unsigned int int_sta_masks;
1054     struct ichdev *ichdev;
1055     static const struct ich_reg_info intel_regs[2] = {
1056         { ICH_MIINT, 0 },
1057         { ICH_MOINT, 0x10 },
1058     };
1059     const struct ich_reg_info *tbl;
1060 
1061     err = pcim_enable_device(pci);
1062     if (err < 0)
1063         return err;
1064 
1065     spin_lock_init(&chip->reg_lock);
1066     chip->device_type = device_type;
1067     chip->card = card;
1068     chip->pci = pci;
1069     chip->irq = -1;
1070 
1071     err = pci_request_regions(pci, card->shortname);
1072     if (err < 0)
1073         return err;
1074 
1075     if (device_type == DEVICE_ALI) {
1076         /* ALI5455 has no ac97 region */
1077         chip->bmaddr = pcim_iomap(pci, 0, 0);
1078     } else {
1079         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
1080             chip->addr = pcim_iomap(pci, 2, 0);
1081         else
1082             chip->addr = pcim_iomap(pci, 0, 0);
1083         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
1084             chip->bmaddr = pcim_iomap(pci, 3, 0);
1085         else
1086             chip->bmaddr = pcim_iomap(pci, 1, 0);
1087     }
1088 
1089     /* initialize offsets */
1090     chip->bdbars_count = 2;
1091     tbl = intel_regs;
1092 
1093     for (i = 0; i < chip->bdbars_count; i++) {
1094         ichdev = &chip->ichd[i];
1095         ichdev->ichd = i;
1096         ichdev->reg_offset = tbl[i].offset;
1097         ichdev->int_sta_mask = tbl[i].int_sta_mask;
1098         if (device_type == DEVICE_SIS) {
1099             /* SiS 7013 swaps the registers */
1100             ichdev->roff_sr = ICH_REG_OFF_PICB;
1101             ichdev->roff_picb = ICH_REG_OFF_SR;
1102         } else {
1103             ichdev->roff_sr = ICH_REG_OFF_SR;
1104             ichdev->roff_picb = ICH_REG_OFF_PICB;
1105         }
1106         if (device_type == DEVICE_ALI)
1107             ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1108     }
1109     /* SIS7013 handles the pcm data in bytes, others are in words */
1110     chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1111 
1112     /* allocate buffer descriptor lists */
1113     /* the start of each lists must be aligned to 8 bytes */
1114     chip->bdbars = snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV,
1115                         chip->bdbars_count * sizeof(u32) *
1116                         ICH_MAX_FRAGS * 2);
1117     if (!chip->bdbars)
1118         return -ENOMEM;
1119 
1120     /* tables must be aligned to 8 bytes here, but the kernel pages
1121        are much bigger, so we don't care (on i386) */
1122     int_sta_masks = 0;
1123     for (i = 0; i < chip->bdbars_count; i++) {
1124         ichdev = &chip->ichd[i];
1125         ichdev->bdbar = ((__le32 *)chip->bdbars->area) + (i * ICH_MAX_FRAGS * 2);
1126         ichdev->bdbar_addr = chip->bdbars->addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1127         int_sta_masks |= ichdev->int_sta_mask;
1128     }
1129     chip->int_sta_reg = ICH_REG_GLOB_STA;
1130     chip->int_sta_mask = int_sta_masks;
1131 
1132     pci_set_master(pci);
1133 
1134     err = snd_intel8x0m_chip_init(chip, 1);
1135     if (err < 0)
1136         return err;
1137 
1138     /* NOTE: we don't use devm version here since it's released /
1139      * re-acquired in PM callbacks.
1140      * It's released explicitly in snd_intel8x0m_free(), too.
1141      */
1142     if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED,
1143             KBUILD_MODNAME, chip)) {
1144         dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1145         return -EBUSY;
1146     }
1147     chip->irq = pci->irq;
1148     card->sync_irq = chip->irq;
1149 
1150     card->private_free = snd_intel8x0m_free;
1151 
1152     return 0;
1153 }
1154 
1155 static struct shortname_table {
1156     unsigned int id;
1157     const char *s;
1158 } shortnames[] = {
1159     { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1160     { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1161     { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1162     { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1163     { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1164     { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1165     { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1166     { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1167     { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1168     { 0x7446, "AMD AMD768" },
1169     { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1170     { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1171     { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1172     { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1173     { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1174     { 0x746e, "AMD AMD8111" },
1175 #if 0
1176     { 0x5455, "ALi M5455" },
1177 #endif
1178     { 0 },
1179 };
1180 
1181 static int __snd_intel8x0m_probe(struct pci_dev *pci,
1182                  const struct pci_device_id *pci_id)
1183 {
1184     struct snd_card *card;
1185     struct intel8x0m *chip;
1186     int err;
1187     struct shortname_table *name;
1188 
1189     err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
1190                 sizeof(*chip), &card);
1191     if (err < 0)
1192         return err;
1193     chip = card->private_data;
1194 
1195     strcpy(card->driver, "ICH-MODEM");
1196     strcpy(card->shortname, "Intel ICH");
1197     for (name = shortnames; name->id; name++) {
1198         if (pci->device == name->id) {
1199             strcpy(card->shortname, name->s);
1200             break;
1201         }
1202     }
1203     strcat(card->shortname," Modem");
1204 
1205     err = snd_intel8x0m_init(card, pci, pci_id->driver_data);
1206     if (err < 0)
1207         return err;
1208 
1209     err = snd_intel8x0m_mixer(chip, ac97_clock);
1210     if (err < 0)
1211         return err;
1212     err = snd_intel8x0m_pcm(chip);
1213     if (err < 0)
1214         return err;
1215     
1216     snd_intel8x0m_proc_init(chip);
1217 
1218     sprintf(card->longname, "%s at irq %i",
1219         card->shortname, chip->irq);
1220 
1221     err = snd_card_register(card);
1222     if (err < 0)
1223         return err;
1224     pci_set_drvdata(pci, card);
1225     return 0;
1226 }
1227 
1228 static int snd_intel8x0m_probe(struct pci_dev *pci,
1229                    const struct pci_device_id *pci_id)
1230 {
1231     return snd_card_free_on_error(&pci->dev, __snd_intel8x0m_probe(pci, pci_id));
1232 }
1233 
1234 static struct pci_driver intel8x0m_driver = {
1235     .name = KBUILD_MODNAME,
1236     .id_table = snd_intel8x0m_ids,
1237     .probe = snd_intel8x0m_probe,
1238     .driver = {
1239         .pm = INTEL8X0M_PM_OPS,
1240     },
1241 };
1242 
1243 module_pci_driver(intel8x0m_driver);
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