pci/ice1712/wm8766.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_WM8766_H
0003 #define __SOUND_WM8766_H
0004
0005 /*
0006  *   ALSA driver for ICEnsemble VT17xx
0007  *
0008  *   Lowlevel functions for WM8766 codec
0009  *
0010  *  Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
0011  */
0012
0013 #define WM8766_REG_DACL1    0x00
0014 #define WM8766_REG_DACR1    0x01
0015 #define WM8766_VOL_MASK         0x1ff       /* incl. update bit */
0016 #define WM8766_VOL_UPDATE       (1 << 8)    /* update volume */
0017 #define WM8766_REG_DACCTRL1 0x02
0018 #define WM8766_DAC_MUTEALL      (1 << 0)
0019 #define WM8766_DAC_DEEMPALL     (1 << 1)
0020 #define WM8766_DAC_PDWN         (1 << 2)
0021 #define WM8766_DAC_ATC          (1 << 3)
0022 #define WM8766_DAC_IZD          (1 << 4)
0023 #define WM8766_DAC_PL_MASK      0x1e0
0024 #define WM8766_DAC_PL_LL        (1 << 5)    /* L chan: L signal */
0025 #define WM8766_DAC_PL_LR        (2 << 5)    /* L chan: R signal */
0026 #define WM8766_DAC_PL_LB        (3 << 5)    /* L chan: both */
0027 #define WM8766_DAC_PL_RL        (1 << 7)    /* R chan: L signal */
0028 #define WM8766_DAC_PL_RR        (2 << 7)    /* R chan: R signal */
0029 #define WM8766_DAC_PL_RB        (3 << 7)    /* R chan: both */
0030 #define WM8766_REG_IFCTRL   0x03
0031 #define WM8766_IF_FMT_RIGHTJ        (0 << 0)
0032 #define WM8766_IF_FMT_LEFTJ     (1 << 0)
0033 #define WM8766_IF_FMT_I2S       (2 << 0)
0034 #define WM8766_IF_FMT_DSP       (3 << 0)
0035 #define WM8766_IF_DSP_LATE      (1 << 2)    /* in DSP mode */
0036 #define WM8766_IF_LRC_INVERTED      (1 << 2)    /* in other modes */
0037 #define WM8766_IF_BCLK_INVERTED     (1 << 3)
0038 #define WM8766_IF_IWL_16BIT     (0 << 4)
0039 #define WM8766_IF_IWL_20BIT     (1 << 4)
0040 #define WM8766_IF_IWL_24BIT     (2 << 4)
0041 #define WM8766_IF_IWL_32BIT     (3 << 4)
0042 #define WM8766_IF_MASK          0x3f
0043 #define WM8766_PHASE_INVERT1        (1 << 6)
0044 #define WM8766_PHASE_INVERT2        (1 << 7)
0045 #define WM8766_PHASE_INVERT3        (1 << 8)
0046 #define WM8766_REG_DACL2    0x04
0047 #define WM8766_REG_DACR2    0x05
0048 #define WM8766_REG_DACL3    0x06
0049 #define WM8766_REG_DACR3    0x07
0050 #define WM8766_REG_MASTDA   0x08
0051 #define WM8766_REG_DACCTRL2 0x09
0052 #define WM8766_DAC2_ZCD         (1 << 0)
0053 #define WM8766_DAC2_ZFLAG_ALL       (0 << 1)
0054 #define WM8766_DAC2_ZFLAG_1     (1 << 1)
0055 #define WM8766_DAC2_ZFLAG_2     (2 << 1)
0056 #define WM8766_DAC2_ZFLAG_3     (3 << 1)
0057 #define WM8766_DAC2_MUTE1       (1 << 3)
0058 #define WM8766_DAC2_MUTE2       (1 << 4)
0059 #define WM8766_DAC2_MUTE3       (1 << 5)
0060 #define WM8766_DAC2_DEEMP1      (1 << 6)
0061 #define WM8766_DAC2_DEEMP2      (1 << 7)
0062 #define WM8766_DAC2_DEEMP3      (1 << 8)
0063 #define WM8766_REG_DACCTRL3 0x0a
0064 #define WM8766_DAC3_DACPD1      (1 << 1)
0065 #define WM8766_DAC3_DACPD2      (1 << 2)
0066 #define WM8766_DAC3_DACPD3      (1 << 3)
0067 #define WM8766_DAC3_PWRDNALL        (1 << 4)
0068 #define WM8766_DAC3_POWER_MASK      0x1e
0069 #define WM8766_DAC3_MASTER      (1 << 5)
0070 #define WM8766_DAC3_DAC128FS        (0 << 6)
0071 #define WM8766_DAC3_DAC192FS        (1 << 6)
0072 #define WM8766_DAC3_DAC256FS        (2 << 6)
0073 #define WM8766_DAC3_DAC384FS        (3 << 6)
0074 #define WM8766_DAC3_DAC512FS        (4 << 6)
0075 #define WM8766_DAC3_DAC768FS        (5 << 6)
0076 #define WM8766_DAC3_MSTR_MASK       0x1e0
0077 #define WM8766_REG_MUTE1    0x0c
0078 #define WM8766_MUTE1_MPD        (1 << 6)
0079 #define WM8766_REG_MUTE2    0x0f
0080 #define WM8766_MUTE2_MPD        (1 << 5)
0081 #define WM8766_REG_RESET    0x1f
0082
0083 #define WM8766_REG_COUNT    0x10    /* don't cache the RESET register */
0084
0085 struct snd_wm8766;
0086
0087 struct snd_wm8766_ops {
0088     void (*write)(struct snd_wm8766 *wm, u16 addr, u16 data);
0089 };
0090
0091 enum snd_wm8766_ctl_id {
0092     WM8766_CTL_CH1_VOL,
0093     WM8766_CTL_CH2_VOL,
0094     WM8766_CTL_CH3_VOL,
0095     WM8766_CTL_CH1_SW,
0096     WM8766_CTL_CH2_SW,
0097     WM8766_CTL_CH3_SW,
0098     WM8766_CTL_PHASE1_SW,
0099     WM8766_CTL_PHASE2_SW,
0100     WM8766_CTL_PHASE3_SW,
0101     WM8766_CTL_DEEMPH1_SW,
0102     WM8766_CTL_DEEMPH2_SW,
0103     WM8766_CTL_DEEMPH3_SW,
0104     WM8766_CTL_IZD_SW,
0105     WM8766_CTL_ZC_SW,
0106
0107     WM8766_CTL_COUNT,
0108 };
0109
0110 #define WM8766_ENUM_MAX     16
0111
0112 #define WM8766_FLAG_STEREO  (1 << 0)
0113 #define WM8766_FLAG_VOL_UPDATE  (1 << 1)
0114 #define WM8766_FLAG_INVERT  (1 << 2)
0115 #define WM8766_FLAG_LIM     (1 << 3)
0116 #define WM8766_FLAG_ALC     (1 << 4)
0117
0118 struct snd_wm8766_ctl {
0119     struct snd_kcontrol *kctl;
0120     const char *name;
0121     snd_ctl_elem_type_t type;
0122     const char *const enum_names[WM8766_ENUM_MAX];
0123     const unsigned int *tlv;
0124     u16 reg1, reg2, mask1, mask2, min, max, flags;
0125     void (*set)(struct snd_wm8766 *wm, u16 ch1, u16 ch2);
0126     void (*get)(struct snd_wm8766 *wm, u16 *ch1, u16 *ch2);
0127 };
0128
0129 enum snd_wm8766_agc_mode { WM8766_AGC_OFF, WM8766_AGC_LIM, WM8766_AGC_ALC };
0130
0131 struct snd_wm8766 {
0132     struct snd_card *card;
0133     struct snd_wm8766_ctl ctl[WM8766_CTL_COUNT];
0134     enum snd_wm8766_agc_mode agc_mode;
0135     struct snd_wm8766_ops ops;
0136     u16 regs[WM8766_REG_COUNT]; /* 9-bit registers */
0137 };
0138
0139
0140
0141 void snd_wm8766_init(struct snd_wm8766 *wm);
0142 void snd_wm8766_resume(struct snd_wm8766 *wm);
0143 void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac);
0144 void snd_wm8766_volume_restore(struct snd_wm8766 *wm);
0145 int snd_wm8766_build_controls(struct snd_wm8766 *wm);
0146
0147 #endif /* __SOUND_WM8766_H */