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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *   ALSA driver for ICEnsemble VT1724 (Envy24HT)
0004  *
0005  *   Lowlevel functions for Infrasonic Quartet
0006  *
0007  *  Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/init.h>
0013 #include <linux/slab.h>
0014 #include <linux/string.h>
0015 #include <sound/core.h>
0016 #include <sound/tlv.h>
0017 #include <sound/info.h>
0018 
0019 #include "ice1712.h"
0020 #include "envy24ht.h"
0021 #include <sound/ak4113.h>
0022 #include "quartet.h"
0023 
0024 struct qtet_spec {
0025     struct ak4113 *ak4113;
0026     unsigned int scr;   /* system control register */
0027     unsigned int mcr;   /* monitoring control register */
0028     unsigned int cpld;  /* cpld register */
0029 };
0030 
0031 struct qtet_kcontrol_private {
0032     unsigned int bit;
0033     void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
0034     unsigned int (*get_register)(struct snd_ice1712 *ice);
0035     const char * const texts[2];
0036 };
0037 
0038 enum {
0039     IN12_SEL = 0,
0040     IN34_SEL,
0041     AIN34_SEL,
0042     COAX_OUT,
0043     IN12_MON12,
0044     IN12_MON34,
0045     IN34_MON12,
0046     IN34_MON34,
0047     OUT12_MON34,
0048     OUT34_MON12,
0049 };
0050 
0051 static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
0052     "Word Clock 256xFS"};
0053 
0054 /* chip address on I2C bus */
0055 #define AK4113_ADDR     0x26    /* S/PDIF receiver */
0056 
0057 /* chip address on SPI bus */
0058 #define AK4620_ADDR     0x02    /* ADC/DAC */
0059 
0060 
0061 /*
0062  * GPIO pins
0063  */
0064 
0065 /* GPIO0 - O - DATA0, def. 0 */
0066 #define GPIO_D0         (1<<0)
0067 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
0068 #define GPIO_D1_JACKDTC0    (1<<1)
0069 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
0070 #define GPIO_D2_JACKDTC1    (1<<2)
0071 /* GPIO3 - I/O - DATA3, def. 1 */
0072 #define GPIO_D3         (1<<3)
0073 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
0074 #define GPIO_D4_SPI_CDTO    (1<<4)
0075 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
0076 #define GPIO_D5_SPI_CCLK    (1<<5)
0077 /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
0078 #define GPIO_D6_CD      (1<<6)
0079 /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
0080 #define GPIO_D7_DD      (1<<7)
0081 /* GPIO8 - O - CPLD Chip Select, def. 1 */
0082 #define GPIO_CPLD_CSN       (1<<8)
0083 /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
0084 #define GPIO_CPLD_RW        (1<<9)
0085 /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
0086 #define GPIO_SPI_CSN0       (1<<10)
0087 /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
0088 #define GPIO_SPI_CSN1       (1<<11)
0089 /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
0090  * init 0 */
0091 #define GPIO_EX_GPIOE       (1<<12)
0092 /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
0093  * def. 1 */
0094 #define GPIO_SCR        (1<<13)
0095 /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
0096  * def. 1 */
0097 #define GPIO_MCR        (1<<14)
0098 
0099 #define GPIO_SPI_ALL        (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
0100         GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
0101 
0102 #define GPIO_DATA_MASK      (GPIO_D0 | GPIO_D1_JACKDTC0 | \
0103         GPIO_D2_JACKDTC1 | GPIO_D3 | \
0104         GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
0105         GPIO_D6_CD | GPIO_D7_DD)
0106 
0107 /* System Control Register GPIO_SCR data bits */
0108 /* Mic/Line select relay (0:line, 1:mic) */
0109 #define SCR_RELAY       GPIO_D0
0110 /* Phantom power drive control (0:5V, 1:48V) */
0111 #define SCR_PHP_V       GPIO_D1_JACKDTC0
0112 /* H/W mute control (0:Normal, 1:Mute) */
0113 #define SCR_MUTE        GPIO_D2_JACKDTC1
0114 /* Phantom power control (0:Phantom on, 1:off) */
0115 #define SCR_PHP         GPIO_D3
0116 /* Analog input 1/2 Source Select */
0117 #define SCR_AIN12_SEL0      GPIO_D4_SPI_CDTO
0118 #define SCR_AIN12_SEL1      GPIO_D5_SPI_CCLK
0119 /* Analog input 3/4 Source Select (0:line, 1:hi-z) */
0120 #define SCR_AIN34_SEL       GPIO_D6_CD
0121 /* Codec Power Down (0:power down, 1:normal) */
0122 #define SCR_CODEC_PDN       GPIO_D7_DD
0123 
0124 #define SCR_AIN12_LINE      (0)
0125 #define SCR_AIN12_MIC       (SCR_AIN12_SEL0)
0126 #define SCR_AIN12_LOWCUT    (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
0127 
0128 /* Monitor Control Register GPIO_MCR data bits */
0129 /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
0130 #define MCR_IN12_MON12      GPIO_D0
0131 /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
0132 #define MCR_IN12_MON34      GPIO_D1_JACKDTC0
0133 /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
0134 #define MCR_IN34_MON12      GPIO_D2_JACKDTC1
0135 /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
0136 #define MCR_IN34_MON34      GPIO_D3
0137 /* Output to Monitor 1/2 (0:off, 1:on) */
0138 #define MCR_OUT34_MON12     GPIO_D4_SPI_CDTO
0139 /* Output to Monitor 3/4 (0:off, 1:on) */
0140 #define MCR_OUT12_MON34     GPIO_D5_SPI_CCLK
0141 
0142 /* CPLD Register DATA bits */
0143 /* Clock Rate Select */
0144 #define CPLD_CKS0       GPIO_D0
0145 #define CPLD_CKS1       GPIO_D1_JACKDTC0
0146 #define CPLD_CKS2       GPIO_D2_JACKDTC1
0147 /* Sync Source Select (0:Internal, 1:External) */
0148 #define CPLD_SYNC_SEL       GPIO_D3
0149 /* Word Clock FS Select (0:FS, 1:256FS) */
0150 #define CPLD_WORD_SEL       GPIO_D4_SPI_CDTO
0151 /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
0152 #define CPLD_COAX_OUT       GPIO_D5_SPI_CCLK
0153 /* Input 1/2 Source Select (0:Analog12, 1:An34) */
0154 #define CPLD_IN12_SEL       GPIO_D6_CD
0155 /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
0156 #define CPLD_IN34_SEL       GPIO_D7_DD
0157 
0158 /* internal clock (CPLD_SYNC_SEL = 0) options */
0159 #define CPLD_CKS_44100HZ    (0)
0160 #define CPLD_CKS_48000HZ    (CPLD_CKS0)
0161 #define CPLD_CKS_88200HZ    (CPLD_CKS1)
0162 #define CPLD_CKS_96000HZ    (CPLD_CKS1 | CPLD_CKS0)
0163 #define CPLD_CKS_176400HZ   (CPLD_CKS2)
0164 #define CPLD_CKS_192000HZ   (CPLD_CKS2 | CPLD_CKS0)
0165 
0166 #define CPLD_CKS_MASK       (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
0167 
0168 /* external clock (CPLD_SYNC_SEL = 1) options */
0169 /* external clock - SPDIF */
0170 #define CPLD_EXT_SPDIF  (0 | CPLD_SYNC_SEL)
0171 /* external clock - WordClock 1xfs */
0172 #define CPLD_EXT_WORDCLOCK_1FS  (CPLD_CKS1 | CPLD_SYNC_SEL)
0173 /* external clock - WordClock 256xfs */
0174 #define CPLD_EXT_WORDCLOCK_256FS    (CPLD_CKS1 | CPLD_WORD_SEL |\
0175         CPLD_SYNC_SEL)
0176 
0177 #define EXT_SPDIF_TYPE          0
0178 #define EXT_WORDCLOCK_1FS_TYPE      1
0179 #define EXT_WORDCLOCK_256FS_TYPE    2
0180 
0181 #define AK4620_DFS0     (1<<0)
0182 #define AK4620_DFS1     (1<<1)
0183 #define AK4620_CKS0     (1<<2)
0184 #define AK4620_CKS1     (1<<3)
0185 /* Clock and Format Control register */
0186 #define AK4620_DFS_REG      0x02
0187 
0188 /* Deem and Volume Control register */
0189 #define AK4620_DEEMVOL_REG  0x03
0190 #define AK4620_SMUTE        (1<<7)
0191 
0192 /*
0193  * Conversion from int value to its binary form. Used for debugging.
0194  * The output buffer must be allocated prior to calling the function.
0195  */
0196 static char *get_binary(char *buffer, int value)
0197 {
0198     int i, j, pos;
0199     pos = 0;
0200     for (i = 0; i < 4; ++i) {
0201         for (j = 0; j < 8; ++j) {
0202             if (value & (1 << (31-(i*8 + j))))
0203                 buffer[pos] = '1';
0204             else
0205                 buffer[pos] = '0';
0206             pos++;
0207         }
0208         if (i < 3) {
0209             buffer[pos] = ' ';
0210             pos++;
0211         }
0212     }
0213     buffer[pos] = '\0';
0214     return buffer;
0215 }
0216 
0217 /*
0218  * Initial setup of the conversion array GPIO <-> rate
0219  */
0220 static const unsigned int qtet_rates[] = {
0221     44100, 48000, 88200,
0222     96000, 176400, 192000,
0223 };
0224 
0225 static const unsigned int cks_vals[] = {
0226     CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,
0227     CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,
0228 };
0229 
0230 static const struct snd_pcm_hw_constraint_list qtet_rates_info = {
0231     .count = ARRAY_SIZE(qtet_rates),
0232     .list = qtet_rates,
0233     .mask = 0,
0234 };
0235 
0236 static void qtet_ak4113_write(void *private_data, unsigned char reg,
0237         unsigned char val)
0238 {
0239     snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,
0240             reg, val);
0241 }
0242 
0243 static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)
0244 {
0245     return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
0246             AK4113_ADDR, reg);
0247 }
0248 
0249 
0250 /*
0251  * AK4620 section
0252  */
0253 
0254 /*
0255  * Write data to addr register of ak4620
0256  */
0257 static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,
0258         unsigned char addr, unsigned char data)
0259 {
0260     unsigned int tmp, orig_dir;
0261     int idx;
0262     unsigned int addrdata;
0263     struct snd_ice1712 *ice = ak->private_data[0];
0264 
0265     if (snd_BUG_ON(chip < 0 || chip >= 4))
0266         return;
0267     /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
0268       data=0x%x\n", chip, addr, data);*/
0269     orig_dir = ice->gpio.get_dir(ice);
0270     ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);
0271     /* set mask - only SPI bits */
0272     ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
0273 
0274     tmp = ice->gpio.get_data(ice);
0275     /* high all */
0276     tmp |= GPIO_SPI_ALL;
0277     ice->gpio.set_data(ice, tmp);
0278     udelay(100);
0279     /* drop chip select */
0280     if (chip)
0281         /* CODEC 1 */
0282         tmp &= ~GPIO_SPI_CSN1;
0283     else
0284         tmp &= ~GPIO_SPI_CSN0;
0285     ice->gpio.set_data(ice, tmp);
0286     udelay(100);
0287 
0288     /* build I2C address + data byte */
0289     addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
0290     addrdata = (addrdata << 8) | data;
0291     for (idx = 15; idx >= 0; idx--) {
0292         /* drop clock */
0293         tmp &= ~GPIO_D5_SPI_CCLK;
0294         ice->gpio.set_data(ice, tmp);
0295         udelay(100);
0296         /* set data */
0297         if (addrdata & (1 << idx))
0298             tmp |= GPIO_D4_SPI_CDTO;
0299         else
0300             tmp &= ~GPIO_D4_SPI_CDTO;
0301         ice->gpio.set_data(ice, tmp);
0302         udelay(100);
0303         /* raise clock */
0304         tmp |= GPIO_D5_SPI_CCLK;
0305         ice->gpio.set_data(ice, tmp);
0306         udelay(100);
0307     }
0308     /* all back to 1 */
0309     tmp |= GPIO_SPI_ALL;
0310     ice->gpio.set_data(ice, tmp);
0311     udelay(100);
0312 
0313     /* return all gpios to non-writable */
0314     ice->gpio.set_mask(ice, 0xffffff);
0315     /* restore GPIOs direction */
0316     ice->gpio.set_dir(ice, orig_dir);
0317 }
0318 
0319 static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,
0320         unsigned char mask, unsigned char value)
0321 {
0322     unsigned char tmp;
0323     int chip;
0324     for (chip = 0; chip < ak->num_chips; chip++) {
0325         tmp = snd_akm4xxx_get(ak, chip, addr);
0326         /* clear the bits */
0327         tmp &= ~mask;
0328         /* set the new bits */
0329         tmp |= value;
0330         snd_akm4xxx_write(ak, chip, addr, tmp);
0331     }
0332 }
0333 
0334 /*
0335  * change the rate of AK4620
0336  */
0337 static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
0338 {
0339     unsigned char ak4620_dfs;
0340 
0341     if (rate == 0)  /* no hint - S/PDIF input is master or the new spdif
0342                input rate undetected, simply return */
0343         return;
0344 
0345     /* adjust DFS on codecs - see datasheet */
0346     if (rate > 108000)
0347         ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;
0348     else if (rate > 54000)
0349         ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;
0350     else
0351         ak4620_dfs = 0;
0352 
0353     /* set new value */
0354     qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |
0355             AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);
0356 }
0357 
0358 #define AK_CONTROL(xname, xch)  { .name = xname, .num_channels = xch }
0359 
0360 #define PCM_12_PLAYBACK_VOLUME  "PCM 1/2 Playback Volume"
0361 #define PCM_34_PLAYBACK_VOLUME  "PCM 3/4 Playback Volume"
0362 #define PCM_12_CAPTURE_VOLUME   "PCM 1/2 Capture Volume"
0363 #define PCM_34_CAPTURE_VOLUME   "PCM 3/4 Capture Volume"
0364 
0365 static const struct snd_akm4xxx_dac_channel qtet_dac[] = {
0366     AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),
0367     AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),
0368 };
0369 
0370 static const struct snd_akm4xxx_adc_channel qtet_adc[] = {
0371     AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),
0372     AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),
0373 };
0374 
0375 static const struct snd_akm4xxx akm_qtet_dac = {
0376     .type = SND_AK4620,
0377     .num_dacs = 4,  /* DAC1 - Output 12
0378     */
0379     .num_adcs = 4,  /* ADC1 - Input 12
0380     */
0381     .ops = {
0382         .write = qtet_akm_write,
0383         .set_rate_val = qtet_akm_set_rate_val,
0384     },
0385     .dac_info = qtet_dac,
0386     .adc_info = qtet_adc,
0387 };
0388 
0389 /* Communication routines with the CPLD */
0390 
0391 
0392 /* Writes data to external register reg, both reg and data are
0393  * GPIO representations */
0394 static void reg_write(struct snd_ice1712 *ice, unsigned int reg,
0395         unsigned int data)
0396 {
0397     unsigned int tmp;
0398 
0399     mutex_lock(&ice->gpio_mutex);
0400     /* set direction of used GPIOs*/
0401     /* all outputs */
0402     tmp = 0x00ffff;
0403     ice->gpio.set_dir(ice, tmp);
0404     /* mask - writable bits */
0405     ice->gpio.set_mask(ice, ~(tmp));
0406     /* write the data */
0407     tmp = ice->gpio.get_data(ice);
0408     tmp &= ~GPIO_DATA_MASK;
0409     tmp |= data;
0410     ice->gpio.set_data(ice, tmp);
0411     udelay(100);
0412     /* drop output enable */
0413     tmp &=  ~GPIO_EX_GPIOE;
0414     ice->gpio.set_data(ice, tmp);
0415     udelay(100);
0416     /* drop the register gpio */
0417     tmp &= ~reg;
0418     ice->gpio.set_data(ice, tmp);
0419     udelay(100);
0420     /* raise the register GPIO */
0421     tmp |= reg;
0422     ice->gpio.set_data(ice, tmp);
0423     udelay(100);
0424 
0425     /* raise all data gpios */
0426     tmp |= GPIO_DATA_MASK;
0427     ice->gpio.set_data(ice, tmp);
0428     /* mask - immutable bits */
0429     ice->gpio.set_mask(ice, 0xffffff);
0430     /* outputs only 8-15 */
0431     ice->gpio.set_dir(ice, 0x00ff00);
0432     mutex_unlock(&ice->gpio_mutex);
0433 }
0434 
0435 static unsigned int get_scr(struct snd_ice1712 *ice)
0436 {
0437     struct qtet_spec *spec = ice->spec;
0438     return spec->scr;
0439 }
0440 
0441 static unsigned int get_mcr(struct snd_ice1712 *ice)
0442 {
0443     struct qtet_spec *spec = ice->spec;
0444     return spec->mcr;
0445 }
0446 
0447 static unsigned int get_cpld(struct snd_ice1712 *ice)
0448 {
0449     struct qtet_spec *spec = ice->spec;
0450     return spec->cpld;
0451 }
0452 
0453 static void set_scr(struct snd_ice1712 *ice, unsigned int val)
0454 {
0455     struct qtet_spec *spec = ice->spec;
0456     reg_write(ice, GPIO_SCR, val);
0457     spec->scr = val;
0458 }
0459 
0460 static void set_mcr(struct snd_ice1712 *ice, unsigned int val)
0461 {
0462     struct qtet_spec *spec = ice->spec;
0463     reg_write(ice, GPIO_MCR, val);
0464     spec->mcr = val;
0465 }
0466 
0467 static void set_cpld(struct snd_ice1712 *ice, unsigned int val)
0468 {
0469     struct qtet_spec *spec = ice->spec;
0470     reg_write(ice, GPIO_CPLD_CSN, val);
0471     spec->cpld = val;
0472 }
0473 
0474 static void proc_regs_read(struct snd_info_entry *entry,
0475         struct snd_info_buffer *buffer)
0476 {
0477     struct snd_ice1712 *ice = entry->private_data;
0478     char bin_buffer[36];
0479 
0480     snd_iprintf(buffer, "SCR:   %s\n", get_binary(bin_buffer,
0481                 get_scr(ice)));
0482     snd_iprintf(buffer, "MCR:   %s\n", get_binary(bin_buffer,
0483                 get_mcr(ice)));
0484     snd_iprintf(buffer, "CPLD:  %s\n", get_binary(bin_buffer,
0485                 get_cpld(ice)));
0486 }
0487 
0488 static void proc_init(struct snd_ice1712 *ice)
0489 {
0490     snd_card_ro_proc_new(ice->card, "quartet", ice, proc_regs_read);
0491 }
0492 
0493 static int qtet_mute_get(struct snd_kcontrol *kcontrol,
0494         struct snd_ctl_elem_value *ucontrol)
0495 {
0496     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0497     unsigned int val;
0498     val = get_scr(ice) & SCR_MUTE;
0499     ucontrol->value.integer.value[0] = (val) ? 0 : 1;
0500     return 0;
0501 }
0502 
0503 static int qtet_mute_put(struct snd_kcontrol *kcontrol,
0504         struct snd_ctl_elem_value *ucontrol)
0505 {
0506     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0507     unsigned int old, new, smute;
0508     old = get_scr(ice) & SCR_MUTE;
0509     if (ucontrol->value.integer.value[0]) {
0510         /* unmute */
0511         new = 0;
0512         /* un-smuting DAC */
0513         smute = 0;
0514     } else {
0515         /* mute */
0516         new = SCR_MUTE;
0517         /* smuting DAC */
0518         smute = AK4620_SMUTE;
0519     }
0520     if (old != new) {
0521         struct snd_akm4xxx *ak = ice->akm;
0522         set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);
0523         /* set smute */
0524         qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);
0525         return 1;
0526     }
0527     /* no change */
0528     return 0;
0529 }
0530 
0531 static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,
0532         struct snd_ctl_elem_info *uinfo)
0533 {
0534     static const char * const texts[3] =
0535         {"Line In 1/2", "Mic", "Mic + Low-cut"};
0536     return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(texts), texts);
0537 }
0538 
0539 static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,
0540         struct snd_ctl_elem_value *ucontrol)
0541 {
0542     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0543     unsigned int val, result;
0544     val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
0545     switch (val) {
0546     case SCR_AIN12_LINE:
0547         result = 0;
0548         break;
0549     case SCR_AIN12_MIC:
0550         result = 1;
0551         break;
0552     case SCR_AIN12_LOWCUT:
0553         result = 2;
0554         break;
0555     default:
0556         /* BUG - no other combinations allowed */
0557         snd_BUG();
0558         result = 0;
0559     }
0560     ucontrol->value.integer.value[0] = result;
0561     return 0;
0562 }
0563 
0564 static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,
0565         struct snd_ctl_elem_value *ucontrol)
0566 {
0567     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0568     unsigned int old, new, tmp, masked_old;
0569     old = get_scr(ice);
0570     masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
0571     tmp = ucontrol->value.integer.value[0];
0572     if (tmp == 2)
0573         tmp = 3;    /* binary 10 is not supported */
0574     tmp <<= 4;  /* shifting to SCR_AIN12_SEL0 */
0575     if (tmp != masked_old) {
0576         /* change requested */
0577         switch (tmp) {
0578         case SCR_AIN12_LINE:
0579             new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
0580             set_scr(ice, new);
0581             /* turn off relay */
0582             new &= ~SCR_RELAY;
0583             set_scr(ice, new);
0584             break;
0585         case SCR_AIN12_MIC:
0586             /* turn on relay */
0587             new = old | SCR_RELAY;
0588             set_scr(ice, new);
0589             new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;
0590             set_scr(ice, new);
0591             break;
0592         case SCR_AIN12_LOWCUT:
0593             /* turn on relay */
0594             new = old | SCR_RELAY;
0595             set_scr(ice, new);
0596             new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;
0597             set_scr(ice, new);
0598             break;
0599         default:
0600             snd_BUG();
0601         }
0602         return 1;
0603     }
0604     /* no change */
0605     return 0;
0606 }
0607 
0608 static int qtet_php_get(struct snd_kcontrol *kcontrol,
0609         struct snd_ctl_elem_value *ucontrol)
0610 {
0611     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0612     unsigned int val;
0613     /* if phantom voltage =48V, phantom on */
0614     val = get_scr(ice) & SCR_PHP_V;
0615     ucontrol->value.integer.value[0] = val ? 1 : 0;
0616     return 0;
0617 }
0618 
0619 static int qtet_php_put(struct snd_kcontrol *kcontrol,
0620         struct snd_ctl_elem_value *ucontrol)
0621 {
0622     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0623     unsigned int old, new;
0624     old = new = get_scr(ice);
0625     if (ucontrol->value.integer.value[0] /* phantom on requested */
0626             && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {
0627         /* is off, turn on */
0628         /* turn voltage on first, = 1 */
0629         new = old | SCR_PHP_V;
0630         set_scr(ice, new);
0631         /* turn phantom on, = 0 */
0632         new &= ~SCR_PHP;
0633         set_scr(ice, new);
0634     } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {
0635         /* phantom off requested and 1 = voltage 48V */
0636         /* is on, turn off */
0637         /* turn voltage off first, = 0 */
0638         new = old & ~SCR_PHP_V;
0639         set_scr(ice, new);
0640         /* turn phantom off, = 1 */
0641         new |= SCR_PHP;
0642         set_scr(ice, new);
0643     }
0644     if (old != new)
0645         return 1;
0646     /* no change */
0647     return 0;
0648 }
0649 
0650 #define PRIV_SW(xid, xbit, xreg)    [xid] = {.bit = xbit,\
0651     .set_register = set_##xreg,\
0652     .get_register = get_##xreg, }
0653 
0654 
0655 #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\
0656     .set_register = set_##xreg,\
0657     .get_register = get_##xreg,\
0658     .texts = {xtext1, xtext2} }
0659 
0660 static const struct qtet_kcontrol_private qtet_privates[] = {
0661     PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),
0662     PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),
0663     PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),
0664     PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),
0665     PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),
0666     PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),
0667     PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),
0668     PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),
0669     PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),
0670     PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
0671 };
0672 
0673 static int qtet_enum_info(struct snd_kcontrol *kcontrol,
0674         struct snd_ctl_elem_info *uinfo)
0675 {
0676     struct qtet_kcontrol_private private =
0677         qtet_privates[kcontrol->private_value];
0678     return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(private.texts),
0679                  private.texts);
0680 }
0681 
0682 static int qtet_sw_get(struct snd_kcontrol *kcontrol,
0683         struct snd_ctl_elem_value *ucontrol)
0684 {
0685     struct qtet_kcontrol_private private =
0686         qtet_privates[kcontrol->private_value];
0687     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0688     ucontrol->value.integer.value[0] =
0689         (private.get_register(ice) & private.bit) ? 1 : 0;
0690     return 0;
0691 }
0692 
0693 static int qtet_sw_put(struct snd_kcontrol *kcontrol,
0694         struct snd_ctl_elem_value *ucontrol)
0695 {
0696     struct qtet_kcontrol_private private =
0697         qtet_privates[kcontrol->private_value];
0698     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0699     unsigned int old, new;
0700     old = private.get_register(ice);
0701     if (ucontrol->value.integer.value[0])
0702         new = old | private.bit;
0703     else
0704         new = old & ~private.bit;
0705     if (old != new) {
0706         private.set_register(ice, new);
0707         return 1;
0708     }
0709     /* no change */
0710     return 0;
0711 }
0712 
0713 #define qtet_sw_info    snd_ctl_boolean_mono_info
0714 
0715 #define QTET_CONTROL(xname, xtype, xpriv)   \
0716     {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
0717     .name = xname,\
0718     .info = qtet_##xtype##_info,\
0719     .get = qtet_sw_get,\
0720     .put = qtet_sw_put,\
0721     .private_value = xpriv }
0722 
0723 static const struct snd_kcontrol_new qtet_controls[] = {
0724     {
0725         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0726         .name = "Master Playback Switch",
0727         .info = qtet_sw_info,
0728         .get = qtet_mute_get,
0729         .put = qtet_mute_put,
0730         .private_value = 0
0731     },
0732     {
0733         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0734         .name = "Phantom Power",
0735         .info = qtet_sw_info,
0736         .get = qtet_php_get,
0737         .put = qtet_php_put,
0738         .private_value = 0
0739     },
0740     {
0741         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0742         .name = "Analog In 1/2 Capture Switch",
0743         .info = qtet_ain12_enum_info,
0744         .get = qtet_ain12_sw_get,
0745         .put = qtet_ain12_sw_put,
0746         .private_value = 0
0747     },
0748     QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),
0749     QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),
0750     QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),
0751     QTET_CONTROL("Coax Output Source", enum, COAX_OUT),
0752     QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),
0753     QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),
0754     QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),
0755     QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),
0756     QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),
0757     QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),
0758 };
0759 
0760 static const char * const follower_vols[] = {
0761     PCM_12_PLAYBACK_VOLUME,
0762     PCM_34_PLAYBACK_VOLUME,
0763     NULL
0764 };
0765 
0766 static
0767 DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);
0768 
0769 static struct snd_kcontrol *ctl_find(struct snd_card *card,
0770                      const char *name)
0771 {
0772     struct snd_ctl_elem_id sid = {0};
0773 
0774     strscpy(sid.name, name, sizeof(sid.name));
0775     sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
0776     return snd_ctl_find_id(card, &sid);
0777 }
0778 
0779 static void add_followers(struct snd_card *card,
0780               struct snd_kcontrol *master, const char * const *list)
0781 {
0782     for (; *list; list++) {
0783         struct snd_kcontrol *follower = ctl_find(card, *list);
0784         if (follower)
0785             snd_ctl_add_follower(master, follower);
0786     }
0787 }
0788 
0789 static int qtet_add_controls(struct snd_ice1712 *ice)
0790 {
0791     struct qtet_spec *spec = ice->spec;
0792     int err, i;
0793     struct snd_kcontrol *vmaster;
0794     err = snd_ice1712_akm4xxx_build_controls(ice);
0795     if (err < 0)
0796         return err;
0797     for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {
0798         err = snd_ctl_add(ice->card,
0799                 snd_ctl_new1(&qtet_controls[i], ice));
0800         if (err < 0)
0801             return err;
0802     }
0803 
0804     /* Create virtual master control */
0805     vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
0806             qtet_master_db_scale);
0807     if (!vmaster)
0808         return -ENOMEM;
0809     add_followers(ice->card, vmaster, follower_vols);
0810     err = snd_ctl_add(ice->card, vmaster);
0811     if (err < 0)
0812         return err;
0813     /* only capture SPDIF over AK4113 */
0814     return snd_ak4113_build(spec->ak4113,
0815             ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
0816 }
0817 
0818 static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)
0819 {
0820     /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
0821     return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;
0822 }
0823 
0824 static unsigned int qtet_get_rate(struct snd_ice1712 *ice)
0825 {
0826     int i;
0827     unsigned char result;
0828 
0829     result =  get_cpld(ice) & CPLD_CKS_MASK;
0830     for (i = 0; i < ARRAY_SIZE(cks_vals); i++)
0831         if (cks_vals[i] == result)
0832             return qtet_rates[i];
0833     return 0;
0834 }
0835 
0836 static int get_cks_val(int rate)
0837 {
0838     int i;
0839     for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)
0840         if (qtet_rates[i] == rate)
0841             return cks_vals[i];
0842     return 0;
0843 }
0844 
0845 /* setting new rate */
0846 static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)
0847 {
0848     unsigned int new;
0849     unsigned char val;
0850     /* switching ice1724 to external clock - supplied by ext. circuits */
0851     val = inb(ICEMT1724(ice, RATE));
0852     outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
0853 
0854     new =  (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);
0855     /* switch to internal clock, drop CPLD_SYNC_SEL */
0856     new &= ~CPLD_SYNC_SEL;
0857     /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
0858        get_cpld(ice), new); */
0859     set_cpld(ice, new);
0860 }
0861 
0862 static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,
0863         unsigned int rate)
0864 {
0865     /* no change in master clock */
0866     return 0;
0867 }
0868 
0869 /* setting clock to external - SPDIF */
0870 static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)
0871 {
0872     unsigned int old, new;
0873 
0874     old = new = get_cpld(ice);
0875     new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);
0876     switch (type) {
0877     case EXT_SPDIF_TYPE:
0878         new |= CPLD_EXT_SPDIF;
0879         break;
0880     case EXT_WORDCLOCK_1FS_TYPE:
0881         new |= CPLD_EXT_WORDCLOCK_1FS;
0882         break;
0883     case EXT_WORDCLOCK_256FS_TYPE:
0884         new |= CPLD_EXT_WORDCLOCK_256FS;
0885         break;
0886     default:
0887         snd_BUG();
0888     }
0889     if (old != new) {
0890         set_cpld(ice, new);
0891         /* changed */
0892         return 1;
0893     }
0894     return 0;
0895 }
0896 
0897 static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)
0898 {
0899     unsigned int val;
0900     int result;
0901     val = get_cpld(ice);
0902     /* checking only rate/clock-related bits */
0903     val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);
0904     if (!(val & CPLD_SYNC_SEL)) {
0905         /* switched to internal clock, is not any external type */
0906         result = -1;
0907     } else {
0908         switch (val) {
0909         case (CPLD_EXT_SPDIF):
0910             result = EXT_SPDIF_TYPE;
0911             break;
0912         case (CPLD_EXT_WORDCLOCK_1FS):
0913             result = EXT_WORDCLOCK_1FS_TYPE;
0914             break;
0915         case (CPLD_EXT_WORDCLOCK_256FS):
0916             result = EXT_WORDCLOCK_256FS_TYPE;
0917             break;
0918         default:
0919             /* undefined combination of external clock setup */
0920             snd_BUG();
0921             result = 0;
0922         }
0923     }
0924     return result;
0925 }
0926 
0927 /* Called when ak4113 detects change in the input SPDIF stream */
0928 static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,
0929         unsigned char c1)
0930 {
0931     struct snd_ice1712 *ice = ak4113->change_callback_private;
0932     int rate;
0933     if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&
0934             c1) {
0935         /* only for SPDIF master mode, rate was changed */
0936         rate = snd_ak4113_external_rate(ak4113);
0937         /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
0938            rate); */
0939         qtet_akm_set_rate_val(ice->akm, rate);
0940     }
0941 }
0942 
0943 /*
0944  * If clock slaved to SPDIF-IN, setting runtime rate
0945  * to the detected external rate
0946  */
0947 static void qtet_spdif_in_open(struct snd_ice1712 *ice,
0948         struct snd_pcm_substream *substream)
0949 {
0950     struct qtet_spec *spec = ice->spec;
0951     struct snd_pcm_runtime *runtime = substream->runtime;
0952     int rate;
0953 
0954     if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)
0955         /* not external SPDIF, no rate limitation */
0956         return;
0957     /* only external SPDIF can detect incoming sample rate */
0958     rate = snd_ak4113_external_rate(spec->ak4113);
0959     if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
0960         runtime->hw.rate_min = rate;
0961         runtime->hw.rate_max = rate;
0962     }
0963 }
0964 
0965 /*
0966  * initialize the chip
0967  */
0968 static int qtet_init(struct snd_ice1712 *ice)
0969 {
0970     static const unsigned char ak4113_init_vals[] = {
0971         /* AK4113_REG_PWRDN */  AK4113_RST | AK4113_PWN |
0972             AK4113_OCKS0 | AK4113_OCKS1,
0973         /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |
0974             AK4113_DEM_OFF | AK4113_DEAU,
0975         /* AK4113_REG_IO0 */    AK4113_OPS2 | AK4113_TXE |
0976             AK4113_XTL_24_576M,
0977         /* AK4113_REG_IO1 */    AK4113_EFH_1024LRCLK | AK4113_IPS(0),
0978         /* AK4113_REG_INT0_MASK */  0,
0979         /* AK4113_REG_INT1_MASK */  0,
0980         /* AK4113_REG_DATDTS */     0,
0981     };
0982     int err;
0983     struct qtet_spec *spec;
0984     struct snd_akm4xxx *ak;
0985     unsigned char val;
0986 
0987     /* switching ice1724 to external clock - supplied by ext. circuits */
0988     val = inb(ICEMT1724(ice, RATE));
0989     outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
0990 
0991     spec = kzalloc(sizeof(*spec), GFP_KERNEL);
0992     if (!spec)
0993         return -ENOMEM;
0994     /* qtet is clocked by Xilinx array */
0995     ice->hw_rates = &qtet_rates_info;
0996     ice->is_spdif_master = qtet_is_spdif_master;
0997     ice->get_rate = qtet_get_rate;
0998     ice->set_rate = qtet_set_rate;
0999     ice->set_mclk = qtet_set_mclk;
1000     ice->set_spdif_clock = qtet_set_spdif_clock;
1001     ice->get_spdif_master_type = qtet_get_spdif_master_type;
1002     ice->ext_clock_names = ext_clock_names;
1003     ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
1004     /* since Qtet can detect correct SPDIF-in rate, all streams can be
1005      * limited to this specific rate */
1006     ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;
1007     ice->spec = spec;
1008 
1009     /* Mute Off */
1010     /* SCR Initialize*/
1011     /* keep codec power down first */
1012     set_scr(ice, SCR_PHP);
1013     udelay(1);
1014     /* codec power up */
1015     set_scr(ice, SCR_PHP | SCR_CODEC_PDN);
1016 
1017     /* MCR Initialize */
1018     set_mcr(ice, 0);
1019 
1020     /* CPLD Initialize */
1021     set_cpld(ice, 0);
1022 
1023 
1024     ice->num_total_dacs = 2;
1025     ice->num_total_adcs = 2;
1026 
1027     ice->akm = kcalloc(2, sizeof(struct snd_akm4xxx), GFP_KERNEL);
1028     ak = ice->akm;
1029     if (!ak)
1030         return -ENOMEM;
1031     /* only one codec with two chips */
1032     ice->akm_codecs = 1;
1033     err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);
1034     if (err < 0)
1035         return err;
1036     err = snd_ak4113_create(ice->card,
1037             qtet_ak4113_read,
1038             qtet_ak4113_write,
1039             ak4113_init_vals,
1040             ice, &spec->ak4113);
1041     if (err < 0)
1042         return err;
1043     /* callback for codecs rate setting */
1044     spec->ak4113->change_callback = qtet_ak4113_change;
1045     spec->ak4113->change_callback_private = ice;
1046     /* AK41143 in Quartet can detect external rate correctly
1047      * (i.e. check_flags = 0) */
1048     spec->ak4113->check_flags = 0;
1049 
1050     proc_init(ice);
1051 
1052     qtet_set_rate(ice, 44100);
1053     return 0;
1054 }
1055 
1056 static const unsigned char qtet_eeprom[] = {
1057     [ICE_EEP2_SYSCONF]     = 0x28,  /* clock 256(24MHz), mpu401, 1xADC,
1058                        1xDACs, SPDIF in */
1059     [ICE_EEP2_ACLINK]      = 0x80,  /* I2S */
1060     [ICE_EEP2_I2S]         = 0x78,  /* 96k, 24bit, 192k */
1061     [ICE_EEP2_SPDIF]       = 0xc3,  /* out-en, out-int, in, out-ext */
1062     [ICE_EEP2_GPIO_DIR]    = 0x00,  /* 0-7 inputs, switched to output
1063                        only during output operations */
1064     [ICE_EEP2_GPIO_DIR1]   = 0xff,  /* 8-15 outputs */
1065     [ICE_EEP2_GPIO_DIR2]   = 0x00,
1066     [ICE_EEP2_GPIO_MASK]   = 0xff,  /* changed only for OUT operations */
1067     [ICE_EEP2_GPIO_MASK1]  = 0x00,
1068     [ICE_EEP2_GPIO_MASK2]  = 0xff,
1069 
1070     [ICE_EEP2_GPIO_STATE]  = 0x00, /* inputs */
1071     [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW
1072                       and GPIO15 always zero */
1073     [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
1074 };
1075 
1076 /* entry point */
1077 struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {
1078     {
1079         .subvendor = VT1724_SUBDEVICE_QTET,
1080         .name = "Infrasonic Quartet",
1081         .model = "quartet",
1082         .chip_init = qtet_init,
1083         .build_controls = qtet_add_controls,
1084         .eeprom_size = sizeof(qtet_eeprom),
1085         .eeprom_data = qtet_eeprom,
1086     },
1087     { } /* terminator */
1088 };
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