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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *   ALSA driver for ICEnsemble VT1724 (Envy24HT)
0004  *
0005  *   Lowlevel functions for Pontis MS300
0006  *
0007  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/init.h>
0013 #include <linux/slab.h>
0014 #include <linux/mutex.h>
0015 
0016 #include <sound/core.h>
0017 #include <sound/info.h>
0018 #include <sound/tlv.h>
0019 
0020 #include "ice1712.h"
0021 #include "envy24ht.h"
0022 #include "pontis.h"
0023 
0024 /* I2C addresses */
0025 #define WM_DEV      0x34
0026 #define CS_DEV      0x20
0027 
0028 /* WM8776 registers */
0029 #define WM_HP_ATTEN_L       0x00    /* headphone left attenuation */
0030 #define WM_HP_ATTEN_R       0x01    /* headphone left attenuation */
0031 #define WM_HP_MASTER        0x02    /* headphone master (both channels) */
0032                     /* override LLR */
0033 #define WM_DAC_ATTEN_L      0x03    /* digital left attenuation */
0034 #define WM_DAC_ATTEN_R      0x04
0035 #define WM_DAC_MASTER       0x05
0036 #define WM_PHASE_SWAP       0x06    /* DAC phase swap */
0037 #define WM_DAC_CTRL1        0x07
0038 #define WM_DAC_MUTE     0x08
0039 #define WM_DAC_CTRL2        0x09
0040 #define WM_DAC_INT      0x0a
0041 #define WM_ADC_INT      0x0b
0042 #define WM_MASTER_CTRL      0x0c
0043 #define WM_POWERDOWN        0x0d
0044 #define WM_ADC_ATTEN_L      0x0e
0045 #define WM_ADC_ATTEN_R      0x0f
0046 #define WM_ALC_CTRL1        0x10
0047 #define WM_ALC_CTRL2        0x11
0048 #define WM_ALC_CTRL3        0x12
0049 #define WM_NOISE_GATE       0x13
0050 #define WM_LIMITER      0x14
0051 #define WM_ADC_MUX      0x15
0052 #define WM_OUT_MUX      0x16
0053 #define WM_RESET        0x17
0054 
0055 /*
0056  * GPIO
0057  */
0058 #define PONTIS_CS_CS        (1<<4)  /* CS */
0059 #define PONTIS_CS_CLK       (1<<5)  /* CLK */
0060 #define PONTIS_CS_RDATA     (1<<6)  /* CS8416 -> VT1720 */
0061 #define PONTIS_CS_WDATA     (1<<7)  /* VT1720 -> CS8416 */
0062 
0063 
0064 /*
0065  * get the current register value of WM codec
0066  */
0067 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
0068 {
0069     reg <<= 1;
0070     return ((unsigned short)ice->akm[0].images[reg] << 8) |
0071         ice->akm[0].images[reg + 1];
0072 }
0073 
0074 /*
0075  * set the register value of WM codec and remember it
0076  */
0077 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
0078 {
0079     unsigned short cval;
0080     cval = (reg << 9) | val;
0081     snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
0082 }
0083 
0084 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
0085 {
0086     wm_put_nocache(ice, reg, val);
0087     reg <<= 1;
0088     ice->akm[0].images[reg] = val >> 8;
0089     ice->akm[0].images[reg + 1] = val;
0090 }
0091 
0092 /*
0093  * DAC volume attenuation mixer control (-64dB to 0dB)
0094  */
0095 
0096 #define DAC_0dB 0xff
0097 #define DAC_RES 128
0098 #define DAC_MIN (DAC_0dB - DAC_RES)
0099 
0100 static int wm_dac_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0101 {
0102     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0103     uinfo->count = 2;
0104     uinfo->value.integer.min = 0;   /* mute */
0105     uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
0106     return 0;
0107 }
0108 
0109 static int wm_dac_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0110 {
0111     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0112     unsigned short val;
0113     int i;
0114 
0115     mutex_lock(&ice->gpio_mutex);
0116     for (i = 0; i < 2; i++) {
0117         val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
0118         val = val > DAC_MIN ? (val - DAC_MIN) : 0;
0119         ucontrol->value.integer.value[i] = val;
0120     }
0121     mutex_unlock(&ice->gpio_mutex);
0122     return 0;
0123 }
0124 
0125 static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0126 {
0127     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0128     unsigned short oval, nval;
0129     int i, idx, change = 0;
0130 
0131     mutex_lock(&ice->gpio_mutex);
0132     for (i = 0; i < 2; i++) {
0133         nval = ucontrol->value.integer.value[i];
0134         nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
0135         idx = WM_DAC_ATTEN_L + i;
0136         oval = wm_get(ice, idx) & 0xff;
0137         if (oval != nval) {
0138             wm_put(ice, idx, nval);
0139             wm_put_nocache(ice, idx, nval | 0x100);
0140             change = 1;
0141         }
0142     }
0143     mutex_unlock(&ice->gpio_mutex);
0144     return change;
0145 }
0146 
0147 /*
0148  * ADC gain mixer control (-64dB to 0dB)
0149  */
0150 
0151 #define ADC_0dB 0xcf
0152 #define ADC_RES 128
0153 #define ADC_MIN (ADC_0dB - ADC_RES)
0154 
0155 static int wm_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0156 {
0157     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0158     uinfo->count = 2;
0159     uinfo->value.integer.min = 0;   /* mute (-64dB) */
0160     uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
0161     return 0;
0162 }
0163 
0164 static int wm_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0165 {
0166     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0167     unsigned short val;
0168     int i;
0169 
0170     mutex_lock(&ice->gpio_mutex);
0171     for (i = 0; i < 2; i++) {
0172         val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
0173         val = val > ADC_MIN ? (val - ADC_MIN) : 0;
0174         ucontrol->value.integer.value[i] = val;
0175     }
0176     mutex_unlock(&ice->gpio_mutex);
0177     return 0;
0178 }
0179 
0180 static int wm_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0181 {
0182     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0183     unsigned short ovol, nvol;
0184     int i, idx, change = 0;
0185 
0186     mutex_lock(&ice->gpio_mutex);
0187     for (i = 0; i < 2; i++) {
0188         nvol = ucontrol->value.integer.value[i];
0189         nvol = nvol ? (nvol + ADC_MIN) : 0;
0190         idx  = WM_ADC_ATTEN_L + i;
0191         ovol = wm_get(ice, idx) & 0xff;
0192         if (ovol != nvol) {
0193             wm_put(ice, idx, nvol);
0194             change = 1;
0195         }
0196     }
0197     mutex_unlock(&ice->gpio_mutex);
0198     return change;
0199 }
0200 
0201 /*
0202  * ADC input mux mixer control
0203  */
0204 #define wm_adc_mux_info     snd_ctl_boolean_mono_info
0205 
0206 static int wm_adc_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0207 {
0208     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0209     int bit = kcontrol->private_value;
0210 
0211     mutex_lock(&ice->gpio_mutex);
0212     ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
0213     mutex_unlock(&ice->gpio_mutex);
0214     return 0;
0215 }
0216 
0217 static int wm_adc_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0218 {
0219     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0220     int bit = kcontrol->private_value;
0221     unsigned short oval, nval;
0222     int change;
0223 
0224     mutex_lock(&ice->gpio_mutex);
0225     nval = oval = wm_get(ice, WM_ADC_MUX);
0226     if (ucontrol->value.integer.value[0])
0227         nval |= (1 << bit);
0228     else
0229         nval &= ~(1 << bit);
0230     change = nval != oval;
0231     if (change) {
0232         wm_put(ice, WM_ADC_MUX, nval);
0233     }
0234     mutex_unlock(&ice->gpio_mutex);
0235     return change;
0236 }
0237 
0238 /*
0239  * Analog bypass (In -> Out)
0240  */
0241 #define wm_bypass_info      snd_ctl_boolean_mono_info
0242 
0243 static int wm_bypass_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0244 {
0245     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0246 
0247     mutex_lock(&ice->gpio_mutex);
0248     ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
0249     mutex_unlock(&ice->gpio_mutex);
0250     return 0;
0251 }
0252 
0253 static int wm_bypass_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0254 {
0255     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0256     unsigned short val, oval;
0257     int change = 0;
0258 
0259     mutex_lock(&ice->gpio_mutex);
0260     val = oval = wm_get(ice, WM_OUT_MUX);
0261     if (ucontrol->value.integer.value[0])
0262         val |= 0x04;
0263     else
0264         val &= ~0x04;
0265     if (val != oval) {
0266         wm_put(ice, WM_OUT_MUX, val);
0267         change = 1;
0268     }
0269     mutex_unlock(&ice->gpio_mutex);
0270     return change;
0271 }
0272 
0273 /*
0274  * Left/Right swap
0275  */
0276 #define wm_chswap_info      snd_ctl_boolean_mono_info
0277 
0278 static int wm_chswap_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0279 {
0280     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0281 
0282     mutex_lock(&ice->gpio_mutex);
0283     ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
0284     mutex_unlock(&ice->gpio_mutex);
0285     return 0;
0286 }
0287 
0288 static int wm_chswap_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0289 {
0290     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0291     unsigned short val, oval;
0292     int change = 0;
0293 
0294     mutex_lock(&ice->gpio_mutex);
0295     oval = wm_get(ice, WM_DAC_CTRL1);
0296     val = oval & 0x0f;
0297     if (ucontrol->value.integer.value[0])
0298         val |= 0x60;
0299     else
0300         val |= 0x90;
0301     if (val != oval) {
0302         wm_put(ice, WM_DAC_CTRL1, val);
0303         wm_put_nocache(ice, WM_DAC_CTRL1, val);
0304         change = 1;
0305     }
0306     mutex_unlock(&ice->gpio_mutex);
0307     return change;
0308 }
0309 
0310 /*
0311  * write data in the SPI mode
0312  */
0313 static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
0314 {
0315     unsigned int tmp = snd_ice1712_gpio_read(ice);
0316     if (val)
0317         tmp |= bit;
0318     else
0319         tmp &= ~bit;
0320     snd_ice1712_gpio_write(ice, tmp);
0321 }
0322 
0323 static void spi_send_byte(struct snd_ice1712 *ice, unsigned char data)
0324 {
0325     int i;
0326     for (i = 0; i < 8; i++) {
0327         set_gpio_bit(ice, PONTIS_CS_CLK, 0);
0328         udelay(1);
0329         set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
0330         udelay(1);
0331         set_gpio_bit(ice, PONTIS_CS_CLK, 1);
0332         udelay(1);
0333         data <<= 1;
0334     }
0335 }
0336 
0337 static unsigned int spi_read_byte(struct snd_ice1712 *ice)
0338 {
0339     int i;
0340     unsigned int val = 0;
0341 
0342     for (i = 0; i < 8; i++) {
0343         val <<= 1;
0344         set_gpio_bit(ice, PONTIS_CS_CLK, 0);
0345         udelay(1);
0346         if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
0347             val |= 1;
0348         udelay(1);
0349         set_gpio_bit(ice, PONTIS_CS_CLK, 1);
0350         udelay(1);
0351     }
0352     return val;
0353 }
0354 
0355 
0356 static void spi_write(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg, unsigned int data)
0357 {
0358     snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
0359     snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
0360     set_gpio_bit(ice, PONTIS_CS_CS, 0);
0361     spi_send_byte(ice, dev & ~1); /* WRITE */
0362     spi_send_byte(ice, reg); /* MAP */
0363     spi_send_byte(ice, data); /* DATA */
0364     /* trigger */
0365     set_gpio_bit(ice, PONTIS_CS_CS, 1);
0366     udelay(1);
0367     /* restore */
0368     snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
0369     snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
0370 }
0371 
0372 static unsigned int spi_read(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg)
0373 {
0374     unsigned int val;
0375     snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
0376     snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
0377     set_gpio_bit(ice, PONTIS_CS_CS, 0);
0378     spi_send_byte(ice, dev & ~1); /* WRITE */
0379     spi_send_byte(ice, reg); /* MAP */
0380     /* trigger */
0381     set_gpio_bit(ice, PONTIS_CS_CS, 1);
0382     udelay(1);
0383     set_gpio_bit(ice, PONTIS_CS_CS, 0);
0384     spi_send_byte(ice, dev | 1); /* READ */
0385     val = spi_read_byte(ice);
0386     /* trigger */
0387     set_gpio_bit(ice, PONTIS_CS_CS, 1);
0388     udelay(1);
0389     /* restore */
0390     snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
0391     snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
0392     return val;
0393 }
0394 
0395 
0396 /*
0397  * SPDIF input source
0398  */
0399 static int cs_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0400 {
0401     static const char * const texts[] = {
0402         "Coax",     /* RXP0 */
0403         "Optical",  /* RXP1 */
0404         "CD",       /* RXP2 */
0405     };
0406     return snd_ctl_enum_info(uinfo, 1, 3, texts);
0407 }
0408 
0409 static int cs_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0410 {
0411     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0412 
0413     mutex_lock(&ice->gpio_mutex);
0414     ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
0415     mutex_unlock(&ice->gpio_mutex);
0416     return 0;
0417 }
0418 
0419 static int cs_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0420 {
0421     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0422     unsigned char val;
0423     int change = 0;
0424 
0425     mutex_lock(&ice->gpio_mutex);
0426     if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
0427         ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
0428         val = 0x80 | (ice->gpio.saved[0] << 3);
0429         spi_write(ice, CS_DEV, 0x04, val);
0430         change = 1;
0431     }
0432     mutex_unlock(&ice->gpio_mutex);
0433     return change;
0434 }
0435 
0436 
0437 /*
0438  * GPIO controls
0439  */
0440 static int pontis_gpio_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
0441 {
0442     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0443     uinfo->count = 1;
0444     uinfo->value.integer.min = 0;
0445     uinfo->value.integer.max = 0xffff; /* 16bit */
0446     return 0;
0447 }
0448 
0449 static int pontis_gpio_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0450 {
0451     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0452     mutex_lock(&ice->gpio_mutex);
0453     /* 4-7 reserved */
0454     ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
0455     mutex_unlock(&ice->gpio_mutex);
0456     return 0;
0457 }
0458     
0459 static int pontis_gpio_mask_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0460 {
0461     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0462     unsigned int val;
0463     int changed;
0464     mutex_lock(&ice->gpio_mutex);
0465     /* 4-7 reserved */
0466     val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
0467     changed = val != ice->gpio.write_mask;
0468     ice->gpio.write_mask = val;
0469     mutex_unlock(&ice->gpio_mutex);
0470     return changed;
0471 }
0472 
0473 static int pontis_gpio_dir_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0474 {
0475     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0476     mutex_lock(&ice->gpio_mutex);
0477     /* 4-7 reserved */
0478     ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
0479     mutex_unlock(&ice->gpio_mutex);
0480     return 0;
0481 }
0482     
0483 static int pontis_gpio_dir_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0484 {
0485     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0486     unsigned int val;
0487     int changed;
0488     mutex_lock(&ice->gpio_mutex);
0489     /* 4-7 reserved */
0490     val = ucontrol->value.integer.value[0] & 0xff0f;
0491     changed = (val != ice->gpio.direction);
0492     ice->gpio.direction = val;
0493     mutex_unlock(&ice->gpio_mutex);
0494     return changed;
0495 }
0496 
0497 static int pontis_gpio_data_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0498 {
0499     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0500     mutex_lock(&ice->gpio_mutex);
0501     snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
0502     snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
0503     ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
0504     mutex_unlock(&ice->gpio_mutex);
0505     return 0;
0506 }
0507 
0508 static int pontis_gpio_data_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
0509 {
0510     struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
0511     unsigned int val, nval;
0512     int changed = 0;
0513     mutex_lock(&ice->gpio_mutex);
0514     snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
0515     snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
0516     val = snd_ice1712_gpio_read(ice) & 0xffff;
0517     nval = ucontrol->value.integer.value[0] & 0xffff;
0518     if (val != nval) {
0519         snd_ice1712_gpio_write(ice, nval);
0520         changed = 1;
0521     }
0522     mutex_unlock(&ice->gpio_mutex);
0523     return changed;
0524 }
0525 
0526 static const DECLARE_TLV_DB_SCALE(db_scale_volume, -6400, 50, 1);
0527 
0528 /*
0529  * mixers
0530  */
0531 
0532 static const struct snd_kcontrol_new pontis_controls[] = {
0533     {
0534         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0535         .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
0536                SNDRV_CTL_ELEM_ACCESS_TLV_READ),
0537         .name = "PCM Playback Volume",
0538         .info = wm_dac_vol_info,
0539         .get = wm_dac_vol_get,
0540         .put = wm_dac_vol_put,
0541         .tlv = { .p = db_scale_volume },
0542     },
0543     {
0544         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0545         .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
0546                SNDRV_CTL_ELEM_ACCESS_TLV_READ),
0547         .name = "Capture Volume",
0548         .info = wm_adc_vol_info,
0549         .get = wm_adc_vol_get,
0550         .put = wm_adc_vol_put,
0551         .tlv = { .p = db_scale_volume },
0552     },
0553     {
0554         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0555         .name = "CD Capture Switch",
0556         .info = wm_adc_mux_info,
0557         .get = wm_adc_mux_get,
0558         .put = wm_adc_mux_put,
0559         .private_value = 0,
0560     },
0561     {
0562         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0563         .name = "Line Capture Switch",
0564         .info = wm_adc_mux_info,
0565         .get = wm_adc_mux_get,
0566         .put = wm_adc_mux_put,
0567         .private_value = 1,
0568     },
0569     {
0570         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0571         .name = "Analog Bypass Switch",
0572         .info = wm_bypass_info,
0573         .get = wm_bypass_get,
0574         .put = wm_bypass_put,
0575     },
0576     {
0577         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0578         .name = "Swap Output Channels",
0579         .info = wm_chswap_info,
0580         .get = wm_chswap_get,
0581         .put = wm_chswap_put,
0582     },
0583     {
0584         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0585         .name = "IEC958 Input Source",
0586         .info = cs_source_info,
0587         .get = cs_source_get,
0588         .put = cs_source_put,
0589     },
0590     /* FIXME: which interface? */
0591     {
0592         .iface = SNDRV_CTL_ELEM_IFACE_CARD,
0593         .name = "GPIO Mask",
0594         .info = pontis_gpio_mask_info,
0595         .get = pontis_gpio_mask_get,
0596         .put = pontis_gpio_mask_put,
0597     },
0598     {
0599         .iface = SNDRV_CTL_ELEM_IFACE_CARD,
0600         .name = "GPIO Direction",
0601         .info = pontis_gpio_mask_info,
0602         .get = pontis_gpio_dir_get,
0603         .put = pontis_gpio_dir_put,
0604     },
0605     {
0606         .iface = SNDRV_CTL_ELEM_IFACE_CARD,
0607         .name = "GPIO Data",
0608         .info = pontis_gpio_mask_info,
0609         .get = pontis_gpio_data_get,
0610         .put = pontis_gpio_data_put,
0611     },
0612 };
0613 
0614 
0615 /*
0616  * WM codec registers
0617  */
0618 static void wm_proc_regs_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
0619 {
0620     struct snd_ice1712 *ice = entry->private_data;
0621     char line[64];
0622     unsigned int reg, val;
0623     mutex_lock(&ice->gpio_mutex);
0624     while (!snd_info_get_line(buffer, line, sizeof(line))) {
0625         if (sscanf(line, "%x %x", &reg, &val) != 2)
0626             continue;
0627         if (reg <= 0x17 && val <= 0xffff)
0628             wm_put(ice, reg, val);
0629     }
0630     mutex_unlock(&ice->gpio_mutex);
0631 }
0632 
0633 static void wm_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
0634 {
0635     struct snd_ice1712 *ice = entry->private_data;
0636     int reg, val;
0637 
0638     mutex_lock(&ice->gpio_mutex);
0639     for (reg = 0; reg <= 0x17; reg++) {
0640         val = wm_get(ice, reg);
0641         snd_iprintf(buffer, "%02x = %04x\n", reg, val);
0642     }
0643     mutex_unlock(&ice->gpio_mutex);
0644 }
0645 
0646 static void wm_proc_init(struct snd_ice1712 *ice)
0647 {
0648     snd_card_rw_proc_new(ice->card, "wm_codec", ice, wm_proc_regs_read,
0649                  wm_proc_regs_write);
0650 }
0651 
0652 static void cs_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
0653 {
0654     struct snd_ice1712 *ice = entry->private_data;
0655     int reg, val;
0656 
0657     mutex_lock(&ice->gpio_mutex);
0658     for (reg = 0; reg <= 0x26; reg++) {
0659         val = spi_read(ice, CS_DEV, reg);
0660         snd_iprintf(buffer, "%02x = %02x\n", reg, val);
0661     }
0662     val = spi_read(ice, CS_DEV, 0x7f);
0663     snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
0664     mutex_unlock(&ice->gpio_mutex);
0665 }
0666 
0667 static void cs_proc_init(struct snd_ice1712 *ice)
0668 {
0669     snd_card_ro_proc_new(ice->card, "cs_codec", ice, cs_proc_regs_read);
0670 }
0671 
0672 
0673 static int pontis_add_controls(struct snd_ice1712 *ice)
0674 {
0675     unsigned int i;
0676     int err;
0677 
0678     for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
0679         err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
0680         if (err < 0)
0681             return err;
0682     }
0683 
0684     wm_proc_init(ice);
0685     cs_proc_init(ice);
0686 
0687     return 0;
0688 }
0689 
0690 
0691 /*
0692  * initialize the chip
0693  */
0694 static int pontis_init(struct snd_ice1712 *ice)
0695 {
0696     static const unsigned short wm_inits[] = {
0697         /* These come first to reduce init pop noise */
0698         WM_ADC_MUX, 0x00c0, /* ADC mute */
0699         WM_DAC_MUTE,    0x0001, /* DAC softmute */
0700         WM_DAC_CTRL1,   0x0000, /* DAC mute */
0701 
0702         WM_POWERDOWN,   0x0008, /* All power-up except HP */
0703         WM_RESET,   0x0000, /* reset */
0704     };
0705     static const unsigned short wm_inits2[] = {
0706         WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
0707         WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
0708         WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
0709         WM_DAC_CTRL1,   0x0090, /* DAC L/R */
0710         WM_OUT_MUX, 0x0001, /* OUT DAC */
0711         WM_HP_ATTEN_L,  0x0179, /* HP 0dB */
0712         WM_HP_ATTEN_R,  0x0179, /* HP 0dB */
0713         WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
0714         WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
0715         WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
0716         WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
0717         /* WM_DAC_MASTER,   0x0100, */  /* DAC master muted */
0718         WM_PHASE_SWAP,  0x0000, /* phase normal */
0719         WM_DAC_CTRL2,   0x0000, /* no deemphasis, no ZFLG */
0720         WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
0721         WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
0722 #if 0
0723         WM_ALC_CTRL1,   0x007b, /* */
0724         WM_ALC_CTRL2,   0x0000, /* */
0725         WM_ALC_CTRL3,   0x0000, /* */
0726         WM_NOISE_GATE,  0x0000, /* */
0727 #endif
0728         WM_DAC_MUTE,    0x0000, /* DAC unmute */
0729         WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
0730     };
0731     static const unsigned char cs_inits[] = {
0732         0x04,   0x80,   /* RUN, RXP0 */
0733         0x05,   0x05,   /* slave, 24bit */
0734         0x01,   0x00,
0735         0x02,   0x00,
0736         0x03,   0x00,
0737     };
0738     unsigned int i;
0739 
0740     ice->vt1720 = 1;
0741     ice->num_total_dacs = 2;
0742     ice->num_total_adcs = 2;
0743 
0744     /* to remember the register values */
0745     ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
0746     if (! ice->akm)
0747         return -ENOMEM;
0748     ice->akm_codecs = 1;
0749 
0750     /* HACK - use this as the SPDIF source.
0751      * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
0752      */
0753     ice->gpio.saved[0] = 0;
0754 
0755     /* initialize WM8776 codec */
0756     for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
0757         wm_put(ice, wm_inits[i], wm_inits[i+1]);
0758     schedule_timeout_uninterruptible(1);
0759     for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
0760         wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
0761 
0762     /* initialize CS8416 codec */
0763     /* assert PRST#; MT05 bit 7 */
0764     outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
0765     mdelay(5);
0766     /* deassert PRST# */
0767     outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
0768 
0769     for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
0770         spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
0771 
0772     return 0;
0773 }
0774 
0775 
0776 /*
0777  * Pontis boards don't provide the EEPROM data at all.
0778  * hence the driver needs to sets up it properly.
0779  */
0780 
0781 static const unsigned char pontis_eeprom[] = {
0782     [ICE_EEP2_SYSCONF]     = 0x08,  /* clock 256, mpu401, spdif-in/ADC, 1DAC */
0783     [ICE_EEP2_ACLINK]      = 0x80,  /* I2S */
0784     [ICE_EEP2_I2S]         = 0xf8,  /* vol, 96k, 24bit, 192k */
0785     [ICE_EEP2_SPDIF]       = 0xc3,  /* out-en, out-int, spdif-in */
0786     [ICE_EEP2_GPIO_DIR]    = 0x07,
0787     [ICE_EEP2_GPIO_DIR1]   = 0x00,
0788     [ICE_EEP2_GPIO_DIR2]   = 0x00,  /* ignored */
0789     [ICE_EEP2_GPIO_MASK]   = 0x0f,  /* 4-7 reserved for CS8416 */
0790     [ICE_EEP2_GPIO_MASK1]  = 0xff,
0791     [ICE_EEP2_GPIO_MASK2]  = 0x00,  /* ignored */
0792     [ICE_EEP2_GPIO_STATE]  = 0x06,  /* 0-low, 1-high, 2-high */
0793     [ICE_EEP2_GPIO_STATE1] = 0x00,
0794     [ICE_EEP2_GPIO_STATE2] = 0x00,  /* ignored */
0795 };
0796 
0797 /* entry point */
0798 struct snd_ice1712_card_info snd_vt1720_pontis_cards[] = {
0799     {
0800         .subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
0801         .name = "Pontis MS300",
0802         .model = "ms300",
0803         .chip_init = pontis_init,
0804         .build_controls = pontis_add_controls,
0805         .eeprom_size = sizeof(pontis_eeprom),
0806         .eeprom_data = pontis_eeprom,
0807     },
0808     { } /* terminator */
0809 };
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