pci/ice1712/ice1712.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_ICE1712_H
0003 #define __SOUND_ICE1712_H
0004
0005 /*
0006  *   ALSA driver for ICEnsemble ICE1712 (Envy24)
0007  *
0008  *  Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
0009  */
0010
0011 #include <linux/io.h>
0012 #include <sound/control.h>
0013 #include <sound/ac97_codec.h>
0014 #include <sound/rawmidi.h>
0015 #include <sound/i2c.h>
0016 #include <sound/ak4xxx-adda.h>
0017 #include <sound/ak4114.h>
0018 #include <sound/pt2258.h>
0019 #include <sound/pcm.h>
0020 #include <sound/mpu401.h>
0021
0022
0023 /*
0024  *  Direct registers
0025  */
0026
0027 #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
0028
0029 #define ICE1712_REG_CONTROL     0x00    /* byte */
0030 #define   ICE1712_RESET         0x80    /* soft reset whole chip */
0031 #define   ICE1712_SERR_ASSERT_DS_DMA    0x40    /* disabled SERR# assertion for the DS DMA Ch-C irq otherwise enabled */
0032 #define   ICE1712_DOS_VOL       0x10    /* DOS WT/FM volume control */
0033 #define   ICE1712_SERR_LEVEL        0x08    /* SERR# level otherwise edge */
0034 #define   ICE1712_SERR_ASSERT_SB    0x02    /* disabled SERR# assertion for SB irq otherwise enabled */
0035 #define   ICE1712_NATIVE        0x01    /* native mode otherwise SB */
0036 #define ICE1712_REG_IRQMASK     0x01    /* byte */
0037 #define   ICE1712_IRQ_MPU1      0x80    /* MIDI irq mask */
0038 #define   ICE1712_IRQ_TIMER     0x40    /* Timer mask */
0039 #define   ICE1712_IRQ_MPU2      0x20    /* Secondary MIDI irq mask */
0040 #define   ICE1712_IRQ_PROPCM        0x10    /* professional multi-track */
0041 #define   ICE1712_IRQ_FM        0x08    /* FM/MIDI - legacy */
0042 #define   ICE1712_IRQ_PBKDS     0x04    /* playback DS channels */
0043 #define   ICE1712_IRQ_CONCAP        0x02    /* consumer capture */
0044 #define   ICE1712_IRQ_CONPBK        0x01    /* consumer playback */
0045 #define ICE1712_REG_IRQSTAT     0x02    /* byte */
0046 /* look to ICE1712_IRQ_* */
0047 #define ICE1712_REG_INDEX       0x03    /* byte - indirect CCIxx regs */
0048 #define ICE1712_REG_DATA        0x04    /* byte - indirect CCIxx regs */
0049 #define ICE1712_REG_NMI_STAT1       0x05    /* byte */
0050 #define ICE1712_REG_NMI_DATA        0x06    /* byte */
0051 #define ICE1712_REG_NMI_INDEX       0x07    /* byte */
0052 #define ICE1712_REG_AC97_INDEX      0x08    /* byte */
0053 #define ICE1712_REG_AC97_CMD        0x09    /* byte */
0054 #define   ICE1712_AC97_COLD     0x80    /* cold reset */
0055 #define   ICE1712_AC97_WARM     0x40    /* warm reset */
0056 #define   ICE1712_AC97_WRITE        0x20    /* W: write, R: write in progress */
0057 #define   ICE1712_AC97_READ     0x10    /* W: read, R: read in progress */
0058 #define   ICE1712_AC97_READY        0x08    /* codec ready status bit */
0059 #define   ICE1712_AC97_PBK_VSR      0x02    /* playback VSR */
0060 #define   ICE1712_AC97_CAP_VSR      0x01    /* capture VSR */
0061 #define ICE1712_REG_AC97_DATA       0x0a    /* word (little endian) */
0062 #define ICE1712_REG_MPU1_CTRL       0x0c    /* byte */
0063 #define ICE1712_REG_MPU1_DATA       0x0d    /* byte */
0064 #define ICE1712_REG_I2C_DEV_ADDR    0x10    /* byte */
0065 #define   ICE1712_I2C_WRITE     0x01    /* write direction */
0066 #define ICE1712_REG_I2C_BYTE_ADDR   0x11    /* byte */
0067 #define ICE1712_REG_I2C_DATA        0x12    /* byte */
0068 #define ICE1712_REG_I2C_CTRL        0x13    /* byte */
0069 #define   ICE1712_I2C_EEPROM        0x80    /* EEPROM exists */
0070 #define   ICE1712_I2C_BUSY      0x01    /* busy bit */
0071 #define ICE1712_REG_CONCAP_ADDR     0x14    /* dword - consumer capture */
0072 #define ICE1712_REG_CONCAP_COUNT    0x18    /* word - current/base count */
0073 #define ICE1712_REG_SERR_SHADOW     0x1b    /* byte */
0074 #define ICE1712_REG_MPU2_CTRL       0x1c    /* byte */
0075 #define ICE1712_REG_MPU2_DATA       0x1d    /* byte */
0076 #define ICE1712_REG_TIMER       0x1e    /* word */
0077
0078 /*
0079  *  Indirect registers
0080  */
0081
0082 #define ICE1712_IREG_PBK_COUNT_LO   0x00
0083 #define ICE1712_IREG_PBK_COUNT_HI   0x01
0084 #define ICE1712_IREG_PBK_CTRL       0x02
0085 #define ICE1712_IREG_PBK_LEFT       0x03    /* left volume */
0086 #define ICE1712_IREG_PBK_RIGHT      0x04    /* right volume */
0087 #define ICE1712_IREG_PBK_SOFT       0x05    /* soft volume */
0088 #define ICE1712_IREG_PBK_RATE_LO    0x06
0089 #define ICE1712_IREG_PBK_RATE_MID   0x07
0090 #define ICE1712_IREG_PBK_RATE_HI    0x08
0091 #define ICE1712_IREG_CAP_COUNT_LO   0x10
0092 #define ICE1712_IREG_CAP_COUNT_HI   0x11
0093 #define ICE1712_IREG_CAP_CTRL       0x12
0094 #define ICE1712_IREG_GPIO_DATA      0x20
0095 #define ICE1712_IREG_GPIO_WRITE_MASK    0x21
0096 #define ICE1712_IREG_GPIO_DIRECTION 0x22
0097 #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
0098 #define ICE1712_IREG_PRO_POWERDOWN  0x31
0099
0100 /*
0101  *  Consumer section direct DMA registers
0102  */
0103
0104 #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
0105
0106 #define ICE1712_DS_INTMASK      0x00    /* word - interrupt mask */
0107 #define ICE1712_DS_INTSTAT      0x02    /* word - interrupt status */
0108 #define ICE1712_DS_DATA         0x04    /* dword - channel data */
0109 #define ICE1712_DS_INDEX        0x08    /* dword - channel index */
0110
0111 /*
0112  *  Consumer section channel registers
0113  */
0114
0115 #define ICE1712_DSC_ADDR0       0x00    /* dword - base address 0 */
0116 #define ICE1712_DSC_COUNT0      0x01    /* word - count 0 */
0117 #define ICE1712_DSC_ADDR1       0x02    /* dword - base address 1 */
0118 #define ICE1712_DSC_COUNT1      0x03    /* word - count 1 */
0119 #define ICE1712_DSC_CONTROL     0x04    /* byte - control & status */
0120 #define   ICE1712_BUFFER1       0x80    /* buffer1 is active */
0121 #define   ICE1712_BUFFER1_AUTO      0x40    /* buffer1 auto init */
0122 #define   ICE1712_BUFFER0_AUTO      0x20    /* buffer0 auto init */
0123 #define   ICE1712_FLUSH         0x10    /* flush FIFO */
0124 #define   ICE1712_STEREO        0x08    /* stereo */
0125 #define   ICE1712_16BIT         0x04    /* 16-bit data */
0126 #define   ICE1712_PAUSE         0x02    /* pause */
0127 #define   ICE1712_START         0x01    /* start */
0128 #define ICE1712_DSC_RATE        0x05    /* dword - rate */
0129 #define ICE1712_DSC_VOLUME      0x06    /* word - volume control */
0130
0131 /*
0132  *  Professional multi-track direct control registers
0133  */
0134
0135 #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
0136
0137 #define ICE1712_MT_IRQ          0x00    /* byte - interrupt mask */
0138 #define   ICE1712_MULTI_CAPTURE     0x80    /* capture IRQ */
0139 #define   ICE1712_MULTI_PLAYBACK    0x40    /* playback IRQ */
0140 #define   ICE1712_MULTI_CAPSTATUS   0x02    /* capture IRQ status */
0141 #define   ICE1712_MULTI_PBKSTATUS   0x01    /* playback IRQ status */
0142 #define ICE1712_MT_RATE         0x01    /* byte - sampling rate select */
0143 #define   ICE1712_SPDIF_MASTER      0x10    /* S/PDIF input is master clock */
0144 #define ICE1712_MT_I2S_FORMAT       0x02    /* byte - I2S data format */
0145 #define ICE1712_MT_AC97_INDEX       0x04    /* byte - AC'97 index */
0146 #define ICE1712_MT_AC97_CMD     0x05    /* byte - AC'97 command & status */
0147 /* look to ICE1712_AC97_* */
0148 #define ICE1712_MT_AC97_DATA        0x06    /* word - AC'97 data */
0149 #define ICE1712_MT_PLAYBACK_ADDR    0x10    /* dword - playback address */
0150 #define ICE1712_MT_PLAYBACK_SIZE    0x14    /* word - playback size */
0151 #define ICE1712_MT_PLAYBACK_COUNT   0x16    /* word - playback count */
0152 #define ICE1712_MT_PLAYBACK_CONTROL 0x18    /* byte - control */
0153 #define   ICE1712_CAPTURE_START_SHADOW  0x04    /* capture start */
0154 #define   ICE1712_PLAYBACK_PAUSE    0x02    /* playback pause */
0155 #define   ICE1712_PLAYBACK_START    0x01    /* playback start */
0156 #define ICE1712_MT_CAPTURE_ADDR     0x20    /* dword - capture address */
0157 #define ICE1712_MT_CAPTURE_SIZE     0x24    /* word - capture size */
0158 #define ICE1712_MT_CAPTURE_COUNT    0x26    /* word - capture count */
0159 #define ICE1712_MT_CAPTURE_CONTROL  0x28    /* byte - control */
0160 #define   ICE1712_CAPTURE_START     0x01    /* capture start */
0161 #define ICE1712_MT_ROUTE_PSDOUT03   0x30    /* word */
0162 #define ICE1712_MT_ROUTE_SPDOUT     0x32    /* word */
0163 #define ICE1712_MT_ROUTE_CAPTURE    0x34    /* dword */
0164 #define ICE1712_MT_MONITOR_VOLUME   0x38    /* word */
0165 #define ICE1712_MT_MONITOR_INDEX    0x3a    /* byte */
0166 #define ICE1712_MT_MONITOR_RATE     0x3b    /* byte */
0167 #define ICE1712_MT_MONITOR_ROUTECTRL    0x3c    /* byte */
0168 #define   ICE1712_ROUTE_AC97        0x01    /* route digital mixer output to AC'97 */
0169 #define ICE1712_MT_MONITOR_PEAKINDEX    0x3e    /* byte */
0170 #define ICE1712_MT_MONITOR_PEAKDATA 0x3f    /* byte */
0171
0172 /*
0173  *  Codec configuration bits
0174  */
0175
0176 /* PCI[60] System Configuration */
0177 #define ICE1712_CFG_CLOCK   0xc0
0178 #define   ICE1712_CFG_CLOCK512  0x00    /* 22.5692Mhz, 44.1kHz*512 */
0179 #define   ICE1712_CFG_CLOCK384  0x40    /* 16.9344Mhz, 44.1kHz*384 */
0180 #define   ICE1712_CFG_EXT   0x80    /* external clock */
0181 #define ICE1712_CFG_2xMPU401    0x20    /* two MPU401 UARTs */
0182 #define ICE1712_CFG_NO_CON_AC97 0x10    /* consumer AC'97 codec is not present */
0183 #define ICE1712_CFG_ADC_MASK    0x0c    /* one, two, three, four stereo ADCs */
0184 #define ICE1712_CFG_DAC_MASK    0x03    /* one, two, three, four stereo DACs */
0185 /* PCI[61] AC-Link Configuration */
0186 #define ICE1712_CFG_PRO_I2S 0x80    /* multitrack converter: I2S or AC'97 */
0187 #define ICE1712_CFG_AC97_PACKED 0x01    /* split or packed mode - AC'97 */
0188 /* PCI[62] I2S Features */
0189 #define ICE1712_CFG_I2S_VOLUME  0x80    /* volume/mute capability */
0190 #define ICE1712_CFG_I2S_96KHZ   0x40    /* supports 96kHz sampling */
0191 #define ICE1712_CFG_I2S_RESMASK 0x30    /* resolution mask, 16,18,20,24-bit */
0192 #define ICE1712_CFG_I2S_OTHER   0x0f    /* other I2S IDs */
0193 /* PCI[63] S/PDIF Configuration */
0194 #define ICE1712_CFG_I2S_CHIPID  0xfc    /* I2S chip ID */
0195 #define ICE1712_CFG_SPDIF_IN    0x02    /* S/PDIF input is present */
0196 #define ICE1712_CFG_SPDIF_OUT   0x01    /* S/PDIF output is present */
0197
0198 /*
0199  * DMA mode values
0200  * identical with DMA_XXX on i386 architecture.
0201  */
0202 #define ICE1712_DMA_MODE_WRITE      0x48
0203 #define ICE1712_DMA_AUTOINIT        0x10
0204
0205
0206 /*
0207  * I2C EEPROM Address
0208  */
0209 #define ICE_I2C_EEPROM_ADDR     0xA0
0210
0211 struct snd_ice1712;
0212
0213 struct snd_ice1712_eeprom {
0214     unsigned int subvendor; /* PCI[2c-2f] */
0215     unsigned char size; /* size of EEPROM image in bytes */
0216     unsigned char version;  /* must be 1 (or 2 for vt1724) */
0217     unsigned char data[32];
0218     unsigned int gpiomask;
0219     unsigned int gpiostate;
0220     unsigned int gpiodir;
0221 };
0222
0223 enum {
0224     ICE_EEP1_CODEC = 0, /* 06 */
0225     ICE_EEP1_ACLINK,    /* 07 */
0226     ICE_EEP1_I2SID,     /* 08 */
0227     ICE_EEP1_SPDIF,     /* 09 */
0228     ICE_EEP1_GPIO_MASK, /* 0a */
0229     ICE_EEP1_GPIO_STATE,    /* 0b */
0230     ICE_EEP1_GPIO_DIR,  /* 0c */
0231     ICE_EEP1_AC97_MAIN_LO,  /* 0d */
0232     ICE_EEP1_AC97_MAIN_HI,  /* 0e */
0233     ICE_EEP1_AC97_PCM_LO,   /* 0f */
0234     ICE_EEP1_AC97_PCM_HI,   /* 10 */
0235     ICE_EEP1_AC97_REC_LO,   /* 11 */
0236     ICE_EEP1_AC97_REC_HI,   /* 12 */
0237     ICE_EEP1_AC97_RECSRC,   /* 13 */
0238     ICE_EEP1_DAC_ID,    /* 14 */
0239     ICE_EEP1_DAC_ID1,
0240     ICE_EEP1_DAC_ID2,
0241     ICE_EEP1_DAC_ID3,
0242     ICE_EEP1_ADC_ID,    /* 18 */
0243     ICE_EEP1_ADC_ID1,
0244     ICE_EEP1_ADC_ID2,
0245     ICE_EEP1_ADC_ID3
0246 };
0247
0248 #define ice_has_con_ac97(ice)   (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
0249
0250
0251 struct snd_ak4xxx_private {
0252     unsigned int cif:1;     /* CIF mode */
0253     unsigned char caddr;        /* C0 and C1 bits */
0254     unsigned int data_mask;     /* DATA gpio bit */
0255     unsigned int clk_mask;      /* CLK gpio bit */
0256     unsigned int cs_mask;       /* bit mask for select/deselect address */
0257     unsigned int cs_addr;       /* bits to select address */
0258     unsigned int cs_none;       /* bits to deselect address */
0259     unsigned int add_flags;     /* additional bits at init */
0260     unsigned int mask_flags;    /* total mask bits */
0261     struct snd_akm4xxx_ops {
0262         void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate);
0263     } ops;
0264 };
0265
0266 struct snd_ice1712_spdif {
0267     unsigned char cs8403_bits;
0268     unsigned char cs8403_stream_bits;
0269     struct snd_kcontrol *stream_ctl;
0270
0271     struct snd_ice1712_spdif_ops {
0272         void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *);
0273         void (*setup_rate)(struct snd_ice1712 *, int rate);
0274         void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *);
0275         void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
0276         int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
0277         void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
0278         int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
0279     } ops;
0280 };
0281
0282 struct snd_ice1712_card_info;
0283
0284 struct snd_ice1712 {
0285     unsigned long conp_dma_size;
0286     unsigned long conc_dma_size;
0287     unsigned long prop_dma_size;
0288     unsigned long proc_dma_size;
0289     int irq;
0290
0291     unsigned long port;
0292     unsigned long ddma_port;
0293     unsigned long dmapath_port;
0294     unsigned long profi_port;
0295
0296     struct pci_dev *pci;
0297     struct snd_card *card;
0298     struct snd_pcm *pcm;
0299     struct snd_pcm *pcm_ds;
0300     struct snd_pcm *pcm_pro;
0301     struct snd_pcm_substream *playback_con_substream;
0302     struct snd_pcm_substream *playback_con_substream_ds[6];
0303     struct snd_pcm_substream *capture_con_substream;
0304     struct snd_pcm_substream *playback_pro_substream;
0305     struct snd_pcm_substream *capture_pro_substream;
0306     unsigned int playback_pro_size;
0307     unsigned int capture_pro_size;
0308     unsigned int playback_con_virt_addr[6];
0309     unsigned int playback_con_active_buf[6];
0310     unsigned int capture_con_virt_addr;
0311     unsigned int ac97_ext_id;
0312     struct snd_ac97 *ac97;
0313     struct snd_rawmidi *rmidi[2];
0314
0315     spinlock_t reg_lock;
0316     struct snd_info_entry *proc_entry;
0317
0318     struct snd_ice1712_eeprom eeprom;
0319     const struct snd_ice1712_card_info *card_info;
0320
0321     unsigned int pro_volumes[20];
0322     unsigned int omni:1;        /* Delta Omni I/O */
0323     unsigned int dxr_enable:1;  /* Terratec DXR enable for DMX6FIRE */
0324     unsigned int vt1724:1;
0325     unsigned int vt1720:1;
0326     unsigned int has_spdif:1;   /* VT1720/4 - has SPDIF I/O */
0327     unsigned int force_pdma4:1; /* VT1720/4 - PDMA4 as non-spdif */
0328     unsigned int force_rdma1:1; /* VT1720/4 - RDMA1 as non-spdif */
0329     unsigned int midi_output:1; /* VT1720/4: MIDI output triggered */
0330     unsigned int midi_input:1;  /* VT1720/4: MIDI input triggered */
0331     unsigned int own_routing:1; /* VT1720/4: use own routing ctls */
0332     unsigned int num_total_dacs;    /* total DACs */
0333     unsigned int num_total_adcs;    /* total ADCs */
0334     unsigned int cur_rate;      /* current rate */
0335
0336     struct mutex open_mutex;
0337     struct snd_pcm_substream *pcm_reserved[4];
0338     const struct snd_pcm_hw_constraint_list *hw_rates; /* card-specific rate constraints */
0339
0340     unsigned int akm_codecs;
0341     struct snd_akm4xxx *akm;
0342     struct snd_ice1712_spdif spdif;
0343
0344     struct mutex i2c_mutex; /* I2C mutex for ICE1724 registers */
0345     struct snd_i2c_bus *i2c;        /* I2C bus */
0346     struct snd_i2c_device *cs8427;  /* CS8427 I2C device */
0347     unsigned int cs8427_timeout;    /* CS8427 reset timeout in HZ/100 */
0348
0349     struct ice1712_gpio {
0350         unsigned int direction;     /* current direction bits */
0351         unsigned int write_mask;    /* current mask bits */
0352         unsigned int saved[2];      /* for ewx_i2c */
0353         /* operators */
0354         void (*set_mask)(struct snd_ice1712 *ice, unsigned int data);
0355         unsigned int (*get_mask)(struct snd_ice1712 *ice);
0356         void (*set_dir)(struct snd_ice1712 *ice, unsigned int data);
0357         unsigned int (*get_dir)(struct snd_ice1712 *ice);
0358         void (*set_data)(struct snd_ice1712 *ice, unsigned int data);
0359         unsigned int (*get_data)(struct snd_ice1712 *ice);
0360         /* misc operators - move to another place? */
0361         void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate);
0362         void (*i2s_mclk_changed)(struct snd_ice1712 *ice);
0363     } gpio;
0364     struct mutex gpio_mutex;
0365
0366     /* other board-specific data */
0367     void *spec;
0368
0369     /* VT172x specific */
0370     int pro_rate_default;
0371     int (*is_spdif_master)(struct snd_ice1712 *ice);
0372     unsigned int (*get_rate)(struct snd_ice1712 *ice);
0373     void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate);
0374     unsigned char (*set_mclk)(struct snd_ice1712 *ice, unsigned int rate);
0375     int (*set_spdif_clock)(struct snd_ice1712 *ice, int type);
0376     int (*get_spdif_master_type)(struct snd_ice1712 *ice);
0377     const char * const *ext_clock_names;
0378     int ext_clock_count;
0379     void (*pro_open)(struct snd_ice1712 *, struct snd_pcm_substream *);
0380 #ifdef CONFIG_PM_SLEEP
0381     int (*pm_suspend)(struct snd_ice1712 *);
0382     int (*pm_resume)(struct snd_ice1712 *);
0383     unsigned int pm_suspend_enabled:1;
0384     unsigned int pm_saved_is_spdif_master:1;
0385     unsigned int pm_saved_spdif_ctrl;
0386     unsigned char pm_saved_spdif_cfg;
0387     unsigned int pm_saved_route;
0388 #endif
0389 };
0390
0391
0392 /*
0393  * gpio access functions
0394  */
0395 static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits)
0396 {
0397     ice->gpio.set_dir(ice, bits);
0398 }
0399
0400 static inline unsigned int snd_ice1712_gpio_get_dir(struct snd_ice1712 *ice)
0401 {
0402     return ice->gpio.get_dir(ice);
0403 }
0404
0405 static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits)
0406 {
0407     ice->gpio.set_mask(ice, bits);
0408 }
0409
0410 static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val)
0411 {
0412     ice->gpio.set_data(ice, val);
0413 }
0414
0415 static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice)
0416 {
0417     return ice->gpio.get_data(ice);
0418 }
0419
0420 /*
0421  * save and restore gpio status
0422  * The access to gpio will be protected by mutex, so don't forget to
0423  * restore!
0424  */
0425 static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice)
0426 {
0427     mutex_lock(&ice->gpio_mutex);
0428     ice->gpio.saved[0] = ice->gpio.direction;
0429     ice->gpio.saved[1] = ice->gpio.write_mask;
0430 }
0431
0432 static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice)
0433 {
0434     ice->gpio.set_dir(ice, ice->gpio.saved[0]);
0435     ice->gpio.set_mask(ice, ice->gpio.saved[1]);
0436     ice->gpio.direction = ice->gpio.saved[0];
0437     ice->gpio.write_mask = ice->gpio.saved[1];
0438     mutex_unlock(&ice->gpio_mutex);
0439 }
0440
0441 /* for bit controls */
0442 #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
0443 { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \
0444   .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
0445   .private_value = mask | (invert << 24) }
0446
0447 int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
0448 int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
0449
0450 /*
0451  * set gpio direction, write mask and data
0452  */
0453 static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice,
0454                            unsigned int mask, unsigned int bits)
0455 {
0456     unsigned val;
0457
0458     ice->gpio.direction |= mask;
0459     snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
0460     val = snd_ice1712_gpio_read(ice);
0461     val &= ~mask;
0462     val |= mask & bits;
0463     snd_ice1712_gpio_write(ice, val);
0464 }
0465
0466 static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice,
0467                           unsigned int mask)
0468 {
0469     ice->gpio.direction &= ~mask;
0470     snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
0471     return  snd_ice1712_gpio_read(ice) & mask;
0472 }
0473
0474 /* route access functions */
0475 int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift);
0476 int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
0477                                 int shift);
0478
0479 int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice);
0480
0481 int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak,
0482                  const struct snd_akm4xxx *template,
0483                  const struct snd_ak4xxx_private *priv,
0484                  struct snd_ice1712 *ice);
0485 void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice);
0486 int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice);
0487
0488 int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr);
0489
0490 static inline void snd_ice1712_write(struct snd_ice1712 *ice, u8 addr, u8 data)
0491 {
0492     outb(addr, ICEREG(ice, INDEX));
0493     outb(data, ICEREG(ice, DATA));
0494 }
0495
0496 static inline u8 snd_ice1712_read(struct snd_ice1712 *ice, u8 addr)
0497 {
0498     outb(addr, ICEREG(ice, INDEX));
0499     return inb(ICEREG(ice, DATA));
0500 }
0501
0502
0503 /*
0504  * entry pointer
0505  */
0506
0507 struct snd_ice1712_card_info {
0508     unsigned int subvendor;
0509     const char *name;
0510     const char *model;
0511     const char *driver;
0512     int (*chip_init)(struct snd_ice1712 *);
0513     void (*chip_exit)(struct snd_ice1712 *);
0514     int (*build_controls)(struct snd_ice1712 *);
0515     unsigned int no_mpu401:1;
0516     unsigned int mpu401_1_info_flags;
0517     unsigned int mpu401_2_info_flags;
0518     const char *mpu401_1_name;
0519     const char *mpu401_2_name;
0520     const unsigned int eeprom_size;
0521     const unsigned char *eeprom_data;
0522 };
0523
0524
0525 #endif /* __SOUND_ICE1712_H */