pci/ice1712/envy24ht.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_VT1724_H
0003 #define __SOUND_VT1724_H
0004
0005 /*
0006  *   ALSA driver for ICEnsemble VT1724 (Envy24)
0007  *
0008  *  Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
0009  */
0010
0011 #include <sound/control.h>
0012 #include <sound/ac97_codec.h>
0013 #include <sound/rawmidi.h>
0014 #include <sound/i2c.h>
0015 #include <sound/pcm.h>
0016
0017 #include "ice1712.h"
0018
0019 enum {
0020     ICE_EEP2_SYSCONF = 0,   /* 06 */
0021     ICE_EEP2_ACLINK,    /* 07 */
0022     ICE_EEP2_I2S,       /* 08 */
0023     ICE_EEP2_SPDIF,     /* 09 */
0024     ICE_EEP2_GPIO_DIR,  /* 0a */
0025     ICE_EEP2_GPIO_DIR1, /* 0b */
0026     ICE_EEP2_GPIO_DIR2, /* 0c */
0027     ICE_EEP2_GPIO_MASK, /* 0d */
0028     ICE_EEP2_GPIO_MASK1,    /* 0e */
0029     ICE_EEP2_GPIO_MASK2,    /* 0f */
0030     ICE_EEP2_GPIO_STATE,    /* 10 */
0031     ICE_EEP2_GPIO_STATE1,   /* 11 */
0032     ICE_EEP2_GPIO_STATE2    /* 12 */
0033 };
0034
0035 /*
0036  *  Direct registers
0037  */
0038
0039 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
0040
0041 #define VT1724_REG_CONTROL      0x00    /* byte */
0042 #define   VT1724_RESET          0x80    /* reset whole chip */
0043 #define VT1724_REG_IRQMASK      0x01    /* byte */
0044 #define   VT1724_IRQ_MPU_RX     0x80
0045 #define   VT1724_IRQ_MPU_TX     0x20
0046 #define   VT1724_IRQ_MTPCM      0x10
0047 #define VT1724_REG_IRQSTAT      0x02    /* byte */
0048 /* look to VT1724_IRQ_* */
0049 #define VT1724_REG_SYS_CFG      0x04    /* byte - system configuration PCI60 on Envy24*/
0050 #define   VT1724_CFG_CLOCK  0xc0
0051 #define     VT1724_CFG_CLOCK512 0x00    /* 22.5692Mhz, 44.1kHz*512 */
0052 #define     VT1724_CFG_CLOCK384  0x40   /* 16.9344Mhz, 44.1kHz*384 */
0053 #define   VT1724_CFG_MPU401 0x20        /* MPU401 UARTs */
0054 #define   VT1724_CFG_ADC_MASK   0x0c    /* one, two or one and S/PDIF, stereo ADCs */
0055 #define   VT1724_CFG_ADC_NONE   0x0c    /* no ADCs */
0056 #define   VT1724_CFG_DAC_MASK   0x03    /* one, two, three, four stereo DACs */
0057
0058 #define VT1724_REG_AC97_CFG     0x05    /* byte */
0059 #define   VT1724_CFG_PRO_I2S    0x80    /* multitrack converter: I2S or AC'97 */
0060 #define   VT1724_CFG_AC97_PACKED    0x01    /* split or packed mode - AC'97 */
0061
0062 #define VT1724_REG_I2S_FEATURES     0x06    /* byte */
0063 #define   VT1724_CFG_I2S_VOLUME 0x80    /* volume/mute capability */
0064 #define   VT1724_CFG_I2S_96KHZ  0x40    /* supports 96kHz sampling */
0065 #define   VT1724_CFG_I2S_RESMASK    0x30    /* resolution mask, 16,18,20,24-bit */
0066 #define   VT1724_CFG_I2S_192KHZ 0x08    /* supports 192kHz sampling */
0067 #define   VT1724_CFG_I2S_OTHER  0x07    /* other I2S IDs */
0068
0069 #define VT1724_REG_SPDIF_CFG        0x07    /* byte */
0070 #define   VT1724_CFG_SPDIF_OUT_EN   0x80    /*Internal S/PDIF output is enabled*/
0071 #define   VT1724_CFG_SPDIF_OUT_INT  0x40    /*Internal S/PDIF output is implemented*/
0072 #define   VT1724_CFG_I2S_CHIPID 0x3c    /* I2S chip ID */
0073 #define   VT1724_CFG_SPDIF_IN   0x02    /* S/PDIF input is present */
0074 #define   VT1724_CFG_SPDIF_OUT  0x01    /* External S/PDIF output is present */
0075
0076 /*there is no consumer AC97 codec with the VT1724*/
0077 //#define VT1724_REG_AC97_INDEX     0x08    /* byte */
0078 //#define VT1724_REG_AC97_CMD       0x09    /* byte */
0079
0080 #define VT1724_REG_MPU_TXFIFO       0x0a    /*byte ro. number of bytes in TX fifo*/
0081 #define VT1724_REG_MPU_RXFIFO       0x0b    /*byte ro. number of bytes in RX fifo*/
0082
0083 #define VT1724_REG_MPU_DATA     0x0c    /* byte */
0084 #define VT1724_REG_MPU_CTRL     0x0d    /* byte */
0085 #define   VT1724_MPU_UART   0x01
0086 #define   VT1724_MPU_TX_EMPTY   0x02
0087 #define   VT1724_MPU_TX_FULL    0x04
0088 #define   VT1724_MPU_RX_EMPTY   0x08
0089 #define   VT1724_MPU_RX_FULL    0x10
0090
0091 #define VT1724_REG_MPU_FIFO_WM  0x0e    /*byte set the high/low watermarks for RX/TX fifos*/
0092 #define   VT1724_MPU_RX_FIFO    0x20    //1=rx fifo watermark 0=tx fifo watermark
0093 #define   VT1724_MPU_FIFO_MASK  0x1f
0094
0095 #define VT1724_REG_I2C_DEV_ADDR 0x10    /* byte */
0096 #define   VT1724_I2C_WRITE      0x01    /* write direction */
0097 #define VT1724_REG_I2C_BYTE_ADDR    0x11    /* byte */
0098 #define VT1724_REG_I2C_DATA     0x12    /* byte */
0099 #define VT1724_REG_I2C_CTRL     0x13    /* byte */
0100 #define   VT1724_I2C_EEPROM     0x80    /* 1 = EEPROM exists */
0101 #define   VT1724_I2C_BUSY       0x01    /* busy bit */
0102
0103 #define VT1724_REG_GPIO_DATA    0x14    /* word */
0104 #define VT1724_REG_GPIO_WRITE_MASK  0x16 /* word */
0105 #define VT1724_REG_GPIO_DIRECTION   0x18 /* dword? (3 bytes) 0=input 1=output.
0106                         bit3 - during reset used for Eeprom power-on strapping
0107                         if TESTEN# pin active, bit 2 always input*/
0108 #define VT1724_REG_POWERDOWN    0x1c
0109 #define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */
0110 #define VT1724_REG_GPIO_WRITE_MASK_22   0x1f /* byte write mask for GPIO 16:22 */
0111
0112
0113 /*
0114  *  Professional multi-track direct control registers
0115  */
0116
0117 #define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
0118
0119 #define VT1724_MT_IRQ           0x00    /* byte - interrupt mask */
0120 #define   VT1724_MULTI_PDMA4    0x80    /* SPDIF Out / PDMA4 */
0121 #define   VT1724_MULTI_PDMA3    0x40    /* PDMA3 */
0122 #define   VT1724_MULTI_PDMA2    0x20    /* PDMA2 */
0123 #define   VT1724_MULTI_PDMA1    0x10    /* PDMA1 */
0124 #define   VT1724_MULTI_FIFO_ERR 0x08    /* DMA FIFO underrun/overrun. */
0125 #define   VT1724_MULTI_RDMA1    0x04    /* RDMA1 (S/PDIF input) */
0126 #define   VT1724_MULTI_RDMA0    0x02    /* RMDA0 */
0127 #define   VT1724_MULTI_PDMA0    0x01    /* MC Interleave/PDMA0 */
0128
0129 #define VT1724_MT_RATE          0x01    /* byte - sampling rate select */
0130 #define   VT1724_SPDIF_MASTER       0x10    /* S/PDIF input is master clock */
0131 #define VT1724_MT_I2S_FORMAT        0x02    /* byte - I2S data format */
0132 #define   VT1724_MT_I2S_MCLK_128X   0x08
0133 #define   VT1724_MT_I2S_FORMAT_MASK 0x03
0134 #define   VT1724_MT_I2S_FORMAT_I2S  0x00
0135 #define VT1724_MT_DMA_INT_MASK      0x03    /* byte -DMA Interrupt Mask */
0136 /* lool to VT1724_MULTI_* */
0137 #define VT1724_MT_AC97_INDEX        0x04    /* byte - AC'97 index */
0138 #define VT1724_MT_AC97_CMD      0x05    /* byte - AC'97 command & status */
0139 #define   VT1724_AC97_COLD  0x80    /* cold reset */
0140 #define   VT1724_AC97_WARM  0x40    /* warm reset */
0141 #define   VT1724_AC97_WRITE 0x20    /* W: write, R: write in progress */
0142 #define   VT1724_AC97_READ  0x10    /* W: read, R: read in progress */
0143 #define   VT1724_AC97_READY 0x08    /* codec ready status bit */
0144 #define   VT1724_AC97_ID_MASK   0x03    /* codec id mask */
0145 #define VT1724_MT_AC97_DATA     0x06    /* word - AC'97 data */
0146 #define VT1724_MT_PLAYBACK_ADDR     0x10    /* dword - playback address */
0147 #define VT1724_MT_PLAYBACK_SIZE     0x14    /* dword - playback size */
0148 #define VT1724_MT_DMA_CONTROL       0x18    /* byte - control */
0149 #define   VT1724_PDMA4_START    0x80    /* SPDIF out / PDMA4 start */
0150 #define   VT1724_PDMA3_START    0x40    /* PDMA3 start */
0151 #define   VT1724_PDMA2_START    0x20    /* PDMA2 start */
0152 #define   VT1724_PDMA1_START    0x10    /* PDMA1 start */
0153 #define   VT1724_RDMA1_START    0x04    /* RDMA1 start */
0154 #define   VT1724_RDMA0_START    0x02    /* RMDA0 start */
0155 #define   VT1724_PDMA0_START    0x01    /* MC Interleave / PDMA0 start */
0156 #define VT1724_MT_BURST         0x19    /* Interleaved playback DMA Active streams / PCI burst size */
0157 #define VT1724_MT_DMA_FIFO_ERR      0x1a    /*Global playback and record DMA FIFO Underrun/Overrun */
0158 #define   VT1724_PDMA4_UNDERRUN     0x80
0159 #define   VT1724_PDMA2_UNDERRUN     0x40
0160 #define   VT1724_PDMA3_UNDERRUN     0x20
0161 #define   VT1724_PDMA1_UNDERRUN     0x10
0162 #define   VT1724_RDMA1_UNDERRUN     0x04
0163 #define   VT1724_RDMA0_UNDERRUN     0x02
0164 #define   VT1724_PDMA0_UNDERRUN     0x01
0165 #define VT1724_MT_DMA_PAUSE     0x1b    /*Global playback and record DMA FIFO pause/resume */
0166 #define   VT1724_PDMA4_PAUSE    0x80
0167 #define   VT1724_PDMA3_PAUSE    0x40
0168 #define   VT1724_PDMA2_PAUSE    0x20
0169 #define   VT1724_PDMA1_PAUSE    0x10
0170 #define   VT1724_RDMA1_PAUSE    0x04
0171 #define   VT1724_RDMA0_PAUSE    0x02
0172 #define   VT1724_PDMA0_PAUSE    0x01
0173 #define VT1724_MT_PLAYBACK_COUNT    0x1c    /* word - playback count */
0174 #define VT1724_MT_CAPTURE_ADDR      0x20    /* dword - capture address */
0175 #define VT1724_MT_CAPTURE_SIZE      0x24    /* word - capture size */
0176 #define VT1724_MT_CAPTURE_COUNT     0x26    /* word - capture count */
0177
0178 #define VT1724_MT_ROUTE_PLAYBACK    0x2c    /* word */
0179
0180 #define VT1724_MT_RDMA1_ADDR        0x30    /* dword - RDMA1 capture address */
0181 #define VT1724_MT_RDMA1_SIZE        0x34    /* word - RDMA1 capture size */
0182 #define VT1724_MT_RDMA1_COUNT       0x36    /* word - RDMA1 capture count */
0183
0184 #define VT1724_MT_SPDIF_CTRL        0x3c    /* word */
0185 #define VT1724_MT_MONITOR_PEAKINDEX 0x3e    /* byte */
0186 #define VT1724_MT_MONITOR_PEAKDATA  0x3f    /* byte */
0187
0188 /* concurrent stereo channels */
0189 #define VT1724_MT_PDMA4_ADDR        0x40    /* dword */
0190 #define VT1724_MT_PDMA4_SIZE        0x44    /* word */
0191 #define VT1724_MT_PDMA4_COUNT       0x46    /* word */
0192 #define VT1724_MT_PDMA3_ADDR        0x50    /* dword */
0193 #define VT1724_MT_PDMA3_SIZE        0x54    /* word */
0194 #define VT1724_MT_PDMA3_COUNT       0x56    /* word */
0195 #define VT1724_MT_PDMA2_ADDR        0x60    /* dword */
0196 #define VT1724_MT_PDMA2_SIZE        0x64    /* word */
0197 #define VT1724_MT_PDMA2_COUNT       0x66    /* word */
0198 #define VT1724_MT_PDMA1_ADDR        0x70    /* dword */
0199 #define VT1724_MT_PDMA1_SIZE        0x74    /* word */
0200 #define VT1724_MT_PDMA1_COUNT       0x76    /* word */
0201
0202
0203 unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr);
0204 void snd_vt1724_write_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr, unsigned char data);
0205
0206 #endif /* __SOUND_VT1724_H */