pci/hda/patch_si3054.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Universal Interface for Intel High Definition Audio Codec
0004  *
0005  * HD audio interface patch for Silicon Labs 3054/5 modem codec
0006  *
0007  * Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org>
0008  *                    Takashi Iwai <tiwai@suse.de>
0009  */
0010
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/slab.h>
0014 #include <linux/module.h>
0015 #include <sound/core.h>
0016 #include <sound/hda_codec.h>
0017 #include "hda_local.h"
0018
0019 /* si3054 verbs */
0020 #define SI3054_VERB_READ_NODE  0x900
0021 #define SI3054_VERB_WRITE_NODE 0x100
0022
0023 /* si3054 nodes (registers) */
0024 #define SI3054_EXTENDED_MID    2
0025 #define SI3054_LINE_RATE       3
0026 #define SI3054_LINE_LEVEL      4
0027 #define SI3054_GPIO_CFG        5
0028 #define SI3054_GPIO_POLARITY   6
0029 #define SI3054_GPIO_STICKY     7
0030 #define SI3054_GPIO_WAKEUP     8
0031 #define SI3054_GPIO_STATUS     9
0032 #define SI3054_GPIO_CONTROL   10
0033 #define SI3054_MISC_AFE       11
0034 #define SI3054_CHIPID         12
0035 #define SI3054_LINE_CFG1      13
0036 #define SI3054_LINE_STATUS    14
0037 #define SI3054_DC_TERMINATION 15
0038 #define SI3054_LINE_CONFIG    16
0039 #define SI3054_CALLPROG_ATT   17
0040 #define SI3054_SQ_CONTROL     18
0041 #define SI3054_MISC_CONTROL   19
0042 #define SI3054_RING_CTRL1     20
0043 #define SI3054_RING_CTRL2     21
0044
0045 /* extended MID */
0046 #define SI3054_MEI_READY 0xf
0047
0048 /* line level */
0049 #define SI3054_ATAG_MASK 0x00f0
0050 #define SI3054_DTAG_MASK 0xf000
0051
0052 /* GPIO bits */
0053 #define SI3054_GPIO_OH    0x0001
0054 #define SI3054_GPIO_CID   0x0002
0055
0056 /* chipid and revisions */
0057 #define SI3054_CHIPID_CODEC_REV_MASK 0x000f
0058 #define SI3054_CHIPID_DAA_REV_MASK   0x00f0
0059 #define SI3054_CHIPID_INTERNATIONAL  0x0100
0060 #define SI3054_CHIPID_DAA_ID         0x0f00
0061 #define SI3054_CHIPID_CODEC_ID      (1<<12)
0062
0063 /* si3054 codec registers (nodes) access macros */
0064 #define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0))
0065 #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val))
0066 #define SET_REG_CACHE(codec,reg,val) \
0067     snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val)
0068
0069
0070 struct si3054_spec {
0071     unsigned international;
0072 };
0073
0074
0075 /*
0076  * Modem mixer
0077  */
0078
0079 #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff))
0080 #define PRIVATE_REG(val) ((val>>16)&0xffff)
0081 #define PRIVATE_MASK(val) (val&0xffff)
0082
0083 #define si3054_switch_info  snd_ctl_boolean_mono_info
0084
0085 static int si3054_switch_get(struct snd_kcontrol *kcontrol,
0086                        struct snd_ctl_elem_value *uvalue)
0087 {
0088     struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
0089     u16 reg  = PRIVATE_REG(kcontrol->private_value);
0090     u16 mask = PRIVATE_MASK(kcontrol->private_value);
0091     uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ;
0092     return 0;
0093 }
0094
0095 static int si3054_switch_put(struct snd_kcontrol *kcontrol,
0096                        struct snd_ctl_elem_value *uvalue)
0097 {
0098     struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
0099     u16 reg  = PRIVATE_REG(kcontrol->private_value);
0100     u16 mask = PRIVATE_MASK(kcontrol->private_value);
0101     if (uvalue->value.integer.value[0])
0102         SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask);
0103     else
0104         SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask);
0105     return 0;
0106 }
0107
0108 #define SI3054_KCONTROL(kname,reg,mask) { \
0109     .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
0110     .name = kname, \
0111     .subdevice = HDA_SUBDEV_NID_FLAG | reg, \
0112     .info = si3054_switch_info, \
0113     .get  = si3054_switch_get, \
0114     .put  = si3054_switch_put, \
0115     .private_value = PRIVATE_VALUE(reg,mask), \
0116 }
0117
0118
0119 static const struct snd_kcontrol_new si3054_modem_mixer[] = {
0120     SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH),
0121     SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID),
0122     {}
0123 };
0124
0125 static int si3054_build_controls(struct hda_codec *codec)
0126 {
0127     return snd_hda_add_new_ctls(codec, si3054_modem_mixer);
0128 }
0129
0130
0131 /*
0132  * PCM callbacks
0133  */
0134
0135 static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo,
0136                   struct hda_codec *codec,
0137                   unsigned int stream_tag,
0138                   unsigned int format,
0139                   struct snd_pcm_substream *substream)
0140 {
0141     u16 val;
0142
0143     SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
0144     val = GET_REG(codec, SI3054_LINE_LEVEL);
0145     val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK));
0146     val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
0147     SET_REG(codec, SI3054_LINE_LEVEL, val);
0148
0149     snd_hda_codec_setup_stream(codec, hinfo->nid,
0150                    stream_tag, 0, format);
0151     return 0;
0152 }
0153
0154 static int si3054_pcm_open(struct hda_pcm_stream *hinfo,
0155                struct hda_codec *codec,
0156                 struct snd_pcm_substream *substream)
0157 {
0158     static const unsigned int rates[] = { 8000, 9600, 16000 };
0159     static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
0160         .count = ARRAY_SIZE(rates),
0161         .list = rates,
0162         .mask = 0,
0163     };
0164     substream->runtime->hw.period_bytes_min = 80;
0165     return snd_pcm_hw_constraint_list(substream->runtime, 0,
0166             SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
0167 }
0168
0169
0170 static const struct hda_pcm_stream si3054_pcm = {
0171     .substreams = 1,
0172     .channels_min = 1,
0173     .channels_max = 1,
0174     .nid = 0x1,
0175     .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT,
0176     .formats = SNDRV_PCM_FMTBIT_S16_LE,
0177     .maxbps = 16,
0178     .ops = {
0179         .open = si3054_pcm_open,
0180         .prepare = si3054_pcm_prepare,
0181     },
0182 };
0183
0184
0185 static int si3054_build_pcms(struct hda_codec *codec)
0186 {
0187     struct hda_pcm *info;
0188
0189     info = snd_hda_codec_pcm_new(codec, "Si3054 Modem");
0190     if (!info)
0191         return -ENOMEM;
0192     info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm;
0193     info->stream[SNDRV_PCM_STREAM_CAPTURE]  = si3054_pcm;
0194     info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = codec->core.mfg;
0195     info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = codec->core.mfg;
0196     info->pcm_type = HDA_PCM_TYPE_MODEM;
0197     return 0;
0198 }
0199
0200
0201 /*
0202  * Init part
0203  */
0204
0205 static int si3054_init(struct hda_codec *codec)
0206 {
0207     struct si3054_spec *spec = codec->spec;
0208     unsigned wait_count;
0209     u16 val;
0210
0211     if (snd_hdac_regmap_add_vendor_verb(&codec->core,
0212                         SI3054_VERB_WRITE_NODE))
0213         return -ENOMEM;
0214
0215     snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0);
0216     snd_hda_codec_write(codec, codec->core.mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0);
0217     SET_REG(codec, SI3054_LINE_RATE, 9600);
0218     SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
0219     SET_REG(codec, SI3054_EXTENDED_MID, 0);
0220
0221     wait_count = 10;
0222     do {
0223         msleep(2);
0224         val = GET_REG(codec, SI3054_EXTENDED_MID);
0225     } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--);
0226
0227     if((val&SI3054_MEI_READY) != SI3054_MEI_READY) {
0228         codec_err(codec, "si3054: cannot initialize. EXT MID = %04x\n", val);
0229         /* let's pray that this is no fatal error */
0230         /* return -EACCES; */
0231     }
0232
0233     SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
0234     SET_REG(codec, SI3054_GPIO_CFG, 0x0);
0235     SET_REG(codec, SI3054_MISC_AFE, 0);
0236     SET_REG(codec, SI3054_LINE_CFG1,0x200);
0237
0238     if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) {
0239         codec_dbg(codec,
0240               "Link Frame Detect(FDT) is not ready (line status: %04x)\n",
0241                 GET_REG(codec,SI3054_LINE_STATUS));
0242     }
0243
0244     spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL;
0245
0246     return 0;
0247 }
0248
0249 static void si3054_free(struct hda_codec *codec)
0250 {
0251     kfree(codec->spec);
0252 }
0253
0254
0255 /*
0256  */
0257
0258 static const struct hda_codec_ops si3054_patch_ops = {
0259     .build_controls = si3054_build_controls,
0260     .build_pcms = si3054_build_pcms,
0261     .init = si3054_init,
0262     .free = si3054_free,
0263 };
0264
0265 static int patch_si3054(struct hda_codec *codec)
0266 {
0267     struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL);
0268     if (spec == NULL)
0269         return -ENOMEM;
0270     codec->spec = spec;
0271     codec->patch_ops = si3054_patch_ops;
0272     return 0;
0273 }
0274
0275 /*
0276  * patch entries
0277  */
0278 static const struct hda_device_id snd_hda_id_si3054[] = {
0279     HDA_CODEC_ENTRY(0x163c3055, "Si3054", patch_si3054),
0280     HDA_CODEC_ENTRY(0x163c3155, "Si3054", patch_si3054),
0281     HDA_CODEC_ENTRY(0x11c13026, "Si3054", patch_si3054),
0282     HDA_CODEC_ENTRY(0x11c13055, "Si3054", patch_si3054),
0283     HDA_CODEC_ENTRY(0x11c13155, "Si3054", patch_si3054),
0284     HDA_CODEC_ENTRY(0x10573055, "Si3054", patch_si3054),
0285     HDA_CODEC_ENTRY(0x10573057, "Si3054", patch_si3054),
0286     HDA_CODEC_ENTRY(0x10573155, "Si3054", patch_si3054),
0287     /* VIA HDA on Clevo m540 */
0288     HDA_CODEC_ENTRY(0x11063288, "Si3054", patch_si3054),
0289     /* Asus A8J Modem (SM56) */
0290     HDA_CODEC_ENTRY(0x15433155, "Si3054", patch_si3054),
0291     /* LG LW20 modem */
0292     HDA_CODEC_ENTRY(0x18540018, "Si3054", patch_si3054),
0293     {}
0294 };
0295 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_si3054);
0296
0297 MODULE_LICENSE("GPL");
0298 MODULE_DESCRIPTION("Si3054 HD-audio modem codec");
0299
0300 static struct hda_codec_driver si3054_driver = {
0301     .id = snd_hda_id_si3054,
0302 };
0303
0304 module_hda_codec_driver(si3054_driver);