pci/hda/patch_cs8409.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
0004  *
0005  * Copyright (C) 2021 Cirrus Logic, Inc. and
0006  *                    Cirrus Logic International Semiconductor Ltd.
0007  */
0008
0009 #ifndef __CS8409_PATCH_H
0010 #define __CS8409_PATCH_H
0011
0012 #include <linux/pci.h>
0013 #include <sound/tlv.h>
0014 #include <linux/workqueue.h>
0015 #include <sound/cs42l42.h>
0016 #include <sound/hda_codec.h>
0017 #include "hda_local.h"
0018 #include "hda_auto_parser.h"
0019 #include "hda_jack.h"
0020 #include "hda_generic.h"
0021
0022 /* CS8409 Specific Definitions */
0023
0024 enum cs8409_pins {
0025     CS8409_PIN_ROOT,
0026     CS8409_PIN_AFG,
0027     CS8409_PIN_ASP1_OUT_A,
0028     CS8409_PIN_ASP1_OUT_B,
0029     CS8409_PIN_ASP1_OUT_C,
0030     CS8409_PIN_ASP1_OUT_D,
0031     CS8409_PIN_ASP1_OUT_E,
0032     CS8409_PIN_ASP1_OUT_F,
0033     CS8409_PIN_ASP1_OUT_G,
0034     CS8409_PIN_ASP1_OUT_H,
0035     CS8409_PIN_ASP2_OUT_A,
0036     CS8409_PIN_ASP2_OUT_B,
0037     CS8409_PIN_ASP2_OUT_C,
0038     CS8409_PIN_ASP2_OUT_D,
0039     CS8409_PIN_ASP2_OUT_E,
0040     CS8409_PIN_ASP2_OUT_F,
0041     CS8409_PIN_ASP2_OUT_G,
0042     CS8409_PIN_ASP2_OUT_H,
0043     CS8409_PIN_ASP1_IN_A,
0044     CS8409_PIN_ASP1_IN_B,
0045     CS8409_PIN_ASP1_IN_C,
0046     CS8409_PIN_ASP1_IN_D,
0047     CS8409_PIN_ASP1_IN_E,
0048     CS8409_PIN_ASP1_IN_F,
0049     CS8409_PIN_ASP1_IN_G,
0050     CS8409_PIN_ASP1_IN_H,
0051     CS8409_PIN_ASP2_IN_A,
0052     CS8409_PIN_ASP2_IN_B,
0053     CS8409_PIN_ASP2_IN_C,
0054     CS8409_PIN_ASP2_IN_D,
0055     CS8409_PIN_ASP2_IN_E,
0056     CS8409_PIN_ASP2_IN_F,
0057     CS8409_PIN_ASP2_IN_G,
0058     CS8409_PIN_ASP2_IN_H,
0059     CS8409_PIN_DMIC1,
0060     CS8409_PIN_DMIC2,
0061     CS8409_PIN_ASP1_TRANSMITTER_A,
0062     CS8409_PIN_ASP1_TRANSMITTER_B,
0063     CS8409_PIN_ASP1_TRANSMITTER_C,
0064     CS8409_PIN_ASP1_TRANSMITTER_D,
0065     CS8409_PIN_ASP1_TRANSMITTER_E,
0066     CS8409_PIN_ASP1_TRANSMITTER_F,
0067     CS8409_PIN_ASP1_TRANSMITTER_G,
0068     CS8409_PIN_ASP1_TRANSMITTER_H,
0069     CS8409_PIN_ASP2_TRANSMITTER_A,
0070     CS8409_PIN_ASP2_TRANSMITTER_B,
0071     CS8409_PIN_ASP2_TRANSMITTER_C,
0072     CS8409_PIN_ASP2_TRANSMITTER_D,
0073     CS8409_PIN_ASP2_TRANSMITTER_E,
0074     CS8409_PIN_ASP2_TRANSMITTER_F,
0075     CS8409_PIN_ASP2_TRANSMITTER_G,
0076     CS8409_PIN_ASP2_TRANSMITTER_H,
0077     CS8409_PIN_ASP1_RECEIVER_A,
0078     CS8409_PIN_ASP1_RECEIVER_B,
0079     CS8409_PIN_ASP1_RECEIVER_C,
0080     CS8409_PIN_ASP1_RECEIVER_D,
0081     CS8409_PIN_ASP1_RECEIVER_E,
0082     CS8409_PIN_ASP1_RECEIVER_F,
0083     CS8409_PIN_ASP1_RECEIVER_G,
0084     CS8409_PIN_ASP1_RECEIVER_H,
0085     CS8409_PIN_ASP2_RECEIVER_A,
0086     CS8409_PIN_ASP2_RECEIVER_B,
0087     CS8409_PIN_ASP2_RECEIVER_C,
0088     CS8409_PIN_ASP2_RECEIVER_D,
0089     CS8409_PIN_ASP2_RECEIVER_E,
0090     CS8409_PIN_ASP2_RECEIVER_F,
0091     CS8409_PIN_ASP2_RECEIVER_G,
0092     CS8409_PIN_ASP2_RECEIVER_H,
0093     CS8409_PIN_DMIC1_IN,
0094     CS8409_PIN_DMIC2_IN,
0095     CS8409_PIN_BEEP_GEN,
0096     CS8409_PIN_VENDOR_WIDGET
0097 };
0098
0099 enum cs8409_coefficient_index_registers {
0100     CS8409_DEV_CFG1,
0101     CS8409_DEV_CFG2,
0102     CS8409_DEV_CFG3,
0103     CS8409_ASP1_CLK_CTRL1,
0104     CS8409_ASP1_CLK_CTRL2,
0105     CS8409_ASP1_CLK_CTRL3,
0106     CS8409_ASP2_CLK_CTRL1,
0107     CS8409_ASP2_CLK_CTRL2,
0108     CS8409_ASP2_CLK_CTRL3,
0109     CS8409_DMIC_CFG,
0110     CS8409_BEEP_CFG,
0111     ASP1_RX_NULL_INS_RMV,
0112     ASP1_Rx_RATE1,
0113     ASP1_Rx_RATE2,
0114     ASP1_Tx_NULL_INS_RMV,
0115     ASP1_Tx_RATE1,
0116     ASP1_Tx_RATE2,
0117     ASP2_Rx_NULL_INS_RMV,
0118     ASP2_Rx_RATE1,
0119     ASP2_Rx_RATE2,
0120     ASP2_Tx_NULL_INS_RMV,
0121     ASP2_Tx_RATE1,
0122     ASP2_Tx_RATE2,
0123     ASP1_SYNC_CTRL,
0124     ASP2_SYNC_CTRL,
0125     ASP1_A_TX_CTRL1,
0126     ASP1_A_TX_CTRL2,
0127     ASP1_B_TX_CTRL1,
0128     ASP1_B_TX_CTRL2,
0129     ASP1_C_TX_CTRL1,
0130     ASP1_C_TX_CTRL2,
0131     ASP1_D_TX_CTRL1,
0132     ASP1_D_TX_CTRL2,
0133     ASP1_E_TX_CTRL1,
0134     ASP1_E_TX_CTRL2,
0135     ASP1_F_TX_CTRL1,
0136     ASP1_F_TX_CTRL2,
0137     ASP1_G_TX_CTRL1,
0138     ASP1_G_TX_CTRL2,
0139     ASP1_H_TX_CTRL1,
0140     ASP1_H_TX_CTRL2,
0141     ASP2_A_TX_CTRL1,
0142     ASP2_A_TX_CTRL2,
0143     ASP2_B_TX_CTRL1,
0144     ASP2_B_TX_CTRL2,
0145     ASP2_C_TX_CTRL1,
0146     ASP2_C_TX_CTRL2,
0147     ASP2_D_TX_CTRL1,
0148     ASP2_D_TX_CTRL2,
0149     ASP2_E_TX_CTRL1,
0150     ASP2_E_TX_CTRL2,
0151     ASP2_F_TX_CTRL1,
0152     ASP2_F_TX_CTRL2,
0153     ASP2_G_TX_CTRL1,
0154     ASP2_G_TX_CTRL2,
0155     ASP2_H_TX_CTRL1,
0156     ASP2_H_TX_CTRL2,
0157     ASP1_A_RX_CTRL1,
0158     ASP1_A_RX_CTRL2,
0159     ASP1_B_RX_CTRL1,
0160     ASP1_B_RX_CTRL2,
0161     ASP1_C_RX_CTRL1,
0162     ASP1_C_RX_CTRL2,
0163     ASP1_D_RX_CTRL1,
0164     ASP1_D_RX_CTRL2,
0165     ASP1_E_RX_CTRL1,
0166     ASP1_E_RX_CTRL2,
0167     ASP1_F_RX_CTRL1,
0168     ASP1_F_RX_CTRL2,
0169     ASP1_G_RX_CTRL1,
0170     ASP1_G_RX_CTRL2,
0171     ASP1_H_RX_CTRL1,
0172     ASP1_H_RX_CTRL2,
0173     ASP2_A_RX_CTRL1,
0174     ASP2_A_RX_CTRL2,
0175     ASP2_B_RX_CTRL1,
0176     ASP2_B_RX_CTRL2,
0177     ASP2_C_RX_CTRL1,
0178     ASP2_C_RX_CTRL2,
0179     ASP2_D_RX_CTRL1,
0180     ASP2_D_RX_CTRL2,
0181     ASP2_E_RX_CTRL1,
0182     ASP2_E_RX_CTRL2,
0183     ASP2_F_RX_CTRL1,
0184     ASP2_F_RX_CTRL2,
0185     ASP2_G_RX_CTRL1,
0186     ASP2_G_RX_CTRL2,
0187     ASP2_H_RX_CTRL1,
0188     ASP2_H_RX_CTRL2,
0189     CS8409_I2C_ADDR,
0190     CS8409_I2C_DATA,
0191     CS8409_I2C_CTRL,
0192     CS8409_I2C_STS,
0193     CS8409_I2C_QWRITE,
0194     CS8409_I2C_QREAD,
0195     CS8409_SPI_CTRL,
0196     CS8409_SPI_TX_DATA,
0197     CS8409_SPI_RX_DATA,
0198     CS8409_SPI_STS,
0199     CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/
0200     CS8409_PFE_COEF_W2,
0201     CS8409_PFE_CTRL1,
0202     CS8409_PFE_CTRL2,
0203     CS8409_PRE_SCALE_ATTN1,
0204     CS8409_PRE_SCALE_ATTN2,
0205     CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/
0206     CS8409_PFE_COEF_MON2,
0207     CS8409_ASP1_INTRN_STS,
0208     CS8409_ASP2_INTRN_STS,
0209     CS8409_ASP1_RX_SCLK_COUNT,
0210     CS8409_ASP1_TX_SCLK_COUNT,
0211     CS8409_ASP2_RX_SCLK_COUNT,
0212     CS8409_ASP2_TX_SCLK_COUNT,
0213     CS8409_ASP_UNS_RESP_MASK,
0214     CS8409_LOOPBACK_CTRL = 0x80,
0215     CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */
0216 };
0217
0218 /* CS42L42 Specific Definitions */
0219
0220 #define CS8409_MAX_CODECS           8
0221 #define CS42L42_VOLUMES             (4U)
0222 #define CS42L42_HP_VOL_REAL_MIN         (-63)
0223 #define CS42L42_HP_VOL_REAL_MAX         (0)
0224 #define CS42L42_AMIC_VOL_REAL_MIN       (-97)
0225 #define CS42L42_AMIC_VOL_REAL_MAX       (12)
0226 #define CS42L42_REG_AMIC_VOL_MASK       (0x00FF)
0227 #define CS42L42_HSTYPE_MASK         (0x03)
0228 #define CS42L42_I2C_TIMEOUT_US          (20000)
0229 #define CS42L42_I2C_SLEEP_US            (2000)
0230 #define CS42L42_PDN_TIMEOUT_US          (250000)
0231 #define CS42L42_PDN_SLEEP_US            (2000)
0232 #define CS42L42_FULL_SCALE_VOL_MASK     (2)
0233 #define CS42L42_FULL_SCALE_VOL_0DB      (1)
0234 #define CS42L42_FULL_SCALE_VOL_MINUS6DB     (0)
0235
0236 /* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */
0237
0238 #define CS42L42_I2C_ADDR            (0x48 << 1)
0239 #define CS8409_CS42L42_RESET            GENMASK(5, 5) /* CS8409_GPIO5 */
0240 #define CS8409_CS42L42_INT          GENMASK(4, 4) /* CS8409_GPIO4 */
0241 #define CS8409_CYBORG_SPEAKER_PDN       GENMASK(2, 2) /* CS8409_GPIO2 */
0242 #define CS8409_WARLOCK_SPEAKER_PDN      GENMASK(1, 1) /* CS8409_GPIO1 */
0243 #define CS8409_CS42L42_HP_PIN_NID       CS8409_PIN_ASP1_TRANSMITTER_A
0244 #define CS8409_CS42L42_SPK_PIN_NID      CS8409_PIN_ASP2_TRANSMITTER_A
0245 #define CS8409_CS42L42_AMIC_PIN_NID     CS8409_PIN_ASP1_RECEIVER_A
0246 #define CS8409_CS42L42_DMIC_PIN_NID     CS8409_PIN_DMIC1_IN
0247 #define CS8409_CS42L42_DMIC_ADC_PIN_NID     CS8409_PIN_DMIC1
0248
0249 /* Dolphin */
0250
0251 #define DOLPHIN_C0_I2C_ADDR         (0x48 << 1)
0252 #define DOLPHIN_C1_I2C_ADDR         (0x49 << 1)
0253 #define DOLPHIN_HP_PIN_NID          CS8409_PIN_ASP1_TRANSMITTER_A
0254 #define DOLPHIN_LO_PIN_NID          CS8409_PIN_ASP1_TRANSMITTER_B
0255 #define DOLPHIN_AMIC_PIN_NID            CS8409_PIN_ASP1_RECEIVER_A
0256
0257 #define DOLPHIN_C0_INT              GENMASK(4, 4)
0258 #define DOLPHIN_C1_INT              GENMASK(0, 0)
0259 #define DOLPHIN_C0_RESET            GENMASK(5, 5)
0260 #define DOLPHIN_C1_RESET            GENMASK(1, 1)
0261 #define DOLPHIN_WAKE                (DOLPHIN_C0_INT | DOLPHIN_C1_INT)
0262
0263 enum {
0264     CS8409_BULLSEYE,
0265     CS8409_WARLOCK,
0266     CS8409_WARLOCK_MLK,
0267     CS8409_WARLOCK_MLK_DUAL_MIC,
0268     CS8409_CYBORG,
0269     CS8409_FIXUPS,
0270     CS8409_DOLPHIN,
0271     CS8409_DOLPHIN_FIXUPS,
0272     CS8409_ODIN,
0273 };
0274
0275 enum {
0276     CS8409_CODEC0,
0277     CS8409_CODEC1
0278 };
0279
0280 enum {
0281     CS42L42_VOL_ADC,
0282     CS42L42_VOL_DAC,
0283 };
0284
0285 #define CS42L42_ADC_VOL_OFFSET          (CS42L42_VOL_ADC)
0286 #define CS42L42_DAC_CH0_VOL_OFFSET      (CS42L42_VOL_DAC)
0287 #define CS42L42_DAC_CH1_VOL_OFFSET      (CS42L42_VOL_DAC + 1)
0288
0289 struct cs8409_i2c_param {
0290     unsigned int addr;
0291     unsigned int value;
0292 };
0293
0294 struct cs8409_cir_param {
0295     unsigned int nid;
0296     unsigned int cir;
0297     unsigned int coeff;
0298 };
0299
0300 struct sub_codec {
0301     struct hda_codec *codec;
0302     unsigned int addr;
0303     unsigned int reset_gpio;
0304     unsigned int irq_mask;
0305     const struct cs8409_i2c_param *init_seq;
0306     unsigned int init_seq_num;
0307
0308     unsigned int hp_jack_in:1;
0309     unsigned int mic_jack_in:1;
0310     unsigned int suspended:1;
0311     unsigned int paged:1;
0312     unsigned int last_page;
0313     unsigned int hsbias_hiz;
0314     unsigned int full_scale_vol:1;
0315     unsigned int no_type_dect:1;
0316
0317     s8 vol[CS42L42_VOLUMES];
0318 };
0319
0320 struct cs8409_spec {
0321     struct hda_gen_spec gen;
0322     struct hda_codec *codec;
0323
0324     struct sub_codec *scodecs[CS8409_MAX_CODECS];
0325     unsigned int num_scodecs;
0326
0327     unsigned int gpio_mask;
0328     unsigned int gpio_dir;
0329     unsigned int gpio_data;
0330
0331     int speaker_pdn_gpio;
0332
0333     struct mutex i2c_mux;
0334     unsigned int i2c_clck_enabled;
0335     unsigned int dev_addr;
0336     struct delayed_work i2c_clk_work;
0337
0338     unsigned int playback_started:1;
0339     unsigned int capture_started:1;
0340     unsigned int init_done:1;
0341     unsigned int build_ctrl_done:1;
0342
0343     /* verb exec op override */
0344     int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
0345              unsigned int *res);
0346 };
0347
0348 extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer;
0349 extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer;
0350
0351 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo);
0352 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
0353 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
0354
0355 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback;
0356 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture;
0357 extern const struct snd_pci_quirk cs8409_fixup_tbl[];
0358 extern const struct hda_model_fixup cs8409_models[];
0359 extern const struct hda_fixup cs8409_fixups[];
0360 extern const struct hda_verb cs8409_cs42l42_init_verbs[];
0361 extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[];
0362 extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[];
0363 extern struct sub_codec cs8409_cs42l42_codec;
0364
0365 extern const struct hda_verb dolphin_init_verbs[];
0366 extern const struct cs8409_cir_param dolphin_hw_cfg[];
0367 extern struct sub_codec dolphin_cs42l42_0;
0368 extern struct sub_codec dolphin_cs42l42_1;
0369
0370 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
0371 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
0372
0373 #endif