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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
0004  *
0005  * Copyright (C) 2021 Cirrus Logic, Inc. and
0006  *                    Cirrus Logic International Semiconductor Ltd.
0007  */
0008 
0009 #include <linux/init.h>
0010 #include <linux/slab.h>
0011 #include <linux/module.h>
0012 #include <sound/core.h>
0013 #include <linux/mutex.h>
0014 #include <linux/iopoll.h>
0015 
0016 #include "patch_cs8409.h"
0017 
0018 /******************************************************************************
0019  *                        CS8409 Specific Functions
0020  ******************************************************************************/
0021 
0022 static int cs8409_parse_auto_config(struct hda_codec *codec)
0023 {
0024     struct cs8409_spec *spec = codec->spec;
0025     int err;
0026     int i;
0027 
0028     err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
0029     if (err < 0)
0030         return err;
0031 
0032     err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
0033     if (err < 0)
0034         return err;
0035 
0036     /* keep the ADCs powered up when it's dynamically switchable */
0037     if (spec->gen.dyn_adc_switch) {
0038         unsigned int done = 0;
0039 
0040         for (i = 0; i < spec->gen.input_mux.num_items; i++) {
0041             int idx = spec->gen.dyn_adc_idx[i];
0042 
0043             if (done & (1 << idx))
0044                 continue;
0045             snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
0046             done |= 1 << idx;
0047         }
0048     }
0049 
0050     return 0;
0051 }
0052 
0053 static void cs8409_disable_i2c_clock_worker(struct work_struct *work);
0054 
0055 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
0056 {
0057     struct cs8409_spec *spec;
0058 
0059     spec = kzalloc(sizeof(*spec), GFP_KERNEL);
0060     if (!spec)
0061         return NULL;
0062     codec->spec = spec;
0063     spec->codec = codec;
0064     codec->power_save_node = 1;
0065     mutex_init(&spec->i2c_mux);
0066     INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
0067     snd_hda_gen_spec_init(&spec->gen);
0068 
0069     return spec;
0070 }
0071 
0072 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
0073 {
0074     snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
0075     return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
0076 }
0077 
0078 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
0079                       unsigned int coef)
0080 {
0081     snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
0082     snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
0083 }
0084 
0085 /*
0086  * cs8409_enable_i2c_clock - Disable I2C clocks
0087  * @codec: the codec instance
0088  * Disable I2C clocks.
0089  * This must be called when the i2c mutex is unlocked.
0090  */
0091 static void cs8409_disable_i2c_clock(struct hda_codec *codec)
0092 {
0093     struct cs8409_spec *spec = codec->spec;
0094 
0095     mutex_lock(&spec->i2c_mux);
0096     if (spec->i2c_clck_enabled) {
0097         cs8409_vendor_coef_set(spec->codec, 0x0,
0098                    cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
0099         spec->i2c_clck_enabled = 0;
0100     }
0101     mutex_unlock(&spec->i2c_mux);
0102 }
0103 
0104 /*
0105  * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
0106  */
0107 static void cs8409_disable_i2c_clock_worker(struct work_struct *work)
0108 {
0109     struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work);
0110 
0111     cs8409_disable_i2c_clock(spec->codec);
0112 }
0113 
0114 /*
0115  * cs8409_enable_i2c_clock - Enable I2C clocks
0116  * @codec: the codec instance
0117  * Enable I2C clocks.
0118  * This must be called when the i2c mutex is locked.
0119  */
0120 static void cs8409_enable_i2c_clock(struct hda_codec *codec)
0121 {
0122     struct cs8409_spec *spec = codec->spec;
0123 
0124     /* Cancel the disable timer, but do not wait for any running disable functions to finish.
0125      * If the disable timer runs out before cancel, the delayed work thread will be blocked,
0126      * waiting for the mutex to become unlocked. This mutex will be locked for the duration of
0127      * any i2c transaction, so the disable function will run to completion immediately
0128      * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
0129      */
0130     cancel_delayed_work(&spec->i2c_clk_work);
0131 
0132     if (!spec->i2c_clck_enabled) {
0133         cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
0134         spec->i2c_clck_enabled = 1;
0135     }
0136     queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
0137 }
0138 
0139 /**
0140  * cs8409_i2c_wait_complete - Wait for I2C transaction
0141  * @codec: the codec instance
0142  *
0143  * Wait for I2C transaction to complete.
0144  * Return -ETIMEDOUT if transaction wait times out.
0145  */
0146 static int cs8409_i2c_wait_complete(struct hda_codec *codec)
0147 {
0148     unsigned int retval;
0149 
0150     return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18,
0151         CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS);
0152 }
0153 
0154 /**
0155  * cs8409_set_i2c_dev_addr - Set i2c address for transaction
0156  * @codec: the codec instance
0157  * @addr: I2C Address
0158  */
0159 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
0160 {
0161     struct cs8409_spec *spec = codec->spec;
0162 
0163     if (spec->dev_addr != addr) {
0164         cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
0165         spec->dev_addr = addr;
0166     }
0167 }
0168 
0169 /**
0170  * cs8409_i2c_set_page - CS8409 I2C set page register.
0171  * @scodec: the codec instance
0172  * @i2c_reg: Page register
0173  *
0174  * Returns negative on error.
0175  */
0176 static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg)
0177 {
0178     struct hda_codec *codec = scodec->codec;
0179 
0180     if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
0181         cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
0182         if (cs8409_i2c_wait_complete(codec) < 0)
0183             return -EIO;
0184         scodec->last_page = i2c_reg >> 8;
0185     }
0186 
0187     return 0;
0188 }
0189 
0190 /**
0191  * cs8409_i2c_read - CS8409 I2C Read.
0192  * @scodec: the codec instance
0193  * @addr: Register to read
0194  *
0195  * Returns negative on error, otherwise returns read value in bits 0-7.
0196  */
0197 static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr)
0198 {
0199     struct hda_codec *codec = scodec->codec;
0200     struct cs8409_spec *spec = codec->spec;
0201     unsigned int i2c_reg_data;
0202     unsigned int read_data;
0203 
0204     if (scodec->suspended)
0205         return -EPERM;
0206 
0207     mutex_lock(&spec->i2c_mux);
0208     cs8409_enable_i2c_clock(codec);
0209     cs8409_set_i2c_dev_addr(codec, scodec->addr);
0210 
0211     if (cs8409_i2c_set_page(scodec, addr))
0212         goto error;
0213 
0214     i2c_reg_data = (addr << 8) & 0x0ffff;
0215     cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
0216     if (cs8409_i2c_wait_complete(codec) < 0)
0217         goto error;
0218 
0219     /* Register in bits 15-8 and the data in 7-0 */
0220     read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
0221 
0222     mutex_unlock(&spec->i2c_mux);
0223 
0224     return read_data & 0x0ff;
0225 
0226 error:
0227     mutex_unlock(&spec->i2c_mux);
0228     codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
0229     return -EIO;
0230 }
0231 
0232 /**
0233  * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
0234  * @scodec: the codec instance
0235  * @seq: Register Sequence to read
0236  * @count: Number of registeres to read
0237  *
0238  * Returns negative on error, values are read into value element of cs8409_i2c_param sequence.
0239  */
0240 static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count)
0241 {
0242     struct hda_codec *codec = scodec->codec;
0243     struct cs8409_spec *spec = codec->spec;
0244     unsigned int i2c_reg_data;
0245     int i;
0246 
0247     if (scodec->suspended)
0248         return -EPERM;
0249 
0250     mutex_lock(&spec->i2c_mux);
0251     cs8409_set_i2c_dev_addr(codec, scodec->addr);
0252 
0253     for (i = 0; i < count; i++) {
0254         cs8409_enable_i2c_clock(codec);
0255         if (cs8409_i2c_set_page(scodec, seq[i].addr))
0256             goto error;
0257 
0258         i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
0259         cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
0260 
0261         if (cs8409_i2c_wait_complete(codec) < 0)
0262             goto error;
0263 
0264         seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
0265     }
0266 
0267     mutex_unlock(&spec->i2c_mux);
0268 
0269     return 0;
0270 
0271 error:
0272     mutex_unlock(&spec->i2c_mux);
0273     codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
0274     return -EIO;
0275 }
0276 
0277 /**
0278  * cs8409_i2c_write - CS8409 I2C Write.
0279  * @scodec: the codec instance
0280  * @addr: Register to write to
0281  * @value: Data to write
0282  *
0283  * Returns negative on error, otherwise returns 0.
0284  */
0285 static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value)
0286 {
0287     struct hda_codec *codec = scodec->codec;
0288     struct cs8409_spec *spec = codec->spec;
0289     unsigned int i2c_reg_data;
0290 
0291     if (scodec->suspended)
0292         return -EPERM;
0293 
0294     mutex_lock(&spec->i2c_mux);
0295 
0296     cs8409_enable_i2c_clock(codec);
0297     cs8409_set_i2c_dev_addr(codec, scodec->addr);
0298 
0299     if (cs8409_i2c_set_page(scodec, addr))
0300         goto error;
0301 
0302     i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
0303     cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
0304 
0305     if (cs8409_i2c_wait_complete(codec) < 0)
0306         goto error;
0307 
0308     mutex_unlock(&spec->i2c_mux);
0309     return 0;
0310 
0311 error:
0312     mutex_unlock(&spec->i2c_mux);
0313     codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
0314     return -EIO;
0315 }
0316 
0317 /**
0318  * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
0319  * @scodec: the codec instance
0320  * @seq: Register Sequence to write
0321  * @count: Number of registeres to write
0322  *
0323  * Returns negative on error.
0324  */
0325 static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq,
0326                  int count)
0327 {
0328     struct hda_codec *codec = scodec->codec;
0329     struct cs8409_spec *spec = codec->spec;
0330     unsigned int i2c_reg_data;
0331     int i;
0332 
0333     if (scodec->suspended)
0334         return -EPERM;
0335 
0336     mutex_lock(&spec->i2c_mux);
0337     cs8409_set_i2c_dev_addr(codec, scodec->addr);
0338 
0339     for (i = 0; i < count; i++) {
0340         cs8409_enable_i2c_clock(codec);
0341         if (cs8409_i2c_set_page(scodec, seq[i].addr))
0342             goto error;
0343 
0344         i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
0345         cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
0346 
0347         if (cs8409_i2c_wait_complete(codec) < 0)
0348             goto error;
0349     }
0350 
0351     mutex_unlock(&spec->i2c_mux);
0352 
0353     return 0;
0354 
0355 error:
0356     mutex_unlock(&spec->i2c_mux);
0357     codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
0358     return -EIO;
0359 }
0360 
0361 static int cs8409_init(struct hda_codec *codec)
0362 {
0363     int ret = snd_hda_gen_init(codec);
0364 
0365     if (!ret)
0366         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
0367 
0368     return ret;
0369 }
0370 
0371 static int cs8409_build_controls(struct hda_codec *codec)
0372 {
0373     int err;
0374 
0375     err = snd_hda_gen_build_controls(codec);
0376     if (err < 0)
0377         return err;
0378     snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
0379 
0380     return 0;
0381 }
0382 
0383 /* Enable/Disable Unsolicited Response */
0384 static void cs8409_enable_ur(struct hda_codec *codec, int flag)
0385 {
0386     struct cs8409_spec *spec = codec->spec;
0387     unsigned int ur_gpios = 0;
0388     int i;
0389 
0390     for (i = 0; i < spec->num_scodecs; i++)
0391         ur_gpios |= spec->scodecs[i]->irq_mask;
0392 
0393     snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
0394                 flag ? ur_gpios : 0);
0395 
0396     snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
0397                 flag ? AC_UNSOL_ENABLED : 0);
0398 }
0399 
0400 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
0401 {
0402     int caps;
0403 
0404     /* CS8409 is simple HDA bridge and intended to be used with a remote
0405      * companion codec. Most of input/output PIN(s) have only basic
0406      * capabilities. Receive and Transmit NID(s) have only OUTC and INC
0407      * capabilities and no presence detect capable (PDC) and call to
0408      * snd_hda_gen_build_controls() will mark them as non detectable
0409      * phantom jacks. However, a companion codec may be
0410      * connected to these pins which supports jack detect
0411      * capabilities. We have to override pin capabilities,
0412      * otherwise they will not be created as input devices.
0413      */
0414     caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
0415     if (caps >= 0)
0416         snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
0417                        (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));
0418 
0419     snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
0420 }
0421 
0422 static int cs8409_spk_sw_gpio_get(struct snd_kcontrol *kcontrol,
0423                  struct snd_ctl_elem_value *ucontrol)
0424 {
0425     struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
0426     struct cs8409_spec *spec = codec->spec;
0427 
0428     ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio);
0429     return 0;
0430 }
0431 
0432 static int cs8409_spk_sw_gpio_put(struct snd_kcontrol *kcontrol,
0433                  struct snd_ctl_elem_value *ucontrol)
0434 {
0435     struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
0436     struct cs8409_spec *spec = codec->spec;
0437     unsigned int gpio_data;
0438 
0439     gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) |
0440         (ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0);
0441     if (gpio_data == spec->gpio_data)
0442         return 0;
0443     spec->gpio_data = gpio_data;
0444     snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
0445     return 1;
0446 }
0447 
0448 static const struct snd_kcontrol_new cs8409_spk_sw_ctrl = {
0449     .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0450     .info = snd_ctl_boolean_mono_info,
0451     .get = cs8409_spk_sw_gpio_get,
0452     .put = cs8409_spk_sw_gpio_put,
0453 };
0454 
0455 /******************************************************************************
0456  *                        CS42L42 Specific Functions
0457  ******************************************************************************/
0458 
0459 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo)
0460 {
0461     unsigned int ofs = get_amp_offset(kctrl);
0462     u8 chs = get_amp_channels(kctrl);
0463 
0464     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0465     uinfo->value.integer.step = 1;
0466     uinfo->count = chs == 3 ? 2 : 1;
0467 
0468     switch (ofs) {
0469     case CS42L42_VOL_DAC:
0470         uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
0471         uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
0472         break;
0473     case CS42L42_VOL_ADC:
0474         uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
0475         uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
0476         break;
0477     default:
0478         break;
0479     }
0480 
0481     return 0;
0482 }
0483 
0484 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
0485 {
0486     struct hda_codec *codec = snd_kcontrol_chip(kctrl);
0487     struct cs8409_spec *spec = codec->spec;
0488     struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
0489     int chs = get_amp_channels(kctrl);
0490     unsigned int ofs = get_amp_offset(kctrl);
0491     long *valp = uctrl->value.integer.value;
0492 
0493     switch (ofs) {
0494     case CS42L42_VOL_DAC:
0495         if (chs & BIT(0))
0496             *valp++ = cs42l42->vol[ofs];
0497         if (chs & BIT(1))
0498             *valp = cs42l42->vol[ofs+1];
0499         break;
0500     case CS42L42_VOL_ADC:
0501         if (chs & BIT(0))
0502             *valp = cs42l42->vol[ofs];
0503         break;
0504     default:
0505         break;
0506     }
0507 
0508     return 0;
0509 }
0510 
0511 static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
0512     unsigned int chs, bool mute)
0513 {
0514     if (mute) {
0515         if (vol_type == CS42L42_VOL_DAC) {
0516             if (chs & BIT(0))
0517                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f);
0518             if (chs & BIT(1))
0519                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f);
0520         } else if (vol_type == CS42L42_VOL_ADC) {
0521             if (chs & BIT(0))
0522                 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f);
0523         }
0524     } else {
0525         if (vol_type == CS42L42_VOL_DAC) {
0526             if (chs & BIT(0))
0527                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL,
0528                     -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
0529                     & CS42L42_MIXER_CH_VOL_MASK);
0530             if (chs & BIT(1))
0531                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL,
0532                     -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
0533                     & CS42L42_MIXER_CH_VOL_MASK);
0534         } else if (vol_type == CS42L42_VOL_ADC) {
0535             if (chs & BIT(0))
0536                 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME,
0537                     cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
0538                     & CS42L42_REG_AMIC_VOL_MASK);
0539         }
0540     }
0541 }
0542 
0543 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
0544 {
0545     struct hda_codec *codec = snd_kcontrol_chip(kctrl);
0546     struct cs8409_spec *spec = codec->spec;
0547     struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
0548     int chs = get_amp_channels(kctrl);
0549     unsigned int ofs = get_amp_offset(kctrl);
0550     long *valp = uctrl->value.integer.value;
0551 
0552     switch (ofs) {
0553     case CS42L42_VOL_DAC:
0554         if (chs & BIT(0))
0555             cs42l42->vol[ofs] = *valp;
0556         if (chs & BIT(1)) {
0557             valp++;
0558             cs42l42->vol[ofs + 1] = *valp;
0559         }
0560         if (spec->playback_started)
0561             cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false);
0562         break;
0563     case CS42L42_VOL_ADC:
0564         if (chs & BIT(0))
0565             cs42l42->vol[ofs] = *valp;
0566         if (spec->capture_started)
0567             cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false);
0568         break;
0569     default:
0570         break;
0571     }
0572 
0573     return 0;
0574 }
0575 
0576 static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo,
0577                    struct hda_codec *codec,
0578                    struct snd_pcm_substream *substream,
0579                    int action)
0580 {
0581     struct cs8409_spec *spec = codec->spec;
0582     struct sub_codec *cs42l42;
0583     int i;
0584     bool mute;
0585 
0586     switch (action) {
0587     case HDA_GEN_PCM_ACT_PREPARE:
0588         mute = false;
0589         spec->playback_started = 1;
0590         break;
0591     case HDA_GEN_PCM_ACT_CLEANUP:
0592         mute = true;
0593         spec->playback_started = 0;
0594         break;
0595     default:
0596         return;
0597     }
0598 
0599     for (i = 0; i < spec->num_scodecs; i++) {
0600         cs42l42 = spec->scodecs[i];
0601         cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute);
0602     }
0603 }
0604 
0605 static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo,
0606                    struct hda_codec *codec,
0607                    struct snd_pcm_substream *substream,
0608                    int action)
0609 {
0610     struct cs8409_spec *spec = codec->spec;
0611     struct sub_codec *cs42l42;
0612     int i;
0613     bool mute;
0614 
0615     switch (action) {
0616     case HDA_GEN_PCM_ACT_PREPARE:
0617         mute = false;
0618         spec->capture_started = 1;
0619         break;
0620     case HDA_GEN_PCM_ACT_CLEANUP:
0621         mute = true;
0622         spec->capture_started = 0;
0623         break;
0624     default:
0625         return;
0626     }
0627 
0628     for (i = 0; i < spec->num_scodecs; i++) {
0629         cs42l42 = spec->scodecs[i];
0630         cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
0631     }
0632 }
0633 
0634 /* Configure CS42L42 slave codec for jack autodetect */
0635 static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
0636 {
0637     cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz);
0638     /* Clear WAKE# */
0639     cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1);
0640     /* Wait ~2.5ms */
0641     usleep_range(2500, 3000);
0642     /* Set mode WAKE# output follows the combination logic directly */
0643     cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0);
0644     /* Clear interrupts status */
0645     cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
0646     /* Enable interrupt */
0647     cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
0648 }
0649 
0650 /* Enable and run CS42L42 slave codec jack auto detect */
0651 static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
0652 {
0653     /* Clear interrupts */
0654     cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
0655     cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1);
0656     cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF);
0657     cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
0658 
0659     cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87);
0660     cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86);
0661     cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07);
0662     cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD);
0663     cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
0664     /* Wait ~20ms*/
0665     usleep_range(20000, 25000);
0666     cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77);
0667     cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0);
0668 }
0669 
0670 static int cs42l42_manual_hs_det(struct sub_codec *cs42l42)
0671 {
0672     unsigned int hs_det_status;
0673     unsigned int hs_det_comp1;
0674     unsigned int hs_det_comp2;
0675     unsigned int hs_det_sw;
0676     unsigned int hs_type;
0677 
0678     /* Set hs detect to manual, active mode */
0679     cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
0680              (1 << CS42L42_HSDET_CTRL_SHIFT) |
0681              (0 << CS42L42_HSDET_SET_SHIFT) |
0682              (0 << CS42L42_HSBIAS_REF_SHIFT) |
0683              (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
0684 
0685     /* Configure HS DET comparator reference levels. */
0686     cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
0687              (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
0688              (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
0689 
0690     /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
0691     cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
0692 
0693     msleep(100);
0694 
0695     hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
0696 
0697     hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
0698             CS42L42_HSDET_COMP1_OUT_SHIFT;
0699     hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
0700             CS42L42_HSDET_COMP2_OUT_SHIFT;
0701 
0702     /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
0703     cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
0704 
0705     msleep(100);
0706 
0707     hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
0708 
0709     hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
0710             CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
0711     hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
0712             CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
0713 
0714     /* Use Comparator 1 with 1.25V Threshold. */
0715     switch (hs_det_comp1) {
0716     case CS42L42_HSDET_COMP_TYPE1:
0717         hs_type = CS42L42_PLUG_CTIA;
0718         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
0719         break;
0720     case CS42L42_HSDET_COMP_TYPE2:
0721         hs_type = CS42L42_PLUG_OMTP;
0722         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
0723         break;
0724     default:
0725         /* Fallback to Comparator 2 with 1.75V Threshold. */
0726         switch (hs_det_comp2) {
0727         case CS42L42_HSDET_COMP_TYPE1:
0728             hs_type = CS42L42_PLUG_CTIA;
0729             hs_det_sw = CS42L42_HSDET_SW_TYPE1;
0730             break;
0731         case CS42L42_HSDET_COMP_TYPE2:
0732             hs_type = CS42L42_PLUG_OMTP;
0733             hs_det_sw = CS42L42_HSDET_SW_TYPE2;
0734             break;
0735         case CS42L42_HSDET_COMP_TYPE3:
0736             hs_type = CS42L42_PLUG_HEADPHONE;
0737             hs_det_sw = CS42L42_HSDET_SW_TYPE3;
0738             break;
0739         default:
0740             hs_type = CS42L42_PLUG_INVALID;
0741             hs_det_sw = CS42L42_HSDET_SW_TYPE4;
0742             break;
0743         }
0744     }
0745 
0746     /* Set Switches */
0747     cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw);
0748 
0749     /* Set HSDET mode to Manual—Disabled */
0750     cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
0751              (0 << CS42L42_HSDET_CTRL_SHIFT) |
0752              (0 << CS42L42_HSDET_SET_SHIFT) |
0753              (0 << CS42L42_HSBIAS_REF_SHIFT) |
0754              (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
0755 
0756     /* Configure HS DET comparator reference levels. */
0757     cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
0758              (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
0759              (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
0760 
0761     return hs_type;
0762 }
0763 
0764 static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
0765 {
0766     int status_changed = 0;
0767 
0768     /* TIP_SENSE INSERT/REMOVE */
0769     switch (reg_ts_status) {
0770     case CS42L42_TS_PLUG:
0771         if (cs42l42->no_type_dect) {
0772             status_changed = 1;
0773             cs42l42->hp_jack_in = 1;
0774             cs42l42->mic_jack_in = 0;
0775         } else {
0776             cs42l42_run_jack_detect(cs42l42);
0777         }
0778         break;
0779 
0780     case CS42L42_TS_UNPLUG:
0781         status_changed = 1;
0782         cs42l42->hp_jack_in = 0;
0783         cs42l42->mic_jack_in = 0;
0784         break;
0785     default:
0786         /* jack in transition */
0787         break;
0788     }
0789 
0790     codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status);
0791 
0792     return status_changed;
0793 }
0794 
0795 static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
0796 {
0797     int current_plug_status;
0798     int status_changed = 0;
0799     int reg_cdc_status;
0800     int reg_hs_status;
0801     int reg_ts_status;
0802     int type;
0803 
0804     /* Read jack detect status registers */
0805     reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
0806     reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
0807     reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
0808 
0809     /* If status values are < 0, read error has occurred. */
0810     if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
0811         return -EIO;
0812 
0813     current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK))
0814                 >> CS42L42_TS_PLUG_SHIFT;
0815 
0816     /* HSDET_AUTO_DONE */
0817     if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) {
0818 
0819         /* Disable HSDET_AUTO_DONE */
0820         cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF);
0821 
0822         type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT;
0823 
0824         /* Configure the HSDET mode. */
0825         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
0826 
0827         if (cs42l42->no_type_dect) {
0828             status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
0829         } else {
0830             if (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) {
0831                 codec_dbg(cs42l42->codec,
0832                       "Auto detect value not valid (%d), running manual det\n",
0833                       type);
0834                 type = cs42l42_manual_hs_det(cs42l42);
0835             }
0836 
0837             switch (type) {
0838             case CS42L42_PLUG_CTIA:
0839             case CS42L42_PLUG_OMTP:
0840                 status_changed = 1;
0841                 cs42l42->hp_jack_in = 1;
0842                 cs42l42->mic_jack_in = 1;
0843                 break;
0844             case CS42L42_PLUG_HEADPHONE:
0845                 status_changed = 1;
0846                 cs42l42->hp_jack_in = 1;
0847                 cs42l42->mic_jack_in = 0;
0848                 break;
0849             default:
0850                 status_changed = 1;
0851                 cs42l42->hp_jack_in = 0;
0852                 cs42l42->mic_jack_in = 0;
0853                 break;
0854             }
0855             codec_dbg(cs42l42->codec, "Detection done (%d)\n", type);
0856         }
0857 
0858         /* Enable the HPOUT ground clamp and configure the HP pull-down */
0859         cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02);
0860         /* Re-Enable Tip Sense Interrupt */
0861         cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
0862     } else {
0863         status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
0864     }
0865 
0866     return status_changed;
0867 }
0868 
0869 static void cs42l42_resume(struct sub_codec *cs42l42)
0870 {
0871     struct hda_codec *codec = cs42l42->codec;
0872     struct cs8409_spec *spec = codec->spec;
0873     struct cs8409_i2c_param irq_regs[] = {
0874         { CS42L42_CODEC_STATUS, 0x00 },
0875         { CS42L42_DET_INT_STATUS1, 0x00 },
0876         { CS42L42_DET_INT_STATUS2, 0x00 },
0877         { CS42L42_TSRS_PLUG_STATUS, 0x00 },
0878     };
0879     int fsv_old, fsv_new;
0880 
0881     /* Bring CS42L42 out of Reset */
0882     spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
0883     spec->gpio_data |= cs42l42->reset_gpio;
0884     snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
0885     usleep_range(10000, 15000);
0886 
0887     cs42l42->suspended = 0;
0888 
0889     /* Initialize CS42L42 companion codec */
0890     cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
0891     usleep_range(20000, 25000);
0892 
0893     /* Clear interrupts, by reading interrupt status registers */
0894     cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
0895 
0896     fsv_old = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL);
0897     if (cs42l42->full_scale_vol == CS42L42_FULL_SCALE_VOL_0DB)
0898         fsv_new = fsv_old & ~CS42L42_FULL_SCALE_VOL_MASK;
0899     else
0900         fsv_new = fsv_old & CS42L42_FULL_SCALE_VOL_MASK;
0901     if (fsv_new != fsv_old)
0902         cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv_new);
0903 
0904     /* we have to explicitly allow unsol event handling even during the
0905      * resume phase so that the jack event is processed properly
0906      */
0907     snd_hda_codec_allow_unsol_events(cs42l42->codec);
0908 
0909     cs42l42_enable_jack_detect(cs42l42);
0910 }
0911 
0912 #ifdef CONFIG_PM
0913 static void cs42l42_suspend(struct sub_codec *cs42l42)
0914 {
0915     struct hda_codec *codec = cs42l42->codec;
0916     struct cs8409_spec *spec = codec->spec;
0917     int reg_cdc_status = 0;
0918     const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
0919         { CS42L42_DAC_CTL2, 0x02 },
0920         { CS42L42_HS_CLAMP_DISABLE, 0x00 },
0921         { CS42L42_MIXER_CHA_VOL, 0x3F },
0922         { CS42L42_MIXER_ADC_VOL, 0x3F },
0923         { CS42L42_MIXER_CHB_VOL, 0x3F },
0924         { CS42L42_HP_CTL, 0x0F },
0925         { CS42L42_ASP_RX_DAI0_EN, 0x00 },
0926         { CS42L42_ASP_CLK_CFG, 0x00 },
0927         { CS42L42_PWR_CTL1, 0xFE },
0928         { CS42L42_PWR_CTL2, 0x8C },
0929         { CS42L42_PWR_CTL1, 0xFF },
0930     };
0931 
0932     cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
0933 
0934     if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
0935             (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
0936             true, cs42l42, CS42L42_CODEC_STATUS) < 0)
0937         codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
0938 
0939     /* Power down CS42L42 ASP/EQ/MIX/HP */
0940     cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);
0941     cs42l42->suspended = 1;
0942     cs42l42->last_page = 0;
0943     cs42l42->hp_jack_in = 0;
0944     cs42l42->mic_jack_in = 0;
0945 
0946     /* Put CS42L42 into Reset */
0947     spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
0948     spec->gpio_data &= ~cs42l42->reset_gpio;
0949     snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
0950 }
0951 #endif
0952 
0953 static void cs8409_free(struct hda_codec *codec)
0954 {
0955     struct cs8409_spec *spec = codec->spec;
0956 
0957     /* Cancel i2c clock disable timer, and disable clock if left enabled */
0958     cancel_delayed_work_sync(&spec->i2c_clk_work);
0959     cs8409_disable_i2c_clock(codec);
0960 
0961     snd_hda_gen_free(codec);
0962 }
0963 
0964 /******************************************************************************
0965  *                   BULLSEYE / WARLOCK / CYBORG Specific Functions
0966  *                               CS8409/CS42L42
0967  ******************************************************************************/
0968 
0969 /*
0970  * In the case of CS8409 we do not have unsolicited events from NID's 0x24
0971  * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
0972  * generate interrupt via gpio 4 to notify jack events. We have to overwrite
0973  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
0974  * and then notify status via generic snd_hda_jack_unsol_event() call.
0975  */
0976 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
0977 {
0978     struct cs8409_spec *spec = codec->spec;
0979     struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
0980     struct hda_jack_tbl *jk;
0981 
0982     /* jack_unsol_event() will be called every time gpio line changing state.
0983      * In this case gpio4 line goes up as a result of reading interrupt status
0984      * registers in previous cs8409_jack_unsol_event() call.
0985      * We don't need to handle this event, ignoring...
0986      */
0987     if (res & cs42l42->irq_mask)
0988         return;
0989 
0990     if (cs42l42_jack_unsol_event(cs42l42)) {
0991         snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
0992                     cs42l42->hp_jack_in ? 0 : PIN_OUT);
0993         /* Report jack*/
0994         jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
0995         if (jk)
0996             snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
0997                             AC_UNSOL_RES_TAG);
0998         /* Report jack*/
0999         jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
1000         if (jk)
1001             snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1002                              AC_UNSOL_RES_TAG);
1003     }
1004 }
1005 
1006 #ifdef CONFIG_PM
1007 /* Manage PDREF, when transition to D3hot */
1008 static int cs8409_cs42l42_suspend(struct hda_codec *codec)
1009 {
1010     struct cs8409_spec *spec = codec->spec;
1011     int i;
1012 
1013     spec->init_done = 0;
1014 
1015     cs8409_enable_ur(codec, 0);
1016 
1017     for (i = 0; i < spec->num_scodecs; i++)
1018         cs42l42_suspend(spec->scodecs[i]);
1019 
1020     /* Cancel i2c clock disable timer, and disable clock if left enabled */
1021     cancel_delayed_work_sync(&spec->i2c_clk_work);
1022     cs8409_disable_i2c_clock(codec);
1023 
1024     snd_hda_shutup_pins(codec);
1025 
1026     return 0;
1027 }
1028 #endif
1029 
1030 /* Vendor specific HW configuration
1031  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1032  */
1033 static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
1034 {
1035     const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;
1036     const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;
1037     struct cs8409_spec *spec = codec->spec;
1038     struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1039 
1040     if (spec->gpio_mask) {
1041         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1042             spec->gpio_mask);
1043         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1044             spec->gpio_dir);
1045         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1046             spec->gpio_data);
1047     }
1048 
1049     for (; seq->nid; seq++)
1050         cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1051 
1052     if (codec->fixup_id == CS8409_BULLSEYE) {
1053         for (; seq_bullseye->nid; seq_bullseye++)
1054             cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
1055     }
1056 
1057     switch (codec->fixup_id) {
1058     case CS8409_CYBORG:
1059     case CS8409_WARLOCK_MLK_DUAL_MIC:
1060         /* DMIC1_MO=00b, DMIC1/2_SR=1 */
1061         cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003);
1062         break;
1063     case CS8409_ODIN:
1064         /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */
1065         cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00);
1066         break;
1067     default:
1068         break;
1069     }
1070 
1071     cs42l42_resume(cs42l42);
1072 
1073     /* Enable Unsolicited Response */
1074     cs8409_enable_ur(codec, 1);
1075 }
1076 
1077 static const struct hda_codec_ops cs8409_cs42l42_patch_ops = {
1078     .build_controls = cs8409_build_controls,
1079     .build_pcms = snd_hda_gen_build_pcms,
1080     .init = cs8409_init,
1081     .free = cs8409_free,
1082     .unsol_event = cs8409_cs42l42_jack_unsol_event,
1083 #ifdef CONFIG_PM
1084     .suspend = cs8409_cs42l42_suspend,
1085 #endif
1086 };
1087 
1088 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1089                     unsigned int *res)
1090 {
1091     struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1092     struct cs8409_spec *spec = codec->spec;
1093     struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1094 
1095     unsigned int nid = ((cmd >> 20) & 0x07f);
1096     unsigned int verb = ((cmd >> 8) & 0x0fff);
1097 
1098     /* CS8409 pins have no AC_PINSENSE_PRESENCE
1099      * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
1100      * and return correct pin sense values for read_pin_sense() call from
1101      * hda_jack based on CS42L42 jack detect status.
1102      */
1103     switch (nid) {
1104     case CS8409_CS42L42_HP_PIN_NID:
1105         if (verb == AC_VERB_GET_PIN_SENSE) {
1106             *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1107             return 0;
1108         }
1109         break;
1110     case CS8409_CS42L42_AMIC_PIN_NID:
1111         if (verb == AC_VERB_GET_PIN_SENSE) {
1112             *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1113             return 0;
1114         }
1115         break;
1116     default:
1117         break;
1118     }
1119 
1120     return spec->exec_verb(dev, cmd, flags, res);
1121 }
1122 
1123 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1124 {
1125     struct cs8409_spec *spec = codec->spec;
1126 
1127     switch (action) {
1128     case HDA_FIXUP_ACT_PRE_PROBE:
1129         snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
1130         /* verb exec op override */
1131         spec->exec_verb = codec->core.exec_verb;
1132         codec->core.exec_verb = cs8409_cs42l42_exec_verb;
1133 
1134         spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
1135         spec->num_scodecs = 1;
1136         spec->scodecs[CS8409_CODEC0]->codec = codec;
1137         codec->patch_ops = cs8409_cs42l42_patch_ops;
1138 
1139         spec->gen.suppress_auto_mute = 1;
1140         spec->gen.no_primary_hp = 1;
1141         spec->gen.suppress_vmaster = 1;
1142 
1143         spec->speaker_pdn_gpio = 0;
1144 
1145         /* GPIO 5 out, 3,4 in */
1146         spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
1147         spec->gpio_data = 0;
1148         spec->gpio_mask = 0x03f;
1149 
1150         /* Basic initial sequence for specific hw configuration */
1151         snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
1152 
1153         cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
1154         cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
1155 
1156         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
1157 
1158         switch (codec->fixup_id) {
1159         case CS8409_CYBORG:
1160             spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1161                 CS42L42_FULL_SCALE_VOL_MINUS6DB;
1162             spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1163             break;
1164         case CS8409_ODIN:
1165             spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1166             spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1167             break;
1168         case CS8409_WARLOCK_MLK:
1169         case CS8409_WARLOCK_MLK_DUAL_MIC:
1170             spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1171             spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1172             break;
1173         default:
1174             spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1175                 CS42L42_FULL_SCALE_VOL_MINUS6DB;
1176             spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1177             break;
1178         }
1179 
1180         if (spec->speaker_pdn_gpio > 0) {
1181             spec->gpio_dir |= spec->speaker_pdn_gpio;
1182             spec->gpio_data |= spec->speaker_pdn_gpio;
1183         }
1184 
1185         break;
1186     case HDA_FIXUP_ACT_PROBE:
1187         /* Fix Sample Rate to 48kHz */
1188         spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1189         spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1190         /* add hooks */
1191         spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1192         spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1193         if (codec->fixup_id != CS8409_ODIN)
1194             /* Set initial DMIC volume to -26 dB */
1195             snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
1196                               HDA_INPUT, 0, 0xff, 0x19);
1197         snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1198                 &cs42l42_dac_volume_mixer);
1199         snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
1200                 &cs42l42_adc_volume_mixer);
1201         if (spec->speaker_pdn_gpio > 0)
1202             snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch",
1203                          &cs8409_spk_sw_ctrl);
1204         /* Disable Unsolicited Response during boot */
1205         cs8409_enable_ur(codec, 0);
1206         snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1207         break;
1208     case HDA_FIXUP_ACT_INIT:
1209         cs8409_cs42l42_hw_init(codec);
1210         spec->init_done = 1;
1211         if (spec->init_done && spec->build_ctrl_done
1212             && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1213             cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1214         break;
1215     case HDA_FIXUP_ACT_BUILD:
1216         spec->build_ctrl_done = 1;
1217         /* Run jack auto detect first time on boot
1218          * after controls have been added, to check if jack has
1219          * been already plugged in.
1220          * Run immediately after init.
1221          */
1222         if (spec->init_done && spec->build_ctrl_done
1223             && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1224             cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1225         break;
1226     default:
1227         break;
1228     }
1229 }
1230 
1231 /******************************************************************************
1232  *                          Dolphin Specific Functions
1233  *                               CS8409/ 2 X CS42L42
1234  ******************************************************************************/
1235 
1236 /*
1237  * In the case of CS8409 we do not have unsolicited events when
1238  * hs mic and hp are connected. Companion codec CS42L42 will
1239  * generate interrupt via irq_mask to notify jack events. We have to overwrite
1240  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
1241  * and then notify status via generic snd_hda_jack_unsol_event() call.
1242  */
1243 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
1244 {
1245     struct cs8409_spec *spec = codec->spec;
1246     struct sub_codec *cs42l42;
1247     struct hda_jack_tbl *jk;
1248 
1249     cs42l42 = spec->scodecs[CS8409_CODEC0];
1250     if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1251         cs42l42_jack_unsol_event(cs42l42)) {
1252         jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
1253         if (jk)
1254             snd_hda_jack_unsol_event(codec,
1255                          (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1256                           AC_UNSOL_RES_TAG);
1257 
1258         jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
1259         if (jk)
1260             snd_hda_jack_unsol_event(codec,
1261                          (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1262                           AC_UNSOL_RES_TAG);
1263     }
1264 
1265     cs42l42 = spec->scodecs[CS8409_CODEC1];
1266     if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1267         cs42l42_jack_unsol_event(cs42l42)) {
1268         jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
1269         if (jk)
1270             snd_hda_jack_unsol_event(codec,
1271                          (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1272                           AC_UNSOL_RES_TAG);
1273     }
1274 }
1275 
1276 /* Vendor specific HW configuration
1277  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1278  */
1279 static void dolphin_hw_init(struct hda_codec *codec)
1280 {
1281     const struct cs8409_cir_param *seq = dolphin_hw_cfg;
1282     struct cs8409_spec *spec = codec->spec;
1283     struct sub_codec *cs42l42;
1284     int i;
1285 
1286     if (spec->gpio_mask) {
1287         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1288                     spec->gpio_mask);
1289         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1290                     spec->gpio_dir);
1291         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1292                     spec->gpio_data);
1293     }
1294 
1295     for (; seq->nid; seq++)
1296         cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1297 
1298     for (i = 0; i < spec->num_scodecs; i++) {
1299         cs42l42 = spec->scodecs[i];
1300         cs42l42_resume(cs42l42);
1301     }
1302 
1303     /* Enable Unsolicited Response */
1304     cs8409_enable_ur(codec, 1);
1305 }
1306 
1307 static const struct hda_codec_ops cs8409_dolphin_patch_ops = {
1308     .build_controls = cs8409_build_controls,
1309     .build_pcms = snd_hda_gen_build_pcms,
1310     .init = cs8409_init,
1311     .free = cs8409_free,
1312     .unsol_event = dolphin_jack_unsol_event,
1313 #ifdef CONFIG_PM
1314     .suspend = cs8409_cs42l42_suspend,
1315 #endif
1316 };
1317 
1318 static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1319                  unsigned int *res)
1320 {
1321     struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1322     struct cs8409_spec *spec = codec->spec;
1323     struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1324 
1325     unsigned int nid = ((cmd >> 20) & 0x07f);
1326     unsigned int verb = ((cmd >> 8) & 0x0fff);
1327 
1328     /* CS8409 pins have no AC_PINSENSE_PRESENCE
1329      * capabilities. We have to intercept calls for CS42L42 pins
1330      * and return correct pin sense values for read_pin_sense() call from
1331      * hda_jack based on CS42L42 jack detect status.
1332      */
1333     switch (nid) {
1334     case DOLPHIN_HP_PIN_NID:
1335     case DOLPHIN_LO_PIN_NID:
1336         if (nid == DOLPHIN_LO_PIN_NID)
1337             cs42l42 = spec->scodecs[CS8409_CODEC1];
1338         if (verb == AC_VERB_GET_PIN_SENSE) {
1339             *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1340             return 0;
1341         }
1342         break;
1343     case DOLPHIN_AMIC_PIN_NID:
1344         if (verb == AC_VERB_GET_PIN_SENSE) {
1345             *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1346             return 0;
1347         }
1348         break;
1349     default:
1350         break;
1351     }
1352 
1353     return spec->exec_verb(dev, cmd, flags, res);
1354 }
1355 
1356 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1357 {
1358     struct cs8409_spec *spec = codec->spec;
1359     struct snd_kcontrol_new *kctrl;
1360     int i;
1361 
1362     switch (action) {
1363     case HDA_FIXUP_ACT_PRE_PROBE:
1364         snd_hda_add_verbs(codec, dolphin_init_verbs);
1365         /* verb exec op override */
1366         spec->exec_verb = codec->core.exec_verb;
1367         codec->core.exec_verb = dolphin_exec_verb;
1368 
1369         spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1370         spec->scodecs[CS8409_CODEC0]->codec = codec;
1371         spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1372         spec->scodecs[CS8409_CODEC1]->codec = codec;
1373         spec->num_scodecs = 2;
1374 
1375         codec->patch_ops = cs8409_dolphin_patch_ops;
1376 
1377         /* GPIO 1,5 out, 0,4 in */
1378         spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1379                  spec->scodecs[CS8409_CODEC1]->reset_gpio;
1380         spec->gpio_data = 0;
1381         spec->gpio_mask = 0x03f;
1382 
1383         /* Basic initial sequence for specific hw configuration */
1384         snd_hda_sequence_write(codec, dolphin_init_verbs);
1385 
1386         snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1387                       SND_JACK_HEADPHONE, NULL);
1388 
1389         snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true,
1390                       SND_JACK_MICROPHONE, NULL);
1391 
1392         cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1393         cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1394         cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1395 
1396         spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1397         spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1398 
1399         break;
1400     case HDA_FIXUP_ACT_PROBE:
1401         /* Fix Sample Rate to 48kHz */
1402         spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1403         spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1404         /* add hooks */
1405         spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1406         spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1407         snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1408                      &cs42l42_dac_volume_mixer);
1409         snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1410         kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1411                          &cs42l42_dac_volume_mixer);
1412         /* Update Line Out kcontrol template */
1413         kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1414                        HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE;
1415         cs8409_enable_ur(codec, 0);
1416         snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1417         break;
1418     case HDA_FIXUP_ACT_INIT:
1419         dolphin_hw_init(codec);
1420         spec->init_done = 1;
1421         if (spec->init_done && spec->build_ctrl_done) {
1422             for (i = 0; i < spec->num_scodecs; i++) {
1423                 if (!spec->scodecs[i]->hp_jack_in)
1424                     cs42l42_run_jack_detect(spec->scodecs[i]);
1425             }
1426         }
1427         break;
1428     case HDA_FIXUP_ACT_BUILD:
1429         spec->build_ctrl_done = 1;
1430         /* Run jack auto detect first time on boot
1431          * after controls have been added, to check if jack has
1432          * been already plugged in.
1433          * Run immediately after init.
1434          */
1435         if (spec->init_done && spec->build_ctrl_done) {
1436             for (i = 0; i < spec->num_scodecs; i++) {
1437                 if (!spec->scodecs[i]->hp_jack_in)
1438                     cs42l42_run_jack_detect(spec->scodecs[i]);
1439             }
1440         }
1441         break;
1442     default:
1443         break;
1444     }
1445 }
1446 
1447 static int patch_cs8409(struct hda_codec *codec)
1448 {
1449     int err;
1450 
1451     if (!cs8409_alloc_spec(codec))
1452         return -ENOMEM;
1453 
1454     snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1455 
1456     codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1457              codec->bus->pci->subsystem_vendor,
1458              codec->bus->pci->subsystem_device);
1459 
1460     snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1461 
1462     err = cs8409_parse_auto_config(codec);
1463     if (err < 0) {
1464         cs8409_free(codec);
1465         return err;
1466     }
1467 
1468     snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1469     return 0;
1470 }
1471 
1472 static const struct hda_device_id snd_hda_id_cs8409[] = {
1473     HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409),
1474     {} /* terminator */
1475 };
1476 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409);
1477 
1478 static struct hda_codec_driver cs8409_driver = {
1479     .id = snd_hda_id_cs8409,
1480 };
1481 module_hda_codec_driver(cs8409_driver);
1482 
1483 MODULE_LICENSE("GPL");
1484 MODULE_DESCRIPTION("Cirrus Logic HDA bridge");
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