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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * patch_cs8409-tables.c  --  HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
0004  *
0005  * Copyright (C) 2021 Cirrus Logic, Inc. and
0006  *                    Cirrus Logic International Semiconductor Ltd.
0007  *
0008  * Author: Lucas Tanure <tanureal@opensource.cirrus.com>
0009  */
0010 
0011 #include "patch_cs8409.h"
0012 
0013 /******************************************************************************
0014  *                          CS42L42 Specific Data
0015  *
0016  ******************************************************************************/
0017 
0018 static const DECLARE_TLV_DB_SCALE(cs42l42_dac_db_scale, CS42L42_HP_VOL_REAL_MIN * 100, 100, 1);
0019 
0020 static const DECLARE_TLV_DB_SCALE(cs42l42_adc_db_scale, CS42L42_AMIC_VOL_REAL_MIN * 100, 100, 1);
0021 
0022 const struct snd_kcontrol_new cs42l42_dac_volume_mixer = {
0023     .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0024     .index = 0,
0025     .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
0026     .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
0027     .info = cs42l42_volume_info,
0028     .get = cs42l42_volume_get,
0029     .put = cs42l42_volume_put,
0030     .tlv = { .p = cs42l42_dac_db_scale },
0031     .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_TRANSMITTER_A, 3, CS8409_CODEC0,
0032              HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE
0033 };
0034 
0035 const struct snd_kcontrol_new cs42l42_adc_volume_mixer = {
0036     .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0037     .index = 0,
0038     .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
0039     .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
0040     .info = cs42l42_volume_info,
0041     .get = cs42l42_volume_get,
0042     .put = cs42l42_volume_put,
0043     .tlv = { .p = cs42l42_adc_db_scale },
0044     .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_RECEIVER_A, 1, CS8409_CODEC0,
0045              HDA_INPUT, CS42L42_VOL_ADC) | HDA_AMP_VAL_MIN_MUTE
0046 };
0047 
0048 const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback = {
0049     .rates = SNDRV_PCM_RATE_48000, /* fixed rate */
0050 };
0051 
0052 const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture = {
0053     .rates = SNDRV_PCM_RATE_48000, /* fixed rate */
0054 };
0055 
0056 /******************************************************************************
0057  *                   BULLSEYE / WARLOCK / CYBORG Specific Arrays
0058  *                               CS8409/CS42L42
0059  ******************************************************************************/
0060 
0061 const struct hda_verb cs8409_cs42l42_init_verbs[] = {
0062     { CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 },     /* WAKE from GPIO 3,4 */
0063     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 },   /* Enable VPW processing */
0064     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 },   /* Configure GPIO 6,7 */
0065     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0080 },   /* I2C mode */
0066     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b },   /* Set I2C bus speed */
0067     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0200 },   /* 100kHz I2C_STO = 2 */
0068     {} /* terminator */
0069 };
0070 
0071 static const struct hda_pintbl cs8409_cs42l42_pincfgs[] = {
0072     { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 },  /* ASP-1-TX */
0073     { CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 }, /* ASP-1-RX */
0074     { CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 },  /* ASP-2-TX */
0075     { CS8409_PIN_DMIC1_IN, 0x90a00090 },        /* DMIC-1 */
0076     {} /* terminator */
0077 };
0078 
0079 static const struct hda_pintbl cs8409_cs42l42_pincfgs_no_dmic[] = {
0080     { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 },  /* ASP-1-TX */
0081     { CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 }, /* ASP-1-RX */
0082     { CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 },  /* ASP-2-TX */
0083     {} /* terminator */
0084 };
0085 
0086 /* Vendor specific HW configuration for CS42L42 */
0087 static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
0088     { CS42L42_I2C_TIMEOUT, 0xB0 },
0089     { CS42L42_ADC_CTL, 0x00 },
0090     { 0x1D02, 0x06 },
0091     { CS42L42_ADC_VOLUME, 0x9F },
0092     { CS42L42_OSC_SWITCH, 0x01 },
0093     { CS42L42_MCLK_CTL, 0x02 },
0094     { CS42L42_SRC_CTL, 0x03 },
0095     { CS42L42_MCLK_SRC_SEL, 0x00 },
0096     { CS42L42_ASP_FRM_CFG, 0x13 },
0097     { CS42L42_FSYNC_P_LOWER, 0xFF },
0098     { CS42L42_FSYNC_P_UPPER, 0x00 },
0099     { CS42L42_ASP_CLK_CFG, 0x20 },
0100     { CS42L42_SPDIF_CLK_CFG, 0x0D },
0101     { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
0102     { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
0103     { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
0104     { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
0105     { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
0106     { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
0107     { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x02 },
0108     { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
0109     { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x80 },
0110     { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x02 },
0111     { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
0112     { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0xA0 },
0113     { CS42L42_ASP_RX_DAI0_EN, 0x0C },
0114     { CS42L42_ASP_TX_CH_EN, 0x01 },
0115     { CS42L42_ASP_TX_CH_AP_RES, 0x02 },
0116     { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
0117     { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
0118     { CS42L42_ASP_TX_SZ_EN, 0x01 },
0119     { CS42L42_PWR_CTL1, 0x0A },
0120     { CS42L42_PWR_CTL2, 0x84 },
0121     { CS42L42_MIXER_CHA_VOL, 0x3F },
0122     { CS42L42_MIXER_CHB_VOL, 0x3F },
0123     { CS42L42_MIXER_ADC_VOL, 0x3f },
0124     { CS42L42_HP_CTL, 0x03 },
0125     { CS42L42_MIC_DET_CTL1, 0xB6 },
0126     { CS42L42_TIPSENSE_CTL, 0xC2 },
0127     { CS42L42_HS_CLAMP_DISABLE, 0x01 },
0128     { CS42L42_HS_SWITCH_CTL, 0xF3 },
0129     { CS42L42_PWR_CTL3, 0x20 },
0130     { CS42L42_RSENSE_CTL2, 0x00 },
0131     { CS42L42_RSENSE_CTL3, 0x00 },
0132     { CS42L42_TSENSE_CTL, 0x80 },
0133     { CS42L42_HS_BIAS_CTL, 0xC0 },
0134     { CS42L42_PWR_CTL1, 0x02 },
0135     { CS42L42_ADC_OVFL_INT_MASK, 0xff },
0136     { CS42L42_MIXER_INT_MASK, 0xff },
0137     { CS42L42_SRC_INT_MASK, 0xff },
0138     { CS42L42_ASP_RX_INT_MASK, 0xff },
0139     { CS42L42_ASP_TX_INT_MASK, 0xff },
0140     { CS42L42_CODEC_INT_MASK, 0xff },
0141     { CS42L42_SRCPL_INT_MASK, 0xff },
0142     { CS42L42_VPMON_INT_MASK, 0xff },
0143     { CS42L42_PLL_LOCK_INT_MASK, 0xff },
0144     { CS42L42_TSRS_PLUG_INT_MASK, 0xff },
0145     { CS42L42_DET_INT1_MASK, 0xff },
0146     { CS42L42_DET_INT2_MASK, 0xff },
0147 };
0148 
0149 /* Vendor specific hw configuration for CS8409 */
0150 const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = {
0151     /* +PLL1/2_EN, +I2C_EN */
0152     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
0153     /* ASP1/2_EN=0, ASP1_STP=1 */
0154     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
0155     /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
0156     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
0157     /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
0158     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
0159     /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
0160     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
0161     /* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
0162     { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL1, 0x0800 },
0163     /* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
0164     { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL2, 0x2800 },
0165     /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
0166     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
0167     /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
0168     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
0169     /* ASP1: LCHI = 00h */
0170     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
0171     /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
0172     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
0173     /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
0174     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
0175     /* ASP2: LCHI=1Fh */
0176     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL1, 0x801f },
0177     /* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
0178     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL2, 0x283f },
0179     /* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
0180     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL3, 0x805c },
0181     /* DMIC1_MO=10b, DMIC1/2_SR=1 */
0182     { CS8409_PIN_VENDOR_WIDGET, CS8409_DMIC_CFG, 0x0023 },
0183     /* ASP1/2_BEEP=0 */
0184     { CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
0185     /* ASP1/2_EN=1, ASP1_STP=1 */
0186     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0062 },
0187     /* -PLL2_EN */
0188     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
0189     /* TX2.A: pre-scale att.=0 dB */
0190     { CS8409_PIN_VENDOR_WIDGET, CS8409_PRE_SCALE_ATTN2, 0x0000 },
0191     /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
0192     { CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc03 },
0193     /* test mode on */
0194     { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
0195     /* GPIO hysteresis = 30 us */
0196     { CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
0197     /* test mode off */
0198     { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
0199     {} /* Terminator */
0200 };
0201 
0202 const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = {
0203     /* EQ_SEL=1, EQ1/2_EN=0 */
0204     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4000 },
0205     /* +EQ_ACC */
0206     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x4000 },
0207     /* +EQ2_EN */
0208     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4010 },
0209     /* EQ_DATA_HI=0x0647 */
0210     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
0211     /* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */
0212     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc0c7 },
0213     /* EQ_DATA_HI=0x0647 */
0214     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
0215     /* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */
0216     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc1c7 },
0217     /* EQ_DATA_HI=0xf370 */
0218     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xf370 },
0219     /* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */
0220     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc271 },
0221     /* EQ_DATA_HI=0x1ef8 */
0222     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ef8 },
0223     /* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */
0224     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc348 },
0225     /* EQ_DATA_HI=0xc110 */
0226     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc110 },
0227     /* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */
0228     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc45a },
0229     /* EQ_DATA_HI=0x1f29 */
0230     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1f29 },
0231     /* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */
0232     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc574 },
0233     /* EQ_DATA_HI=0x1d7a */
0234     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1d7a },
0235     /* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */
0236     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc653 },
0237     /* EQ_DATA_HI=0xc38c */
0238     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
0239     /* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */
0240     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc714 },
0241     /* EQ_DATA_HI=0x1ca3 */
0242     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ca3 },
0243     /* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */
0244     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc8c7 },
0245     /* EQ_DATA_HI=0xc38c */
0246     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
0247     /* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */
0248     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc914 },
0249     /* -EQ_ACC, -EQ_WRT */
0250     { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x0000 },
0251     {} /* Terminator */
0252 };
0253 
0254 struct sub_codec cs8409_cs42l42_codec = {
0255     .addr = CS42L42_I2C_ADDR,
0256     .reset_gpio = CS8409_CS42L42_RESET,
0257     .irq_mask = CS8409_CS42L42_INT,
0258     .init_seq = cs42l42_init_reg_seq,
0259     .init_seq_num = ARRAY_SIZE(cs42l42_init_reg_seq),
0260     .hp_jack_in = 0,
0261     .mic_jack_in = 0,
0262     .paged = 1,
0263     .suspended = 1,
0264     .no_type_dect = 0,
0265 };
0266 
0267 /******************************************************************************
0268  *                          Dolphin Specific Arrays
0269  *                            CS8409/ 2 X CS42L42
0270  ******************************************************************************/
0271 
0272 const struct hda_verb dolphin_init_verbs[] = {
0273     { 0x01, AC_VERB_SET_GPIO_WAKE_MASK, DOLPHIN_WAKE }, /* WAKE from GPIO 0,4 */
0274     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing  */
0275     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
0276     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0080 }, /* I2C mode */
0277     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
0278     { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0200 }, /* 100kHz I2C_STO = 2 */
0279     {} /* terminator */
0280 };
0281 
0282 static const struct hda_pintbl dolphin_pincfgs[] = {
0283     { 0x24, 0x022210f0 }, /* ASP-1-TX-A */
0284     { 0x25, 0x010240f0 }, /* ASP-1-TX-B */
0285     { 0x34, 0x02a21050 }, /* ASP-1-RX */
0286     {} /* terminator */
0287 };
0288 
0289 /* Vendor specific HW configuration for CS42L42 */
0290 static const struct cs8409_i2c_param dolphin_c0_init_reg_seq[] = {
0291     { CS42L42_I2C_TIMEOUT, 0xB0 },
0292     { CS42L42_ADC_CTL, 0x00 },
0293     { 0x1D02, 0x06 },
0294     { CS42L42_ADC_VOLUME, 0x9F },
0295     { CS42L42_OSC_SWITCH, 0x01 },
0296     { CS42L42_MCLK_CTL, 0x02 },
0297     { CS42L42_SRC_CTL, 0x03 },
0298     { CS42L42_MCLK_SRC_SEL, 0x00 },
0299     { CS42L42_ASP_FRM_CFG, 0x13 },
0300     { CS42L42_FSYNC_P_LOWER, 0xFF },
0301     { CS42L42_FSYNC_P_UPPER, 0x00 },
0302     { CS42L42_ASP_CLK_CFG, 0x20 },
0303     { CS42L42_SPDIF_CLK_CFG, 0x0D },
0304     { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
0305     { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
0306     { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
0307     { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
0308     { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
0309     { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
0310     { CS42L42_ASP_RX_DAI0_EN, 0x0C },
0311     { CS42L42_ASP_TX_CH_EN, 0x01 },
0312     { CS42L42_ASP_TX_CH_AP_RES, 0x02 },
0313     { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
0314     { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
0315     { CS42L42_ASP_TX_SZ_EN, 0x01 },
0316     { CS42L42_PWR_CTL1, 0x0A },
0317     { CS42L42_PWR_CTL2, 0x84 },
0318     { CS42L42_HP_CTL, 0x03 },
0319     { CS42L42_MIXER_CHA_VOL, 0x3F },
0320     { CS42L42_MIXER_CHB_VOL, 0x3F },
0321     { CS42L42_MIXER_ADC_VOL, 0x3f },
0322     { CS42L42_MIC_DET_CTL1, 0xB6 },
0323     { CS42L42_TIPSENSE_CTL, 0xC2 },
0324     { CS42L42_HS_CLAMP_DISABLE, 0x01 },
0325     { CS42L42_HS_SWITCH_CTL, 0xF3 },
0326     { CS42L42_PWR_CTL3, 0x20 },
0327     { CS42L42_RSENSE_CTL2, 0x00 },
0328     { CS42L42_RSENSE_CTL3, 0x00 },
0329     { CS42L42_TSENSE_CTL, 0x80 },
0330     { CS42L42_HS_BIAS_CTL, 0xC0 },
0331     { CS42L42_PWR_CTL1, 0x02 },
0332     { CS42L42_ADC_OVFL_INT_MASK, 0xff },
0333     { CS42L42_MIXER_INT_MASK, 0xff },
0334     { CS42L42_SRC_INT_MASK, 0xff },
0335     { CS42L42_ASP_RX_INT_MASK, 0xff },
0336     { CS42L42_ASP_TX_INT_MASK, 0xff },
0337     { CS42L42_CODEC_INT_MASK, 0xff },
0338     { CS42L42_SRCPL_INT_MASK, 0xff },
0339     { CS42L42_VPMON_INT_MASK, 0xff },
0340     { CS42L42_PLL_LOCK_INT_MASK, 0xff },
0341     { CS42L42_TSRS_PLUG_INT_MASK, 0xff },
0342     { CS42L42_DET_INT1_MASK, 0xff },
0343     { CS42L42_DET_INT2_MASK, 0xff }
0344 };
0345 
0346 static const struct cs8409_i2c_param dolphin_c1_init_reg_seq[] = {
0347     { CS42L42_I2C_TIMEOUT, 0xB0 },
0348     { CS42L42_ADC_CTL, 0x00 },
0349     { 0x1D02, 0x06 },
0350     { CS42L42_ADC_VOLUME, 0x9F },
0351     { CS42L42_OSC_SWITCH, 0x01 },
0352     { CS42L42_MCLK_CTL, 0x02 },
0353     { CS42L42_SRC_CTL, 0x03 },
0354     { CS42L42_MCLK_SRC_SEL, 0x00 },
0355     { CS42L42_ASP_FRM_CFG, 0x13 },
0356     { CS42L42_FSYNC_P_LOWER, 0xFF },
0357     { CS42L42_FSYNC_P_UPPER, 0x00 },
0358     { CS42L42_ASP_CLK_CFG, 0x20 },
0359     { CS42L42_SPDIF_CLK_CFG, 0x0D },
0360     { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
0361     { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
0362     { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x80 },
0363     { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
0364     { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
0365     { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0xA0 },
0366     { CS42L42_ASP_RX_DAI0_EN, 0x0C },
0367     { CS42L42_ASP_TX_CH_EN, 0x00 },
0368     { CS42L42_ASP_TX_CH_AP_RES, 0x02 },
0369     { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
0370     { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
0371     { CS42L42_ASP_TX_SZ_EN, 0x00 },
0372     { CS42L42_PWR_CTL1, 0x0E },
0373     { CS42L42_PWR_CTL2, 0x84 },
0374     { CS42L42_HP_CTL, 0x01 },
0375     { CS42L42_MIXER_CHA_VOL, 0x3F },
0376     { CS42L42_MIXER_CHB_VOL, 0x3F },
0377     { CS42L42_MIXER_ADC_VOL, 0x3f },
0378     { CS42L42_MIC_DET_CTL1, 0xB6 },
0379     { CS42L42_TIPSENSE_CTL, 0xC2 },
0380     { CS42L42_HS_CLAMP_DISABLE, 0x01 },
0381     { CS42L42_HS_SWITCH_CTL, 0xF3 },
0382     { CS42L42_PWR_CTL3, 0x20 },
0383     { CS42L42_RSENSE_CTL2, 0x00 },
0384     { CS42L42_RSENSE_CTL3, 0x00 },
0385     { CS42L42_TSENSE_CTL, 0x80 },
0386     { CS42L42_HS_BIAS_CTL, 0xC0 },
0387     { CS42L42_PWR_CTL1, 0x06 },
0388     { CS42L42_ADC_OVFL_INT_MASK, 0xff },
0389     { CS42L42_MIXER_INT_MASK, 0xff },
0390     { CS42L42_SRC_INT_MASK, 0xff },
0391     { CS42L42_ASP_RX_INT_MASK, 0xff },
0392     { CS42L42_ASP_TX_INT_MASK, 0xff },
0393     { CS42L42_CODEC_INT_MASK, 0xff },
0394     { CS42L42_SRCPL_INT_MASK, 0xff },
0395     { CS42L42_VPMON_INT_MASK, 0xff },
0396     { CS42L42_PLL_LOCK_INT_MASK, 0xff },
0397     { CS42L42_TSRS_PLUG_INT_MASK, 0xff },
0398     { CS42L42_DET_INT1_MASK, 0xff },
0399     { CS42L42_DET_INT2_MASK, 0xff }
0400 };
0401 
0402 /* Vendor specific hw configuration for CS8409 */
0403 const struct cs8409_cir_param dolphin_hw_cfg[] = {
0404     /* +PLL1/2_EN, +I2C_EN */
0405     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
0406     /* ASP1_EN=0, ASP1_STP=1 */
0407     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
0408     /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
0409     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
0410     /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
0411     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
0412     /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
0413     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
0414     /* ASP1.B: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=128 */
0415     { CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL1, 0x0880 },
0416     /* ASP1.B: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=160 */
0417     { CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL2, 0x08a0 },
0418     /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
0419     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
0420     /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
0421     { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
0422     /* ASP1: LCHI = 00h */
0423     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
0424     /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
0425     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
0426     /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
0427     { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
0428     /* ASP1/2_BEEP=0 */
0429     { CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
0430     /* ASP1_EN=1, ASP1_STP=1 */
0431     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0022 },
0432     /* -PLL2_EN */
0433     { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
0434     /* ASP1_xxx_EN=1, ASP1_MCLK_EN=0 */
0435     { CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0x5400 },
0436     /* test mode on */
0437     { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
0438     /* GPIO hysteresis = 30 us */
0439     { CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
0440     /* test mode off */
0441     { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
0442     {} /* Terminator */
0443 };
0444 
0445 struct sub_codec dolphin_cs42l42_0 = {
0446     .addr = DOLPHIN_C0_I2C_ADDR,
0447     .reset_gpio = DOLPHIN_C0_RESET,
0448     .irq_mask = DOLPHIN_C0_INT,
0449     .init_seq = dolphin_c0_init_reg_seq,
0450     .init_seq_num = ARRAY_SIZE(dolphin_c0_init_reg_seq),
0451     .hp_jack_in = 0,
0452     .mic_jack_in = 0,
0453     .paged = 1,
0454     .suspended = 1,
0455     .no_type_dect = 0,
0456 };
0457 
0458 struct sub_codec dolphin_cs42l42_1 = {
0459     .addr = DOLPHIN_C1_I2C_ADDR,
0460     .reset_gpio = DOLPHIN_C1_RESET,
0461     .irq_mask = DOLPHIN_C1_INT,
0462     .init_seq = dolphin_c1_init_reg_seq,
0463     .init_seq_num = ARRAY_SIZE(dolphin_c1_init_reg_seq),
0464     .hp_jack_in = 0,
0465     .mic_jack_in = 0,
0466     .paged = 1,
0467     .suspended = 1,
0468     .no_type_dect = 1,
0469 };
0470 
0471 /******************************************************************************
0472  *                         CS8409 Patch Driver Structs
0473  *                    Arrays Used for all projects using CS8409
0474  ******************************************************************************/
0475 
0476 const struct snd_pci_quirk cs8409_fixup_tbl[] = {
0477     SND_PCI_QUIRK(0x1028, 0x0A11, "Bullseye", CS8409_BULLSEYE),
0478     SND_PCI_QUIRK(0x1028, 0x0A12, "Bullseye", CS8409_BULLSEYE),
0479     SND_PCI_QUIRK(0x1028, 0x0A23, "Bullseye", CS8409_BULLSEYE),
0480     SND_PCI_QUIRK(0x1028, 0x0A24, "Bullseye", CS8409_BULLSEYE),
0481     SND_PCI_QUIRK(0x1028, 0x0A25, "Bullseye", CS8409_BULLSEYE),
0482     SND_PCI_QUIRK(0x1028, 0x0A29, "Bullseye", CS8409_BULLSEYE),
0483     SND_PCI_QUIRK(0x1028, 0x0A2A, "Bullseye", CS8409_BULLSEYE),
0484     SND_PCI_QUIRK(0x1028, 0x0A2B, "Bullseye", CS8409_BULLSEYE),
0485     SND_PCI_QUIRK(0x1028, 0x0A77, "Cyborg", CS8409_CYBORG),
0486     SND_PCI_QUIRK(0x1028, 0x0A78, "Cyborg", CS8409_CYBORG),
0487     SND_PCI_QUIRK(0x1028, 0x0A79, "Cyborg", CS8409_CYBORG),
0488     SND_PCI_QUIRK(0x1028, 0x0A7A, "Cyborg", CS8409_CYBORG),
0489     SND_PCI_QUIRK(0x1028, 0x0A7D, "Cyborg", CS8409_CYBORG),
0490     SND_PCI_QUIRK(0x1028, 0x0A7E, "Cyborg", CS8409_CYBORG),
0491     SND_PCI_QUIRK(0x1028, 0x0A7F, "Cyborg", CS8409_CYBORG),
0492     SND_PCI_QUIRK(0x1028, 0x0A80, "Cyborg", CS8409_CYBORG),
0493     SND_PCI_QUIRK(0x1028, 0x0AB0, "Warlock", CS8409_WARLOCK),
0494     SND_PCI_QUIRK(0x1028, 0x0AB2, "Warlock", CS8409_WARLOCK),
0495     SND_PCI_QUIRK(0x1028, 0x0AB1, "Warlock", CS8409_WARLOCK),
0496     SND_PCI_QUIRK(0x1028, 0x0AB3, "Warlock", CS8409_WARLOCK),
0497     SND_PCI_QUIRK(0x1028, 0x0AB4, "Warlock", CS8409_WARLOCK),
0498     SND_PCI_QUIRK(0x1028, 0x0AB5, "Warlock", CS8409_WARLOCK),
0499     SND_PCI_QUIRK(0x1028, 0x0ACF, "Dolphin", CS8409_DOLPHIN),
0500     SND_PCI_QUIRK(0x1028, 0x0AD0, "Dolphin", CS8409_DOLPHIN),
0501     SND_PCI_QUIRK(0x1028, 0x0AD1, "Dolphin", CS8409_DOLPHIN),
0502     SND_PCI_QUIRK(0x1028, 0x0AD2, "Dolphin", CS8409_DOLPHIN),
0503     SND_PCI_QUIRK(0x1028, 0x0AD3, "Dolphin", CS8409_DOLPHIN),
0504     SND_PCI_QUIRK(0x1028, 0x0AD9, "Warlock", CS8409_WARLOCK),
0505     SND_PCI_QUIRK(0x1028, 0x0ADA, "Warlock", CS8409_WARLOCK),
0506     SND_PCI_QUIRK(0x1028, 0x0ADB, "Warlock", CS8409_WARLOCK),
0507     SND_PCI_QUIRK(0x1028, 0x0ADC, "Warlock", CS8409_WARLOCK),
0508     SND_PCI_QUIRK(0x1028, 0x0ADF, "Cyborg", CS8409_CYBORG),
0509     SND_PCI_QUIRK(0x1028, 0x0AE0, "Cyborg", CS8409_CYBORG),
0510     SND_PCI_QUIRK(0x1028, 0x0AE1, "Cyborg", CS8409_CYBORG),
0511     SND_PCI_QUIRK(0x1028, 0x0AE2, "Cyborg", CS8409_CYBORG),
0512     SND_PCI_QUIRK(0x1028, 0x0AE9, "Cyborg", CS8409_CYBORG),
0513     SND_PCI_QUIRK(0x1028, 0x0AEA, "Cyborg", CS8409_CYBORG),
0514     SND_PCI_QUIRK(0x1028, 0x0AEB, "Cyborg", CS8409_CYBORG),
0515     SND_PCI_QUIRK(0x1028, 0x0AEC, "Cyborg", CS8409_CYBORG),
0516     SND_PCI_QUIRK(0x1028, 0x0AED, "Cyborg", CS8409_CYBORG),
0517     SND_PCI_QUIRK(0x1028, 0x0AEE, "Cyborg", CS8409_CYBORG),
0518     SND_PCI_QUIRK(0x1028, 0x0AEF, "Cyborg", CS8409_CYBORG),
0519     SND_PCI_QUIRK(0x1028, 0x0AF0, "Cyborg", CS8409_CYBORG),
0520     SND_PCI_QUIRK(0x1028, 0x0AF4, "Warlock", CS8409_WARLOCK),
0521     SND_PCI_QUIRK(0x1028, 0x0AF5, "Warlock", CS8409_WARLOCK),
0522     SND_PCI_QUIRK(0x1028, 0x0B92, "Warlock MLK", CS8409_WARLOCK_MLK),
0523     SND_PCI_QUIRK(0x1028, 0x0B93, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
0524     SND_PCI_QUIRK(0x1028, 0x0B94, "Warlock MLK", CS8409_WARLOCK_MLK),
0525     SND_PCI_QUIRK(0x1028, 0x0B95, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
0526     SND_PCI_QUIRK(0x1028, 0x0B96, "Warlock MLK", CS8409_WARLOCK_MLK),
0527     SND_PCI_QUIRK(0x1028, 0x0B97, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
0528     SND_PCI_QUIRK(0x1028, 0x0BA5, "Odin", CS8409_ODIN),
0529     SND_PCI_QUIRK(0x1028, 0x0BA6, "Odin", CS8409_ODIN),
0530     SND_PCI_QUIRK(0x1028, 0x0BA8, "Odin", CS8409_ODIN),
0531     SND_PCI_QUIRK(0x1028, 0x0BAA, "Odin", CS8409_ODIN),
0532     SND_PCI_QUIRK(0x1028, 0x0BAE, "Odin", CS8409_ODIN),
0533     SND_PCI_QUIRK(0x1028, 0x0BB2, "Warlock MLK", CS8409_WARLOCK_MLK),
0534     SND_PCI_QUIRK(0x1028, 0x0BB3, "Warlock MLK", CS8409_WARLOCK_MLK),
0535     SND_PCI_QUIRK(0x1028, 0x0BB4, "Warlock MLK", CS8409_WARLOCK_MLK),
0536     SND_PCI_QUIRK(0x1028, 0x0BB5, "Warlock N3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
0537     SND_PCI_QUIRK(0x1028, 0x0BB6, "Warlock V3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
0538     SND_PCI_QUIRK(0x1028, 0x0BB8, "Warlock MLK", CS8409_WARLOCK_MLK),
0539     SND_PCI_QUIRK(0x1028, 0x0BB9, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
0540     SND_PCI_QUIRK(0x1028, 0x0BBA, "Warlock MLK", CS8409_WARLOCK_MLK),
0541     SND_PCI_QUIRK(0x1028, 0x0BBB, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
0542     SND_PCI_QUIRK(0x1028, 0x0BBC, "Warlock MLK", CS8409_WARLOCK_MLK),
0543     SND_PCI_QUIRK(0x1028, 0x0BBD, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
0544     SND_PCI_QUIRK(0x1028, 0x0BD4, "Dolphin", CS8409_DOLPHIN),
0545     SND_PCI_QUIRK(0x1028, 0x0BD5, "Dolphin", CS8409_DOLPHIN),
0546     SND_PCI_QUIRK(0x1028, 0x0BD6, "Dolphin", CS8409_DOLPHIN),
0547     SND_PCI_QUIRK(0x1028, 0x0BD7, "Dolphin", CS8409_DOLPHIN),
0548     SND_PCI_QUIRK(0x1028, 0x0BD8, "Dolphin", CS8409_DOLPHIN),
0549     SND_PCI_QUIRK(0x1028, 0x0C43, "Dolphin", CS8409_DOLPHIN),
0550     SND_PCI_QUIRK(0x1028, 0x0C50, "Dolphin", CS8409_DOLPHIN),
0551     SND_PCI_QUIRK(0x1028, 0x0C51, "Dolphin", CS8409_DOLPHIN),
0552     SND_PCI_QUIRK(0x1028, 0x0C52, "Dolphin", CS8409_DOLPHIN),
0553     {} /* terminator */
0554 };
0555 
0556 /* Dell Inspiron models with cs8409/cs42l42 */
0557 const struct hda_model_fixup cs8409_models[] = {
0558     { .id = CS8409_BULLSEYE, .name = "bullseye" },
0559     { .id = CS8409_WARLOCK, .name = "warlock" },
0560     { .id = CS8409_WARLOCK_MLK, .name = "warlock mlk" },
0561     { .id = CS8409_WARLOCK_MLK_DUAL_MIC, .name = "warlock mlk dual mic" },
0562     { .id = CS8409_CYBORG, .name = "cyborg" },
0563     { .id = CS8409_DOLPHIN, .name = "dolphin" },
0564     { .id = CS8409_ODIN, .name = "odin" },
0565     {}
0566 };
0567 
0568 const struct hda_fixup cs8409_fixups[] = {
0569     [CS8409_BULLSEYE] = {
0570         .type = HDA_FIXUP_PINS,
0571         .v.pins = cs8409_cs42l42_pincfgs,
0572         .chained = true,
0573         .chain_id = CS8409_FIXUPS,
0574     },
0575     [CS8409_WARLOCK] = {
0576         .type = HDA_FIXUP_PINS,
0577         .v.pins = cs8409_cs42l42_pincfgs,
0578         .chained = true,
0579         .chain_id = CS8409_FIXUPS,
0580     },
0581     [CS8409_WARLOCK_MLK] = {
0582         .type = HDA_FIXUP_PINS,
0583         .v.pins = cs8409_cs42l42_pincfgs,
0584         .chained = true,
0585         .chain_id = CS8409_FIXUPS,
0586     },
0587     [CS8409_WARLOCK_MLK_DUAL_MIC] = {
0588         .type = HDA_FIXUP_PINS,
0589         .v.pins = cs8409_cs42l42_pincfgs,
0590         .chained = true,
0591         .chain_id = CS8409_FIXUPS,
0592     },
0593     [CS8409_CYBORG] = {
0594         .type = HDA_FIXUP_PINS,
0595         .v.pins = cs8409_cs42l42_pincfgs,
0596         .chained = true,
0597         .chain_id = CS8409_FIXUPS,
0598     },
0599     [CS8409_FIXUPS] = {
0600         .type = HDA_FIXUP_FUNC,
0601         .v.func = cs8409_cs42l42_fixups,
0602     },
0603     [CS8409_DOLPHIN] = {
0604         .type = HDA_FIXUP_PINS,
0605         .v.pins = dolphin_pincfgs,
0606         .chained = true,
0607         .chain_id = CS8409_DOLPHIN_FIXUPS,
0608     },
0609     [CS8409_DOLPHIN_FIXUPS] = {
0610         .type = HDA_FIXUP_FUNC,
0611         .v.func = dolphin_fixups,
0612     },
0613     [CS8409_ODIN] = {
0614         .type = HDA_FIXUP_PINS,
0615         .v.pins = cs8409_cs42l42_pincfgs_no_dmic,
0616         .chained = true,
0617         .chain_id = CS8409_FIXUPS,
0618     },
0619 };
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