pci/hda/hda_tegra.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/clocksource.h>
0009 #include <linux/completion.h>
0010 #include <linux/delay.h>
0011 #include <linux/dma-mapping.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/moduleparam.h>
0018 #include <linux/mutex.h>
0019 #include <linux/of_device.h>
0020 #include <linux/reset.h>
0021 #include <linux/slab.h>
0022 #include <linux/time.h>
0023 #include <linux/string.h>
0024 #include <linux/pm_runtime.h>
0025
0026 #include <sound/core.h>
0027 #include <sound/initval.h>
0028
0029 #include <sound/hda_codec.h>
0030 #include "hda_controller.h"
0031
0032 /* Defines for Nvidia Tegra HDA support */
0033 #define HDA_BAR0           0x8000
0034
0035 #define HDA_CFG_CMD        0x1004
0036 #define HDA_CFG_BAR0       0x1010
0037
0038 #define HDA_ENABLE_IO_SPACE       (1 << 0)
0039 #define HDA_ENABLE_MEM_SPACE      (1 << 1)
0040 #define HDA_ENABLE_BUS_MASTER     (1 << 2)
0041 #define HDA_ENABLE_SERR           (1 << 8)
0042 #define HDA_DISABLE_INTR          (1 << 10)
0043 #define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
0044 #define HDA_BAR0_FINAL_PROGRAM    (1 << 14)
0045
0046 /* IPFS */
0047 #define HDA_IPFS_CONFIG           0x180
0048 #define HDA_IPFS_EN_FPCI          0x1
0049
0050 #define HDA_IPFS_FPCI_BAR0        0x80
0051 #define HDA_FPCI_BAR0_START       0x40
0052
0053 #define HDA_IPFS_INTR_MASK        0x188
0054 #define HDA_IPFS_EN_INTR          (1 << 16)
0055
0056 /* FPCI */
0057 #define FPCI_DBG_CFG_2        0x10F4
0058 #define FPCI_GCAP_NSDO_SHIFT      18
0059 #define FPCI_GCAP_NSDO_MASK   (0x3 << FPCI_GCAP_NSDO_SHIFT)
0060
0061 /* max number of SDs */
0062 #define NUM_CAPTURE_SD 1
0063 #define NUM_PLAYBACK_SD 1
0064
0065 /*
0066  * Tegra194 does not reflect correct number of SDO lines. Below macro
0067  * is used to update the GCAP register to workaround the issue.
0068  */
0069 #define TEGRA194_NUM_SDO_LINES    4
0070
0071 struct hda_tegra_soc {
0072     bool has_hda2codec_2x_reset;
0073     bool has_hda2hdmi;
0074 };
0075
0076 struct hda_tegra {
0077     struct azx chip;
0078     struct device *dev;
0079     struct reset_control_bulk_data resets[3];
0080     struct clk_bulk_data clocks[3];
0081     unsigned int nresets;
0082     unsigned int nclocks;
0083     void __iomem *regs;
0084     struct work_struct probe_work;
0085     const struct hda_tegra_soc *soc;
0086 };
0087
0088 #ifdef CONFIG_PM
0089 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
0090 module_param(power_save, bint, 0644);
0091 MODULE_PARM_DESC(power_save,
0092          "Automatic power-saving timeout (in seconds, 0 = disable).");
0093 #else
0094 #define power_save  0
0095 #endif
0096
0097 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
0098
0099 static void hda_tegra_init(struct hda_tegra *hda)
0100 {
0101     u32 v;
0102
0103     /* Enable PCI access */
0104     v = readl(hda->regs + HDA_IPFS_CONFIG);
0105     v |= HDA_IPFS_EN_FPCI;
0106     writel(v, hda->regs + HDA_IPFS_CONFIG);
0107
0108     /* Enable MEM/IO space and bus master */
0109     v = readl(hda->regs + HDA_CFG_CMD);
0110     v &= ~HDA_DISABLE_INTR;
0111     v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
0112         HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
0113     writel(v, hda->regs + HDA_CFG_CMD);
0114
0115     writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
0116     writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
0117     writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
0118
0119     v = readl(hda->regs + HDA_IPFS_INTR_MASK);
0120     v |= HDA_IPFS_EN_INTR;
0121     writel(v, hda->regs + HDA_IPFS_INTR_MASK);
0122 }
0123
0124 /*
0125  * power management
0126  */
0127 static int __maybe_unused hda_tegra_suspend(struct device *dev)
0128 {
0129     struct snd_card *card = dev_get_drvdata(dev);
0130     int rc;
0131
0132     rc = pm_runtime_force_suspend(dev);
0133     if (rc < 0)
0134         return rc;
0135     snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
0136
0137     return 0;
0138 }
0139
0140 static int __maybe_unused hda_tegra_resume(struct device *dev)
0141 {
0142     struct snd_card *card = dev_get_drvdata(dev);
0143     int rc;
0144
0145     rc = pm_runtime_force_resume(dev);
0146     if (rc < 0)
0147         return rc;
0148     snd_power_change_state(card, SNDRV_CTL_POWER_D0);
0149
0150     return 0;
0151 }
0152
0153 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
0154 {
0155     struct snd_card *card = dev_get_drvdata(dev);
0156     struct azx *chip = card->private_data;
0157     struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
0158
0159     if (chip && chip->running) {
0160         /* enable controller wake up event */
0161         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
0162                STATESTS_INT_MASK);
0163
0164         azx_stop_chip(chip);
0165         azx_enter_link_reset(chip);
0166     }
0167     clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
0168
0169     return 0;
0170 }
0171
0172 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
0173 {
0174     struct snd_card *card = dev_get_drvdata(dev);
0175     struct azx *chip = card->private_data;
0176     struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
0177     int rc;
0178
0179     if (!chip->running) {
0180         rc = reset_control_bulk_assert(hda->nresets, hda->resets);
0181         if (rc)
0182             return rc;
0183     }
0184
0185     rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
0186     if (rc != 0)
0187         return rc;
0188     if (chip->running) {
0189         hda_tegra_init(hda);
0190         azx_init_chip(chip, 1);
0191         /* disable controller wake up event*/
0192         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
0193                ~STATESTS_INT_MASK);
0194     } else {
0195         usleep_range(10, 100);
0196
0197         rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
0198         if (rc)
0199             return rc;
0200     }
0201
0202     return 0;
0203 }
0204
0205 static const struct dev_pm_ops hda_tegra_pm = {
0206     SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
0207     SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
0208                hda_tegra_runtime_resume,
0209                NULL)
0210 };
0211
0212 static int hda_tegra_dev_disconnect(struct snd_device *device)
0213 {
0214     struct azx *chip = device->device_data;
0215
0216     chip->bus.shutdown = 1;
0217     return 0;
0218 }
0219
0220 /*
0221  * destructor
0222  */
0223 static int hda_tegra_dev_free(struct snd_device *device)
0224 {
0225     struct azx *chip = device->device_data;
0226     struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
0227
0228     cancel_work_sync(&hda->probe_work);
0229     if (azx_bus(chip)->chip_init) {
0230         azx_stop_all_streams(chip);
0231         azx_stop_chip(chip);
0232     }
0233
0234     azx_free_stream_pages(chip);
0235     azx_free_streams(chip);
0236     snd_hdac_bus_exit(azx_bus(chip));
0237
0238     return 0;
0239 }
0240
0241 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
0242 {
0243     struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
0244     struct hdac_bus *bus = azx_bus(chip);
0245     struct resource *res;
0246
0247     hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0248     if (IS_ERR(hda->regs))
0249         return PTR_ERR(hda->regs);
0250
0251     bus->remap_addr = hda->regs + HDA_BAR0;
0252     bus->addr = res->start + HDA_BAR0;
0253
0254     hda_tegra_init(hda);
0255
0256     return 0;
0257 }
0258
0259 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
0260 {
0261     struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
0262     struct hdac_bus *bus = azx_bus(chip);
0263     struct snd_card *card = chip->card;
0264     int err;
0265     unsigned short gcap;
0266     int irq_id = platform_get_irq(pdev, 0);
0267     const char *sname, *drv_name = "tegra-hda";
0268     struct device_node *np = pdev->dev.of_node;
0269
0270     if (irq_id < 0)
0271         return irq_id;
0272
0273     err = hda_tegra_init_chip(chip, pdev);
0274     if (err)
0275         return err;
0276
0277     err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
0278                  IRQF_SHARED, KBUILD_MODNAME, chip);
0279     if (err) {
0280         dev_err(chip->card->dev,
0281             "unable to request IRQ %d, disabling device\n",
0282             irq_id);
0283         return err;
0284     }
0285     bus->irq = irq_id;
0286     bus->dma_stop_delay = 100;
0287     card->sync_irq = bus->irq;
0288
0289     /*
0290      * Tegra194 has 4 SDO lines and the STRIPE can be used to
0291      * indicate how many of the SDO lines the stream should be
0292      * striped. But GCAP register does not reflect the true
0293      * capability of HW. Below workaround helps to fix this.
0294      *
0295      * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
0296      * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
0297      */
0298     if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
0299         u32 val;
0300
0301         dev_info(card->dev, "Override SDO lines to %u\n",
0302              TEGRA194_NUM_SDO_LINES);
0303
0304         val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
0305         val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
0306         writel(val, hda->regs + FPCI_DBG_CFG_2);
0307     }
0308
0309     gcap = azx_readw(chip, GCAP);
0310     dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
0311
0312     chip->align_buffer_size = 1;
0313
0314     /* read number of streams from GCAP register instead of using
0315      * hardcoded value
0316      */
0317     chip->capture_streams = (gcap >> 8) & 0x0f;
0318
0319     /* The GCAP register on Tegra234 implies no Input Streams(ISS) support,
0320      * but the HW output stream descriptor programming should start with
0321      * offset 0x20*4 from base stream descriptor address. This will be a
0322      * problem while calculating the offset for output stream descriptor
0323      * which will be considering input stream also. So here output stream
0324      * starts with offset 0 which is wrong as HW register for output stream
0325      * offset starts with 4.
0326      */
0327     if (of_device_is_compatible(np, "nvidia,tegra234-hda"))
0328         chip->capture_streams = 4;
0329
0330     chip->playback_streams = (gcap >> 12) & 0x0f;
0331     if (!chip->playback_streams && !chip->capture_streams) {
0332         /* gcap didn't give any info, switching to old method */
0333         chip->playback_streams = NUM_PLAYBACK_SD;
0334         chip->capture_streams = NUM_CAPTURE_SD;
0335     }
0336     chip->capture_index_offset = 0;
0337     chip->playback_index_offset = chip->capture_streams;
0338     chip->num_streams = chip->playback_streams + chip->capture_streams;
0339
0340     /* initialize streams */
0341     err = azx_init_streams(chip);
0342     if (err < 0) {
0343         dev_err(card->dev, "failed to initialize streams: %d\n", err);
0344         return err;
0345     }
0346
0347     err = azx_alloc_stream_pages(chip);
0348     if (err < 0) {
0349         dev_err(card->dev, "failed to allocate stream pages: %d\n",
0350             err);
0351         return err;
0352     }
0353
0354     /* initialize chip */
0355     azx_init_chip(chip, 1);
0356
0357     /*
0358      * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
0359      * 4 SDO lines due to legacy design limitation. Following
0360      * is, from HD Audio Specification (Revision 1.0a), used to
0361      * control striping of the stream across multiple SDO lines
0362      * for sample rates <= 48K.
0363      *
0364      * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
0365      *
0366      * Due to legacy design issue it is recommended that above
0367      * ratio must be greater than 8. Since number of SDO lines is
0368      * in powers of 2, next available ratio is 16 which can be
0369      * used as a limiting factor here.
0370      */
0371     if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
0372         chip->bus.core.sdo_limit = 16;
0373
0374     /* codec detection */
0375     if (!bus->codec_mask) {
0376         dev_err(card->dev, "no codecs found!\n");
0377         return -ENODEV;
0378     }
0379
0380     /* driver name */
0381     strncpy(card->driver, drv_name, sizeof(card->driver));
0382     /* shortname for card */
0383     sname = of_get_property(np, "nvidia,model", NULL);
0384     if (!sname)
0385         sname = drv_name;
0386     if (strlen(sname) > sizeof(card->shortname))
0387         dev_info(card->dev, "truncating shortname for card\n");
0388     strncpy(card->shortname, sname, sizeof(card->shortname));
0389
0390     /* longname for card */
0391     snprintf(card->longname, sizeof(card->longname),
0392          "%s at 0x%lx irq %i",
0393          card->shortname, bus->addr, bus->irq);
0394
0395     return 0;
0396 }
0397
0398 /*
0399  * constructor
0400  */
0401
0402 static void hda_tegra_probe_work(struct work_struct *work);
0403
0404 static int hda_tegra_create(struct snd_card *card,
0405                 unsigned int driver_caps,
0406                 struct hda_tegra *hda)
0407 {
0408     static const struct snd_device_ops ops = {
0409         .dev_disconnect = hda_tegra_dev_disconnect,
0410         .dev_free = hda_tegra_dev_free,
0411     };
0412     struct azx *chip;
0413     int err;
0414
0415     chip = &hda->chip;
0416
0417     mutex_init(&chip->open_mutex);
0418     chip->card = card;
0419     chip->ops = &hda_tegra_ops;
0420     chip->driver_caps = driver_caps;
0421     chip->driver_type = driver_caps & 0xff;
0422     chip->dev_index = 0;
0423     chip->jackpoll_interval = msecs_to_jiffies(5000);
0424     INIT_LIST_HEAD(&chip->pcm_list);
0425
0426     chip->codec_probe_mask = -1;
0427
0428     chip->single_cmd = false;
0429     chip->snoop = true;
0430
0431     INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
0432
0433     err = azx_bus_init(chip, NULL);
0434     if (err < 0)
0435         return err;
0436
0437     chip->bus.core.sync_write = 0;
0438     chip->bus.core.needs_damn_long_delay = 1;
0439     chip->bus.core.aligned_mmio = 1;
0440     chip->bus.jackpoll_in_suspend = 1;
0441
0442     err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
0443     if (err < 0) {
0444         dev_err(card->dev, "Error creating device\n");
0445         return err;
0446     }
0447
0448     return 0;
0449 }
0450
0451 static const struct hda_tegra_soc tegra30_data = {
0452     .has_hda2codec_2x_reset = true,
0453     .has_hda2hdmi = true,
0454 };
0455
0456 static const struct hda_tegra_soc tegra194_data = {
0457     .has_hda2codec_2x_reset = false,
0458     .has_hda2hdmi = true,
0459 };
0460
0461 static const struct hda_tegra_soc tegra234_data = {
0462     .has_hda2codec_2x_reset = true,
0463     .has_hda2hdmi = false,
0464 };
0465
0466 static const struct of_device_id hda_tegra_match[] = {
0467     { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
0468     { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
0469     { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data },
0470     {},
0471 };
0472 MODULE_DEVICE_TABLE(of, hda_tegra_match);
0473
0474 static int hda_tegra_probe(struct platform_device *pdev)
0475 {
0476     const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
0477                       AZX_DCAPS_PM_RUNTIME |
0478                       AZX_DCAPS_4K_BDLE_BOUNDARY;
0479     struct snd_card *card;
0480     struct azx *chip;
0481     struct hda_tegra *hda;
0482     int err;
0483
0484     hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
0485     if (!hda)
0486         return -ENOMEM;
0487     hda->dev = &pdev->dev;
0488     chip = &hda->chip;
0489
0490     hda->soc = of_device_get_match_data(&pdev->dev);
0491
0492     err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
0493                THIS_MODULE, 0, &card);
0494     if (err < 0) {
0495         dev_err(&pdev->dev, "Error creating card!\n");
0496         return err;
0497     }
0498
0499     hda->resets[hda->nresets++].id = "hda";
0500
0501     /*
0502      * "hda2hdmi" is not applicable for Tegra234. This is because the
0503      * codec is separate IP and not under display SOR partition now.
0504      */
0505     if (hda->soc->has_hda2hdmi)
0506         hda->resets[hda->nresets++].id = "hda2hdmi";
0507
0508     /*
0509      * "hda2codec_2x" reset is not present on Tegra194. Though DT would
0510      * be updated to reflect this, but to have backward compatibility
0511      * below is necessary.
0512      */
0513     if (hda->soc->has_hda2codec_2x_reset)
0514         hda->resets[hda->nresets++].id = "hda2codec_2x";
0515
0516     err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
0517                             hda->resets);
0518     if (err)
0519         goto out_free;
0520
0521     hda->clocks[hda->nclocks++].id = "hda";
0522     if (hda->soc->has_hda2hdmi)
0523         hda->clocks[hda->nclocks++].id = "hda2hdmi";
0524     hda->clocks[hda->nclocks++].id = "hda2codec_2x";
0525
0526     err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
0527     if (err < 0)
0528         goto out_free;
0529
0530     err = hda_tegra_create(card, driver_flags, hda);
0531     if (err < 0)
0532         goto out_free;
0533     card->private_data = chip;
0534
0535     dev_set_drvdata(&pdev->dev, card);
0536
0537     pm_runtime_enable(hda->dev);
0538     if (!azx_has_pm_runtime(chip))
0539         pm_runtime_forbid(hda->dev);
0540
0541     schedule_work(&hda->probe_work);
0542
0543     return 0;
0544
0545 out_free:
0546     snd_card_free(card);
0547     return err;
0548 }
0549
0550 static void hda_tegra_probe_work(struct work_struct *work)
0551 {
0552     struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
0553     struct azx *chip = &hda->chip;
0554     struct platform_device *pdev = to_platform_device(hda->dev);
0555     int err;
0556
0557     pm_runtime_get_sync(hda->dev);
0558     err = hda_tegra_first_init(chip, pdev);
0559     if (err < 0)
0560         goto out_free;
0561
0562     /* create codec instances */
0563     err = azx_probe_codecs(chip, 8);
0564     if (err < 0)
0565         goto out_free;
0566
0567     err = azx_codec_configure(chip);
0568     if (err < 0)
0569         goto out_free;
0570
0571     err = snd_card_register(chip->card);
0572     if (err < 0)
0573         goto out_free;
0574
0575     chip->running = 1;
0576     snd_hda_set_power_save(&chip->bus, power_save * 1000);
0577
0578  out_free:
0579     pm_runtime_put(hda->dev);
0580     return; /* no error return from async probe */
0581 }
0582
0583 static int hda_tegra_remove(struct platform_device *pdev)
0584 {
0585     int ret;
0586
0587     ret = snd_card_free(dev_get_drvdata(&pdev->dev));
0588     pm_runtime_disable(&pdev->dev);
0589
0590     return ret;
0591 }
0592
0593 static void hda_tegra_shutdown(struct platform_device *pdev)
0594 {
0595     struct snd_card *card = dev_get_drvdata(&pdev->dev);
0596     struct azx *chip;
0597
0598     if (!card)
0599         return;
0600     chip = card->private_data;
0601     if (chip && chip->running)
0602         azx_stop_chip(chip);
0603 }
0604
0605 static struct platform_driver tegra_platform_hda = {
0606     .driver = {
0607         .name = "tegra-hda",
0608         .pm = &hda_tegra_pm,
0609         .of_match_table = hda_tegra_match,
0610     },
0611     .probe = hda_tegra_probe,
0612     .remove = hda_tegra_remove,
0613     .shutdown = hda_tegra_shutdown,
0614 };
0615 module_platform_driver(tegra_platform_hda);
0616
0617 MODULE_DESCRIPTION("Tegra HDA bus driver");
0618 MODULE_LICENSE("GPL v2");