pci/hda/hda_controller.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  Common functionality for the alsa driver code base for HD Audio.
0004  */
0005
0006 #ifndef __SOUND_HDA_CONTROLLER_H
0007 #define __SOUND_HDA_CONTROLLER_H
0008
0009 #include <linux/timecounter.h>
0010 #include <linux/interrupt.h>
0011 #include <sound/core.h>
0012 #include <sound/pcm.h>
0013 #include <sound/initval.h>
0014 #include <sound/hda_codec.h>
0015 #include <sound/hda_register.h>
0016
0017 #define AZX_MAX_CODECS      HDA_MAX_CODECS
0018 #define AZX_DEFAULT_CODECS  4
0019
0020 /* driver quirks (capabilities) */
0021 /* bits 0-7 are used for indicating driver type */
0022 #define AZX_DCAPS_NO_TCSEL  (1 << 8)    /* No Intel TCSEL bit */
0023 #define AZX_DCAPS_NO_MSI    (1 << 9)    /* No MSI support */
0024 #define AZX_DCAPS_SNOOP_MASK    (3 << 10)   /* snoop type mask */
0025 #define AZX_DCAPS_SNOOP_OFF (1 << 12)   /* snoop default off */
0026 #ifdef CONFIG_SND_HDA_I915
0027 #define AZX_DCAPS_I915_COMPONENT (1 << 13)  /* bind with i915 gfx */
0028 #else
0029 #define AZX_DCAPS_I915_COMPONENT 0      /* NOP */
0030 #endif
0031 /* 14 unused */
0032 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)  /* X-Fi workaround */
0033 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)   /* Use LPIB as default */
0034 #define AZX_DCAPS_AMD_WORKAROUND (1 << 17)  /* AMD-specific workaround */
0035 #define AZX_DCAPS_NO_64BIT  (1 << 18)   /* No 64bit address */
0036 /* 19 unused */
0037 #define AZX_DCAPS_OLD_SSYNC (1 << 20)   /* Old SSYNC reg for ICH */
0038 #define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21)    /* no buffer size alignment */
0039 /* 22 unused */
0040 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
0041 /* 24 unused */
0042 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
0043 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)   /* runtime PM support */
0044 #define AZX_DCAPS_RETRY_PROBE   (1 << 27)   /* retry probe if no codec is configured */
0045 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)   /* CORBRP clears itself after reset */
0046 #define AZX_DCAPS_NO_MSI64      (1 << 29)   /* Stick to 32-bit MSIs */
0047 #define AZX_DCAPS_SEPARATE_STREAM_TAG   (1 << 30) /* capture and playback use separate stream tag */
0048
0049 enum {
0050     AZX_SNOOP_TYPE_NONE,
0051     AZX_SNOOP_TYPE_SCH,
0052     AZX_SNOOP_TYPE_ATI,
0053     AZX_SNOOP_TYPE_NVIDIA,
0054 };
0055
0056 struct azx_dev {
0057     struct hdac_stream core;
0058
0059     unsigned int irq_pending:1;
0060     /*
0061      * For VIA:
0062      *  A flag to ensure DMA position is 0
0063      *  when link position is not greater than FIFO size
0064      */
0065     unsigned int insufficient:1;
0066 };
0067
0068 #define azx_stream(dev)     (&(dev)->core)
0069 #define stream_to_azx_dev(s)    container_of(s, struct azx_dev, core)
0070
0071 struct azx;
0072
0073 /* Functions to read/write to hda registers. */
0074 struct hda_controller_ops {
0075     /* Disable msi if supported, PCI only */
0076     int (*disable_msi_reset_irq)(struct azx *);
0077     /* Check if current position is acceptable */
0078     int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
0079     /* enable/disable the link power */
0080     int (*link_power)(struct azx *chip, bool enable);
0081 };
0082
0083 struct azx_pcm {
0084     struct azx *chip;
0085     struct snd_pcm *pcm;
0086     struct hda_codec *codec;
0087     struct hda_pcm *info;
0088     struct list_head list;
0089 };
0090
0091 typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
0092 typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
0093
0094 struct azx {
0095     struct hda_bus bus;
0096
0097     struct snd_card *card;
0098     struct pci_dev *pci;
0099     int dev_index;
0100
0101     /* chip type specific */
0102     int driver_type;
0103     unsigned int driver_caps;
0104     int playback_streams;
0105     int playback_index_offset;
0106     int capture_streams;
0107     int capture_index_offset;
0108     int num_streams;
0109     int jackpoll_interval; /* jack poll interval in jiffies */
0110
0111     /* Register interaction. */
0112     const struct hda_controller_ops *ops;
0113
0114     /* position adjustment callbacks */
0115     azx_get_pos_callback_t get_position[2];
0116     azx_get_delay_callback_t get_delay[2];
0117
0118     /* locks */
0119     struct mutex open_mutex; /* Prevents concurrent open/close operations */
0120
0121     /* PCM */
0122     struct list_head pcm_list; /* azx_pcm list */
0123
0124     /* HD codec */
0125     int  codec_probe_mask; /* copied from probe_mask option */
0126     unsigned int beep_mode;
0127
0128 #ifdef CONFIG_SND_HDA_PATCH_LOADER
0129     const struct firmware *fw;
0130 #endif
0131
0132     /* flags */
0133     int bdl_pos_adj;
0134     unsigned int running:1;
0135     unsigned int fallback_to_single_cmd:1;
0136     unsigned int single_cmd:1;
0137     unsigned int msi:1;
0138     unsigned int probing:1; /* codec probing phase */
0139     unsigned int snoop:1;
0140     unsigned int uc_buffer:1; /* non-cached pages for stream buffers */
0141     unsigned int align_buffer_size:1;
0142     unsigned int disabled:1; /* disabled by vga_switcheroo */
0143     unsigned int pm_prepared:1;
0144
0145     /* GTS present */
0146     unsigned int gts_present:1;
0147
0148 #ifdef CONFIG_SND_HDA_DSP_LOADER
0149     struct azx_dev saved_azx_dev;
0150 #endif
0151 };
0152
0153 #define azx_bus(chip)   (&(chip)->bus.core)
0154 #define bus_to_azx(_bus)    container_of(_bus, struct azx, bus.core)
0155
0156 static inline bool azx_snoop(struct azx *chip)
0157 {
0158     return !IS_ENABLED(CONFIG_X86) || chip->snoop;
0159 }
0160
0161 /*
0162  * macros for easy use
0163  */
0164
0165 #define azx_writel(chip, reg, value) \
0166     snd_hdac_chip_writel(azx_bus(chip), reg, value)
0167 #define azx_readl(chip, reg) \
0168     snd_hdac_chip_readl(azx_bus(chip), reg)
0169 #define azx_writew(chip, reg, value) \
0170     snd_hdac_chip_writew(azx_bus(chip), reg, value)
0171 #define azx_readw(chip, reg) \
0172     snd_hdac_chip_readw(azx_bus(chip), reg)
0173 #define azx_writeb(chip, reg, value) \
0174     snd_hdac_chip_writeb(azx_bus(chip), reg, value)
0175 #define azx_readb(chip, reg) \
0176     snd_hdac_chip_readb(azx_bus(chip), reg)
0177
0178 #define azx_has_pm_runtime(chip) \
0179     ((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME)
0180
0181 /* PCM setup */
0182 static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
0183 {
0184     return substream->runtime->private_data;
0185 }
0186 unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev);
0187 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev);
0188 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev);
0189
0190 /* Stream control. */
0191 void azx_stop_all_streams(struct azx *chip);
0192
0193 /* Allocation functions. */
0194 #define azx_alloc_stream_pages(chip) \
0195     snd_hdac_bus_alloc_stream_pages(azx_bus(chip))
0196 #define azx_free_stream_pages(chip) \
0197     snd_hdac_bus_free_stream_pages(azx_bus(chip))
0198
0199 /* Low level azx interface */
0200 void azx_init_chip(struct azx *chip, bool full_reset);
0201 void azx_stop_chip(struct azx *chip);
0202 #define azx_enter_link_reset(chip) \
0203     snd_hdac_bus_enter_link_reset(azx_bus(chip))
0204 irqreturn_t azx_interrupt(int irq, void *dev_id);
0205
0206 /* Codec interface */
0207 int azx_bus_init(struct azx *chip, const char *model);
0208 int azx_probe_codecs(struct azx *chip, unsigned int max_slots);
0209 int azx_codec_configure(struct azx *chip);
0210 int azx_init_streams(struct azx *chip);
0211 void azx_free_streams(struct azx *chip);
0212
0213 #endif /* __SOUND_HDA_CONTROLLER_H */