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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *
0004  *  Implementation of primary alsa driver code base for Intel HD Audio.
0005  *
0006  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
0007  *
0008  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
0009  *                     PeiSen Hou <pshou@realtek.com.tw>
0010  */
0011 
0012 #include <linux/clocksource.h>
0013 #include <linux/delay.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/slab.h>
0019 
0020 #ifdef CONFIG_X86
0021 /* for art-tsc conversion */
0022 #include <asm/tsc.h>
0023 #endif
0024 
0025 #include <sound/core.h>
0026 #include <sound/initval.h>
0027 #include "hda_controller.h"
0028 #include "hda_local.h"
0029 
0030 #define CREATE_TRACE_POINTS
0031 #include "hda_controller_trace.h"
0032 
0033 /* DSP lock helpers */
0034 #define dsp_lock(dev)       snd_hdac_dsp_lock(azx_stream(dev))
0035 #define dsp_unlock(dev)     snd_hdac_dsp_unlock(azx_stream(dev))
0036 #define dsp_is_locked(dev)  snd_hdac_stream_is_locked(azx_stream(dev))
0037 
0038 /* assign a stream for the PCM */
0039 static inline struct azx_dev *
0040 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
0041 {
0042     struct hdac_stream *s;
0043 
0044     s = snd_hdac_stream_assign(azx_bus(chip), substream);
0045     if (!s)
0046         return NULL;
0047     return stream_to_azx_dev(s);
0048 }
0049 
0050 /* release the assigned stream */
0051 static inline void azx_release_device(struct azx_dev *azx_dev)
0052 {
0053     snd_hdac_stream_release(azx_stream(azx_dev));
0054 }
0055 
0056 static inline struct hda_pcm_stream *
0057 to_hda_pcm_stream(struct snd_pcm_substream *substream)
0058 {
0059     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0060     return &apcm->info->stream[substream->stream];
0061 }
0062 
0063 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
0064                 u64 nsec)
0065 {
0066     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0067     struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
0068     u64 codec_frames, codec_nsecs;
0069 
0070     if (!hinfo->ops.get_delay)
0071         return nsec;
0072 
0073     codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
0074     codec_nsecs = div_u64(codec_frames * 1000000000LL,
0075                   substream->runtime->rate);
0076 
0077     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0078         return nsec + codec_nsecs;
0079 
0080     return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
0081 }
0082 
0083 /*
0084  * PCM ops
0085  */
0086 
0087 static int azx_pcm_close(struct snd_pcm_substream *substream)
0088 {
0089     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0090     struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
0091     struct azx *chip = apcm->chip;
0092     struct azx_dev *azx_dev = get_azx_dev(substream);
0093 
0094     trace_azx_pcm_close(chip, azx_dev);
0095     mutex_lock(&chip->open_mutex);
0096     azx_release_device(azx_dev);
0097     if (hinfo->ops.close)
0098         hinfo->ops.close(hinfo, apcm->codec, substream);
0099     snd_hda_power_down(apcm->codec);
0100     mutex_unlock(&chip->open_mutex);
0101     snd_hda_codec_pcm_put(apcm->info);
0102     return 0;
0103 }
0104 
0105 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
0106                  struct snd_pcm_hw_params *hw_params)
0107 {
0108     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0109     struct azx *chip = apcm->chip;
0110     struct azx_dev *azx_dev = get_azx_dev(substream);
0111     int ret = 0;
0112 
0113     trace_azx_pcm_hw_params(chip, azx_dev);
0114     dsp_lock(azx_dev);
0115     if (dsp_is_locked(azx_dev)) {
0116         ret = -EBUSY;
0117         goto unlock;
0118     }
0119 
0120     azx_dev->core.bufsize = 0;
0121     azx_dev->core.period_bytes = 0;
0122     azx_dev->core.format_val = 0;
0123 
0124 unlock:
0125     dsp_unlock(azx_dev);
0126     return ret;
0127 }
0128 
0129 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
0130 {
0131     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0132     struct azx_dev *azx_dev = get_azx_dev(substream);
0133     struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
0134 
0135     /* reset BDL address */
0136     dsp_lock(azx_dev);
0137     if (!dsp_is_locked(azx_dev))
0138         snd_hdac_stream_cleanup(azx_stream(azx_dev));
0139 
0140     snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
0141 
0142     azx_stream(azx_dev)->prepared = 0;
0143     dsp_unlock(azx_dev);
0144     return 0;
0145 }
0146 
0147 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
0148 {
0149     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0150     struct azx *chip = apcm->chip;
0151     struct azx_dev *azx_dev = get_azx_dev(substream);
0152     struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
0153     struct snd_pcm_runtime *runtime = substream->runtime;
0154     unsigned int format_val, stream_tag;
0155     int err;
0156     struct hda_spdif_out *spdif =
0157         snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
0158     unsigned short ctls = spdif ? spdif->ctls : 0;
0159 
0160     trace_azx_pcm_prepare(chip, azx_dev);
0161     dsp_lock(azx_dev);
0162     if (dsp_is_locked(azx_dev)) {
0163         err = -EBUSY;
0164         goto unlock;
0165     }
0166 
0167     snd_hdac_stream_reset(azx_stream(azx_dev));
0168     format_val = snd_hdac_calc_stream_format(runtime->rate,
0169                         runtime->channels,
0170                         runtime->format,
0171                         hinfo->maxbps,
0172                         ctls);
0173     if (!format_val) {
0174         dev_err(chip->card->dev,
0175             "invalid format_val, rate=%d, ch=%d, format=%d\n",
0176             runtime->rate, runtime->channels, runtime->format);
0177         err = -EINVAL;
0178         goto unlock;
0179     }
0180 
0181     err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
0182     if (err < 0)
0183         goto unlock;
0184 
0185     snd_hdac_stream_setup(azx_stream(azx_dev));
0186 
0187     stream_tag = azx_dev->core.stream_tag;
0188     /* CA-IBG chips need the playback stream starting from 1 */
0189     if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
0190         stream_tag > chip->capture_streams)
0191         stream_tag -= chip->capture_streams;
0192     err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
0193                      azx_dev->core.format_val, substream);
0194 
0195  unlock:
0196     if (!err)
0197         azx_stream(azx_dev)->prepared = 1;
0198     dsp_unlock(azx_dev);
0199     return err;
0200 }
0201 
0202 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
0203 {
0204     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0205     struct azx *chip = apcm->chip;
0206     struct hdac_bus *bus = azx_bus(chip);
0207     struct azx_dev *azx_dev;
0208     struct snd_pcm_substream *s;
0209     struct hdac_stream *hstr;
0210     bool start;
0211     int sbits = 0;
0212     int sync_reg;
0213 
0214     azx_dev = get_azx_dev(substream);
0215     trace_azx_pcm_trigger(chip, azx_dev, cmd);
0216 
0217     hstr = azx_stream(azx_dev);
0218     if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
0219         sync_reg = AZX_REG_OLD_SSYNC;
0220     else
0221         sync_reg = AZX_REG_SSYNC;
0222 
0223     if (dsp_is_locked(azx_dev) || !hstr->prepared)
0224         return -EPIPE;
0225 
0226     switch (cmd) {
0227     case SNDRV_PCM_TRIGGER_START:
0228     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0229     case SNDRV_PCM_TRIGGER_RESUME:
0230         start = true;
0231         break;
0232     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0233     case SNDRV_PCM_TRIGGER_SUSPEND:
0234     case SNDRV_PCM_TRIGGER_STOP:
0235         start = false;
0236         break;
0237     default:
0238         return -EINVAL;
0239     }
0240 
0241     snd_pcm_group_for_each_entry(s, substream) {
0242         if (s->pcm->card != substream->pcm->card)
0243             continue;
0244         azx_dev = get_azx_dev(s);
0245         sbits |= 1 << azx_dev->core.index;
0246         snd_pcm_trigger_done(s, substream);
0247     }
0248 
0249     spin_lock(&bus->reg_lock);
0250 
0251     /* first, set SYNC bits of corresponding streams */
0252     snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
0253 
0254     snd_pcm_group_for_each_entry(s, substream) {
0255         if (s->pcm->card != substream->pcm->card)
0256             continue;
0257         azx_dev = get_azx_dev(s);
0258         if (start) {
0259             azx_dev->insufficient = 1;
0260             snd_hdac_stream_start(azx_stream(azx_dev), true);
0261         } else {
0262             snd_hdac_stream_stop(azx_stream(azx_dev));
0263         }
0264     }
0265     spin_unlock(&bus->reg_lock);
0266 
0267     snd_hdac_stream_sync(hstr, start, sbits);
0268 
0269     spin_lock(&bus->reg_lock);
0270     /* reset SYNC bits */
0271     snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
0272     if (start)
0273         snd_hdac_stream_timecounter_init(hstr, sbits);
0274     spin_unlock(&bus->reg_lock);
0275     return 0;
0276 }
0277 
0278 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
0279 {
0280     return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
0281 }
0282 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
0283 
0284 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
0285 {
0286     return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
0287 }
0288 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
0289 
0290 unsigned int azx_get_position(struct azx *chip,
0291                   struct azx_dev *azx_dev)
0292 {
0293     struct snd_pcm_substream *substream = azx_dev->core.substream;
0294     unsigned int pos;
0295     int stream = substream->stream;
0296     int delay = 0;
0297 
0298     if (chip->get_position[stream])
0299         pos = chip->get_position[stream](chip, azx_dev);
0300     else /* use the position buffer as default */
0301         pos = azx_get_pos_posbuf(chip, azx_dev);
0302 
0303     if (pos >= azx_dev->core.bufsize)
0304         pos = 0;
0305 
0306     if (substream->runtime) {
0307         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0308         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
0309 
0310         if (chip->get_delay[stream])
0311             delay += chip->get_delay[stream](chip, azx_dev, pos);
0312         if (hinfo->ops.get_delay)
0313             delay += hinfo->ops.get_delay(hinfo, apcm->codec,
0314                               substream);
0315         substream->runtime->delay = delay;
0316     }
0317 
0318     trace_azx_get_position(chip, azx_dev, pos, delay);
0319     return pos;
0320 }
0321 EXPORT_SYMBOL_GPL(azx_get_position);
0322 
0323 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
0324 {
0325     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0326     struct azx *chip = apcm->chip;
0327     struct azx_dev *azx_dev = get_azx_dev(substream);
0328     return bytes_to_frames(substream->runtime,
0329                    azx_get_position(chip, azx_dev));
0330 }
0331 
0332 /*
0333  * azx_scale64: Scale base by mult/div while not overflowing sanely
0334  *
0335  * Derived from scale64_check_overflow in kernel/time/timekeeping.c
0336  *
0337  * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
0338  * is about 384307 ie ~4.5 days.
0339  *
0340  * This scales the calculation so that overflow will happen but after 2^64 /
0341  * 48000 secs, which is pretty large!
0342  *
0343  * In caln below:
0344  *  base may overflow, but since there isn’t any additional division
0345  *  performed on base it’s OK
0346  *  rem can’t overflow because both are 32-bit values
0347  */
0348 
0349 #ifdef CONFIG_X86
0350 static u64 azx_scale64(u64 base, u32 num, u32 den)
0351 {
0352     u64 rem;
0353 
0354     rem = do_div(base, den);
0355 
0356     base *= num;
0357     rem *= num;
0358 
0359     do_div(rem, den);
0360 
0361     return base + rem;
0362 }
0363 
0364 static int azx_get_sync_time(ktime_t *device,
0365         struct system_counterval_t *system, void *ctx)
0366 {
0367     struct snd_pcm_substream *substream = ctx;
0368     struct azx_dev *azx_dev = get_azx_dev(substream);
0369     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0370     struct azx *chip = apcm->chip;
0371     struct snd_pcm_runtime *runtime;
0372     u64 ll_counter, ll_counter_l, ll_counter_h;
0373     u64 tsc_counter, tsc_counter_l, tsc_counter_h;
0374     u32 wallclk_ctr, wallclk_cycles;
0375     bool direction;
0376     u32 dma_select;
0377     u32 timeout;
0378     u32 retry_count = 0;
0379 
0380     runtime = substream->runtime;
0381 
0382     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0383         direction = 1;
0384     else
0385         direction = 0;
0386 
0387     /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
0388     do {
0389         timeout = 100;
0390         dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
0391                     (azx_dev->core.stream_tag - 1);
0392         snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
0393 
0394         /* Enable the capture */
0395         snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
0396 
0397         while (timeout) {
0398             if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
0399                         GTSCC_TSCCD_MASK)
0400                 break;
0401 
0402             timeout--;
0403         }
0404 
0405         if (!timeout) {
0406             dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
0407             return -EIO;
0408         }
0409 
0410         /* Read wall clock counter */
0411         wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
0412 
0413         /* Read TSC counter */
0414         tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
0415         tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
0416 
0417         /* Read Link counter */
0418         ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
0419         ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
0420 
0421         /* Ack: registers read done */
0422         snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
0423 
0424         tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
0425                         tsc_counter_l;
0426 
0427         ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
0428         wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
0429 
0430         /*
0431          * An error occurs near frame "rollover". The clocks in
0432          * frame value indicates whether this error may have
0433          * occurred. Here we use the value of 10 i.e.,
0434          * HDA_MAX_CYCLE_OFFSET
0435          */
0436         if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
0437                     && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
0438             break;
0439 
0440         /*
0441          * Sleep before we read again, else we may again get
0442          * value near to MAX_CYCLE. Try to sleep for different
0443          * amount of time so we dont hit the same number again
0444          */
0445         udelay(retry_count++);
0446 
0447     } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
0448 
0449     if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
0450         dev_err_ratelimited(chip->card->dev,
0451             "Error in WALFCC cycle count\n");
0452         return -EIO;
0453     }
0454 
0455     *device = ns_to_ktime(azx_scale64(ll_counter,
0456                 NSEC_PER_SEC, runtime->rate));
0457     *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
0458                    ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
0459 
0460     *system = convert_art_to_tsc(tsc_counter);
0461 
0462     return 0;
0463 }
0464 
0465 #else
0466 static int azx_get_sync_time(ktime_t *device,
0467         struct system_counterval_t *system, void *ctx)
0468 {
0469     return -ENXIO;
0470 }
0471 #endif
0472 
0473 static int azx_get_crosststamp(struct snd_pcm_substream *substream,
0474                   struct system_device_crosststamp *xtstamp)
0475 {
0476     return get_device_system_crosststamp(azx_get_sync_time,
0477                     substream, NULL, xtstamp);
0478 }
0479 
0480 static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
0481                 struct snd_pcm_audio_tstamp_config *ts)
0482 {
0483     if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
0484         if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
0485             return true;
0486 
0487     return false;
0488 }
0489 
0490 static int azx_get_time_info(struct snd_pcm_substream *substream,
0491             struct timespec64 *system_ts, struct timespec64 *audio_ts,
0492             struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
0493             struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
0494 {
0495     struct azx_dev *azx_dev = get_azx_dev(substream);
0496     struct snd_pcm_runtime *runtime = substream->runtime;
0497     struct system_device_crosststamp xtstamp;
0498     int ret;
0499     u64 nsec;
0500 
0501     if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
0502         (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
0503 
0504         snd_pcm_gettime(substream->runtime, system_ts);
0505 
0506         nsec = timecounter_read(&azx_dev->core.tc);
0507         if (audio_tstamp_config->report_delay)
0508             nsec = azx_adjust_codec_delay(substream, nsec);
0509 
0510         *audio_ts = ns_to_timespec64(nsec);
0511 
0512         audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
0513         audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
0514         audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
0515 
0516     } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
0517 
0518         ret = azx_get_crosststamp(substream, &xtstamp);
0519         if (ret)
0520             return ret;
0521 
0522         switch (runtime->tstamp_type) {
0523         case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
0524             return -EINVAL;
0525 
0526         case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
0527             *system_ts = ktime_to_timespec64(xtstamp.sys_monoraw);
0528             break;
0529 
0530         default:
0531             *system_ts = ktime_to_timespec64(xtstamp.sys_realtime);
0532             break;
0533 
0534         }
0535 
0536         *audio_ts = ktime_to_timespec64(xtstamp.device);
0537 
0538         audio_tstamp_report->actual_type =
0539             SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
0540         audio_tstamp_report->accuracy_report = 1;
0541         /* 24 MHz WallClock == 42ns resolution */
0542         audio_tstamp_report->accuracy = 42;
0543 
0544     } else {
0545         audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
0546     }
0547 
0548     return 0;
0549 }
0550 
0551 static const struct snd_pcm_hardware azx_pcm_hw = {
0552     .info =         (SNDRV_PCM_INFO_MMAP |
0553                  SNDRV_PCM_INFO_INTERLEAVED |
0554                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
0555                  SNDRV_PCM_INFO_MMAP_VALID |
0556                  /* No full-resume yet implemented */
0557                  /* SNDRV_PCM_INFO_RESUME |*/
0558                  SNDRV_PCM_INFO_PAUSE |
0559                  SNDRV_PCM_INFO_SYNC_START |
0560                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
0561                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
0562                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
0563     .formats =      SNDRV_PCM_FMTBIT_S16_LE,
0564     .rates =        SNDRV_PCM_RATE_48000,
0565     .rate_min =     48000,
0566     .rate_max =     48000,
0567     .channels_min =     2,
0568     .channels_max =     2,
0569     .buffer_bytes_max = AZX_MAX_BUF_SIZE,
0570     .period_bytes_min = 128,
0571     .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
0572     .periods_min =      2,
0573     .periods_max =      AZX_MAX_FRAG,
0574     .fifo_size =        0,
0575 };
0576 
0577 static int azx_pcm_open(struct snd_pcm_substream *substream)
0578 {
0579     struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
0580     struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
0581     struct azx *chip = apcm->chip;
0582     struct azx_dev *azx_dev;
0583     struct snd_pcm_runtime *runtime = substream->runtime;
0584     int err;
0585     int buff_step;
0586 
0587     snd_hda_codec_pcm_get(apcm->info);
0588     mutex_lock(&chip->open_mutex);
0589     azx_dev = azx_assign_device(chip, substream);
0590     trace_azx_pcm_open(chip, azx_dev);
0591     if (azx_dev == NULL) {
0592         err = -EBUSY;
0593         goto unlock;
0594     }
0595     runtime->private_data = azx_dev;
0596 
0597     runtime->hw = azx_pcm_hw;
0598     if (chip->gts_present)
0599         runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
0600     runtime->hw.channels_min = hinfo->channels_min;
0601     runtime->hw.channels_max = hinfo->channels_max;
0602     runtime->hw.formats = hinfo->formats;
0603     runtime->hw.rates = hinfo->rates;
0604     snd_pcm_limit_hw_rates(runtime);
0605     snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
0606 
0607     /* avoid wrap-around with wall-clock */
0608     snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
0609                      20,
0610                      178000000);
0611 
0612     if (chip->align_buffer_size)
0613         /* constrain buffer sizes to be multiple of 128
0614            bytes. This is more efficient in terms of memory
0615            access but isn't required by the HDA spec and
0616            prevents users from specifying exact period/buffer
0617            sizes. For example for 44.1kHz, a period size set
0618            to 20ms will be rounded to 19.59ms. */
0619         buff_step = 128;
0620     else
0621         /* Don't enforce steps on buffer sizes, still need to
0622            be multiple of 4 bytes (HDA spec). Tested on Intel
0623            HDA controllers, may not work on all devices where
0624            option needs to be disabled */
0625         buff_step = 4;
0626 
0627     snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
0628                    buff_step);
0629     snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
0630                    buff_step);
0631     snd_hda_power_up(apcm->codec);
0632     if (hinfo->ops.open)
0633         err = hinfo->ops.open(hinfo, apcm->codec, substream);
0634     else
0635         err = -ENODEV;
0636     if (err < 0) {
0637         azx_release_device(azx_dev);
0638         goto powerdown;
0639     }
0640     snd_pcm_limit_hw_rates(runtime);
0641     /* sanity check */
0642     if (snd_BUG_ON(!runtime->hw.channels_min) ||
0643         snd_BUG_ON(!runtime->hw.channels_max) ||
0644         snd_BUG_ON(!runtime->hw.formats) ||
0645         snd_BUG_ON(!runtime->hw.rates)) {
0646         azx_release_device(azx_dev);
0647         if (hinfo->ops.close)
0648             hinfo->ops.close(hinfo, apcm->codec, substream);
0649         err = -EINVAL;
0650         goto powerdown;
0651     }
0652 
0653     /* disable LINK_ATIME timestamps for capture streams
0654        until we figure out how to handle digital inputs */
0655     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
0656         runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
0657         runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
0658     }
0659 
0660     snd_pcm_set_sync(substream);
0661     mutex_unlock(&chip->open_mutex);
0662     return 0;
0663 
0664  powerdown:
0665     snd_hda_power_down(apcm->codec);
0666  unlock:
0667     mutex_unlock(&chip->open_mutex);
0668     snd_hda_codec_pcm_put(apcm->info);
0669     return err;
0670 }
0671 
0672 static const struct snd_pcm_ops azx_pcm_ops = {
0673     .open = azx_pcm_open,
0674     .close = azx_pcm_close,
0675     .hw_params = azx_pcm_hw_params,
0676     .hw_free = azx_pcm_hw_free,
0677     .prepare = azx_pcm_prepare,
0678     .trigger = azx_pcm_trigger,
0679     .pointer = azx_pcm_pointer,
0680     .get_time_info =  azx_get_time_info,
0681 };
0682 
0683 static void azx_pcm_free(struct snd_pcm *pcm)
0684 {
0685     struct azx_pcm *apcm = pcm->private_data;
0686     if (apcm) {
0687         list_del(&apcm->list);
0688         apcm->info->pcm = NULL;
0689         kfree(apcm);
0690     }
0691 }
0692 
0693 #define MAX_PREALLOC_SIZE   (32 * 1024 * 1024)
0694 
0695 int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
0696                   struct hda_pcm *cpcm)
0697 {
0698     struct hdac_bus *bus = &_bus->core;
0699     struct azx *chip = bus_to_azx(bus);
0700     struct snd_pcm *pcm;
0701     struct azx_pcm *apcm;
0702     int pcm_dev = cpcm->device;
0703     unsigned int size;
0704     int s, err;
0705     int type = SNDRV_DMA_TYPE_DEV_SG;
0706 
0707     list_for_each_entry(apcm, &chip->pcm_list, list) {
0708         if (apcm->pcm->device == pcm_dev) {
0709             dev_err(chip->card->dev, "PCM %d already exists\n",
0710                 pcm_dev);
0711             return -EBUSY;
0712         }
0713     }
0714     err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
0715               cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
0716               cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
0717               &pcm);
0718     if (err < 0)
0719         return err;
0720     strscpy(pcm->name, cpcm->name, sizeof(pcm->name));
0721     apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
0722     if (apcm == NULL) {
0723         snd_device_free(chip->card, pcm);
0724         return -ENOMEM;
0725     }
0726     apcm->chip = chip;
0727     apcm->pcm = pcm;
0728     apcm->codec = codec;
0729     apcm->info = cpcm;
0730     pcm->private_data = apcm;
0731     pcm->private_free = azx_pcm_free;
0732     if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
0733         pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
0734     list_add_tail(&apcm->list, &chip->pcm_list);
0735     cpcm->pcm = pcm;
0736     for (s = 0; s < 2; s++) {
0737         if (cpcm->stream[s].substreams)
0738             snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
0739     }
0740     /* buffer pre-allocation */
0741     size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
0742     if (size > MAX_PREALLOC_SIZE)
0743         size = MAX_PREALLOC_SIZE;
0744     if (chip->uc_buffer)
0745         type = SNDRV_DMA_TYPE_DEV_WC_SG;
0746     snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev,
0747                        size, MAX_PREALLOC_SIZE);
0748     return 0;
0749 }
0750 
0751 static unsigned int azx_command_addr(u32 cmd)
0752 {
0753     unsigned int addr = cmd >> 28;
0754 
0755     if (addr >= AZX_MAX_CODECS) {
0756         snd_BUG();
0757         addr = 0;
0758     }
0759 
0760     return addr;
0761 }
0762 
0763 /* receive a response */
0764 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
0765                  unsigned int *res)
0766 {
0767     struct azx *chip = bus_to_azx(bus);
0768     struct hda_bus *hbus = &chip->bus;
0769     int err;
0770 
0771  again:
0772     err = snd_hdac_bus_get_response(bus, addr, res);
0773     if (!err)
0774         return 0;
0775 
0776     if (hbus->no_response_fallback)
0777         return -EIO;
0778 
0779     if (!bus->polling_mode) {
0780         dev_warn(chip->card->dev,
0781              "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
0782              bus->last_cmd[addr]);
0783         bus->polling_mode = 1;
0784         goto again;
0785     }
0786 
0787     if (chip->msi) {
0788         dev_warn(chip->card->dev,
0789              "No response from codec, disabling MSI: last cmd=0x%08x\n",
0790              bus->last_cmd[addr]);
0791         if (chip->ops->disable_msi_reset_irq &&
0792             chip->ops->disable_msi_reset_irq(chip) < 0)
0793             return -EIO;
0794         goto again;
0795     }
0796 
0797     if (chip->probing) {
0798         /* If this critical timeout happens during the codec probing
0799          * phase, this is likely an access to a non-existing codec
0800          * slot.  Better to return an error and reset the system.
0801          */
0802         return -EIO;
0803     }
0804 
0805     /* no fallback mechanism? */
0806     if (!chip->fallback_to_single_cmd)
0807         return -EIO;
0808 
0809     /* a fatal communication error; need either to reset or to fallback
0810      * to the single_cmd mode
0811      */
0812     if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
0813         hbus->response_reset = 1;
0814         dev_err(chip->card->dev,
0815             "No response from codec, resetting bus: last cmd=0x%08x\n",
0816             bus->last_cmd[addr]);
0817         return -EAGAIN; /* give a chance to retry */
0818     }
0819 
0820     dev_err(chip->card->dev,
0821         "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
0822         bus->last_cmd[addr]);
0823     chip->single_cmd = 1;
0824     hbus->response_reset = 0;
0825     snd_hdac_bus_stop_cmd_io(bus);
0826     return -EIO;
0827 }
0828 
0829 /*
0830  * Use the single immediate command instead of CORB/RIRB for simplicity
0831  *
0832  * Note: according to Intel, this is not preferred use.  The command was
0833  *       intended for the BIOS only, and may get confused with unsolicited
0834  *       responses.  So, we shouldn't use it for normal operation from the
0835  *       driver.
0836  *       I left the codes, however, for debugging/testing purposes.
0837  */
0838 
0839 /* receive a response */
0840 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
0841 {
0842     int timeout = 50;
0843 
0844     while (timeout--) {
0845         /* check IRV busy bit */
0846         if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
0847             /* reuse rirb.res as the response return value */
0848             azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
0849             return 0;
0850         }
0851         udelay(1);
0852     }
0853     if (printk_ratelimit())
0854         dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
0855             azx_readw(chip, IRS));
0856     azx_bus(chip)->rirb.res[addr] = -1;
0857     return -EIO;
0858 }
0859 
0860 /* send a command */
0861 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
0862 {
0863     struct azx *chip = bus_to_azx(bus);
0864     unsigned int addr = azx_command_addr(val);
0865     int timeout = 50;
0866 
0867     bus->last_cmd[azx_command_addr(val)] = val;
0868     while (timeout--) {
0869         /* check ICB busy bit */
0870         if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
0871             /* Clear IRV valid bit */
0872             azx_writew(chip, IRS, azx_readw(chip, IRS) |
0873                    AZX_IRS_VALID);
0874             azx_writel(chip, IC, val);
0875             azx_writew(chip, IRS, azx_readw(chip, IRS) |
0876                    AZX_IRS_BUSY);
0877             return azx_single_wait_for_response(chip, addr);
0878         }
0879         udelay(1);
0880     }
0881     if (printk_ratelimit())
0882         dev_dbg(chip->card->dev,
0883             "send_cmd timeout: IRS=0x%x, val=0x%x\n",
0884             azx_readw(chip, IRS), val);
0885     return -EIO;
0886 }
0887 
0888 /* receive a response */
0889 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
0890                    unsigned int *res)
0891 {
0892     if (res)
0893         *res = bus->rirb.res[addr];
0894     return 0;
0895 }
0896 
0897 /*
0898  * The below are the main callbacks from hda_codec.
0899  *
0900  * They are just the skeleton to call sub-callbacks according to the
0901  * current setting of chip->single_cmd.
0902  */
0903 
0904 /* send a command */
0905 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
0906 {
0907     struct azx *chip = bus_to_azx(bus);
0908 
0909     if (chip->disabled)
0910         return 0;
0911     if (chip->single_cmd)
0912         return azx_single_send_cmd(bus, val);
0913     else
0914         return snd_hdac_bus_send_cmd(bus, val);
0915 }
0916 
0917 /* get a response */
0918 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
0919                 unsigned int *res)
0920 {
0921     struct azx *chip = bus_to_azx(bus);
0922 
0923     if (chip->disabled)
0924         return 0;
0925     if (chip->single_cmd)
0926         return azx_single_get_response(bus, addr, res);
0927     else
0928         return azx_rirb_get_response(bus, addr, res);
0929 }
0930 
0931 static const struct hdac_bus_ops bus_core_ops = {
0932     .command = azx_send_cmd,
0933     .get_response = azx_get_response,
0934 };
0935 
0936 #ifdef CONFIG_SND_HDA_DSP_LOADER
0937 /*
0938  * DSP loading code (e.g. for CA0132)
0939  */
0940 
0941 /* use the first stream for loading DSP */
0942 static struct azx_dev *
0943 azx_get_dsp_loader_dev(struct azx *chip)
0944 {
0945     struct hdac_bus *bus = azx_bus(chip);
0946     struct hdac_stream *s;
0947 
0948     list_for_each_entry(s, &bus->stream_list, list)
0949         if (s->index == chip->playback_index_offset)
0950             return stream_to_azx_dev(s);
0951 
0952     return NULL;
0953 }
0954 
0955 int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
0956                    unsigned int byte_size,
0957                    struct snd_dma_buffer *bufp)
0958 {
0959     struct hdac_bus *bus = &codec->bus->core;
0960     struct azx *chip = bus_to_azx(bus);
0961     struct azx_dev *azx_dev;
0962     struct hdac_stream *hstr;
0963     bool saved = false;
0964     int err;
0965 
0966     azx_dev = azx_get_dsp_loader_dev(chip);
0967     hstr = azx_stream(azx_dev);
0968     spin_lock_irq(&bus->reg_lock);
0969     if (hstr->opened) {
0970         chip->saved_azx_dev = *azx_dev;
0971         saved = true;
0972     }
0973     spin_unlock_irq(&bus->reg_lock);
0974 
0975     err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
0976     if (err < 0) {
0977         spin_lock_irq(&bus->reg_lock);
0978         if (saved)
0979             *azx_dev = chip->saved_azx_dev;
0980         spin_unlock_irq(&bus->reg_lock);
0981         return err;
0982     }
0983 
0984     hstr->prepared = 0;
0985     return err;
0986 }
0987 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
0988 
0989 void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
0990 {
0991     struct hdac_bus *bus = &codec->bus->core;
0992     struct azx *chip = bus_to_azx(bus);
0993     struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
0994 
0995     snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
0996 }
0997 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
0998 
0999 void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1000                     struct snd_dma_buffer *dmab)
1001 {
1002     struct hdac_bus *bus = &codec->bus->core;
1003     struct azx *chip = bus_to_azx(bus);
1004     struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1005     struct hdac_stream *hstr = azx_stream(azx_dev);
1006 
1007     if (!dmab->area || !hstr->locked)
1008         return;
1009 
1010     snd_hdac_dsp_cleanup(hstr, dmab);
1011     spin_lock_irq(&bus->reg_lock);
1012     if (hstr->opened)
1013         *azx_dev = chip->saved_azx_dev;
1014     hstr->locked = false;
1015     spin_unlock_irq(&bus->reg_lock);
1016 }
1017 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1018 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1019 
1020 /*
1021  * reset and start the controller registers
1022  */
1023 void azx_init_chip(struct azx *chip, bool full_reset)
1024 {
1025     if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1026         /* correct RINTCNT for CXT */
1027         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1028             azx_writew(chip, RINTCNT, 0xc0);
1029     }
1030 }
1031 EXPORT_SYMBOL_GPL(azx_init_chip);
1032 
1033 void azx_stop_all_streams(struct azx *chip)
1034 {
1035     struct hdac_bus *bus = azx_bus(chip);
1036     struct hdac_stream *s;
1037 
1038     list_for_each_entry(s, &bus->stream_list, list)
1039         snd_hdac_stream_stop(s);
1040 }
1041 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1042 
1043 void azx_stop_chip(struct azx *chip)
1044 {
1045     snd_hdac_bus_stop_chip(azx_bus(chip));
1046 }
1047 EXPORT_SYMBOL_GPL(azx_stop_chip);
1048 
1049 /*
1050  * interrupt handler
1051  */
1052 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1053 {
1054     struct azx *chip = bus_to_azx(bus);
1055     struct azx_dev *azx_dev = stream_to_azx_dev(s);
1056 
1057     /* check whether this IRQ is really acceptable */
1058     if (!chip->ops->position_check ||
1059         chip->ops->position_check(chip, azx_dev)) {
1060         spin_unlock(&bus->reg_lock);
1061         snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1062         spin_lock(&bus->reg_lock);
1063     }
1064 }
1065 
1066 irqreturn_t azx_interrupt(int irq, void *dev_id)
1067 {
1068     struct azx *chip = dev_id;
1069     struct hdac_bus *bus = azx_bus(chip);
1070     u32 status;
1071     bool active, handled = false;
1072     int repeat = 0; /* count for avoiding endless loop */
1073 
1074 #ifdef CONFIG_PM
1075     if (azx_has_pm_runtime(chip))
1076         if (!pm_runtime_active(chip->card->dev))
1077             return IRQ_NONE;
1078 #endif
1079 
1080     spin_lock(&bus->reg_lock);
1081 
1082     if (chip->disabled)
1083         goto unlock;
1084 
1085     do {
1086         status = azx_readl(chip, INTSTS);
1087         if (status == 0 || status == 0xffffffff)
1088             break;
1089 
1090         handled = true;
1091         active = false;
1092         if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1093             active = true;
1094 
1095         status = azx_readb(chip, RIRBSTS);
1096         if (status & RIRB_INT_MASK) {
1097             /*
1098              * Clearing the interrupt status here ensures that no
1099              * interrupt gets masked after the RIRB wp is read in
1100              * snd_hdac_bus_update_rirb. This avoids a possible
1101              * race condition where codec response in RIRB may
1102              * remain unserviced by IRQ, eventually falling back
1103              * to polling mode in azx_rirb_get_response.
1104              */
1105             azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1106             active = true;
1107             if (status & RIRB_INT_RESPONSE) {
1108                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1109                     udelay(80);
1110                 snd_hdac_bus_update_rirb(bus);
1111             }
1112         }
1113     } while (active && ++repeat < 10);
1114 
1115  unlock:
1116     spin_unlock(&bus->reg_lock);
1117 
1118     return IRQ_RETVAL(handled);
1119 }
1120 EXPORT_SYMBOL_GPL(azx_interrupt);
1121 
1122 /*
1123  * Codec initerface
1124  */
1125 
1126 /*
1127  * Probe the given codec address
1128  */
1129 static int probe_codec(struct azx *chip, int addr)
1130 {
1131     unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1132         (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1133     struct hdac_bus *bus = azx_bus(chip);
1134     int err;
1135     unsigned int res = -1;
1136 
1137     mutex_lock(&bus->cmd_mutex);
1138     chip->probing = 1;
1139     azx_send_cmd(bus, cmd);
1140     err = azx_get_response(bus, addr, &res);
1141     chip->probing = 0;
1142     mutex_unlock(&bus->cmd_mutex);
1143     if (err < 0 || res == -1)
1144         return -EIO;
1145     dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1146     return 0;
1147 }
1148 
1149 void snd_hda_bus_reset(struct hda_bus *bus)
1150 {
1151     struct azx *chip = bus_to_azx(&bus->core);
1152 
1153     bus->in_reset = 1;
1154     azx_stop_chip(chip);
1155     azx_init_chip(chip, true);
1156     if (bus->core.chip_init)
1157         snd_hda_bus_reset_codecs(bus);
1158     bus->in_reset = 0;
1159 }
1160 
1161 /* HD-audio bus initialization */
1162 int azx_bus_init(struct azx *chip, const char *model)
1163 {
1164     struct hda_bus *bus = &chip->bus;
1165     int err;
1166 
1167     err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops);
1168     if (err < 0)
1169         return err;
1170 
1171     bus->card = chip->card;
1172     mutex_init(&bus->prepare_mutex);
1173     bus->pci = chip->pci;
1174     bus->modelname = model;
1175     bus->mixer_assigned = -1;
1176     bus->core.snoop = azx_snoop(chip);
1177     if (chip->get_position[0] != azx_get_pos_lpib ||
1178         chip->get_position[1] != azx_get_pos_lpib)
1179         bus->core.use_posbuf = true;
1180     bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1181     if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1182         bus->core.corbrp_self_clear = true;
1183 
1184     if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1185         bus->core.align_bdle_4k = true;
1186 
1187     /* enable sync_write flag for stable communication as default */
1188     bus->core.sync_write = 1;
1189 
1190     return 0;
1191 }
1192 EXPORT_SYMBOL_GPL(azx_bus_init);
1193 
1194 /* Probe codecs */
1195 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1196 {
1197     struct hdac_bus *bus = azx_bus(chip);
1198     int c, codecs, err;
1199 
1200     codecs = 0;
1201     if (!max_slots)
1202         max_slots = AZX_DEFAULT_CODECS;
1203 
1204     /* First try to probe all given codec slots */
1205     for (c = 0; c < max_slots; c++) {
1206         if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1207             if (probe_codec(chip, c) < 0) {
1208                 /* Some BIOSen give you wrong codec addresses
1209                  * that don't exist
1210                  */
1211                 dev_warn(chip->card->dev,
1212                      "Codec #%d probe error; disabling it...\n", c);
1213                 bus->codec_mask &= ~(1 << c);
1214                 /* More badly, accessing to a non-existing
1215                  * codec often screws up the controller chip,
1216                  * and disturbs the further communications.
1217                  * Thus if an error occurs during probing,
1218                  * better to reset the controller chip to
1219                  * get back to the sanity state.
1220                  */
1221                 azx_stop_chip(chip);
1222                 azx_init_chip(chip, true);
1223             }
1224         }
1225     }
1226 
1227     /* Then create codec instances */
1228     for (c = 0; c < max_slots; c++) {
1229         if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1230             struct hda_codec *codec;
1231             err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1232             if (err < 0)
1233                 continue;
1234             codec->jackpoll_interval = chip->jackpoll_interval;
1235             codec->beep_mode = chip->beep_mode;
1236             codecs++;
1237         }
1238     }
1239     if (!codecs) {
1240         dev_err(chip->card->dev, "no codecs initialized\n");
1241         return -ENXIO;
1242     }
1243     return 0;
1244 }
1245 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1246 
1247 /* configure each codec instance */
1248 int azx_codec_configure(struct azx *chip)
1249 {
1250     struct hda_codec *codec, *next;
1251     int success = 0;
1252 
1253     list_for_each_codec(codec, &chip->bus) {
1254         if (!snd_hda_codec_configure(codec))
1255             success++;
1256     }
1257 
1258     if (success) {
1259         /* unregister failed codecs if any codec has been probed */
1260         list_for_each_codec_safe(codec, next, &chip->bus) {
1261             if (!codec->configured) {
1262                 codec_err(codec, "Unable to configure, disabling\n");
1263                 snd_hdac_device_unregister(&codec->core);
1264             }
1265         }
1266     }
1267 
1268     return success ? 0 : -ENODEV;
1269 }
1270 EXPORT_SYMBOL_GPL(azx_codec_configure);
1271 
1272 static int stream_direction(struct azx *chip, unsigned char index)
1273 {
1274     if (index >= chip->capture_index_offset &&
1275         index < chip->capture_index_offset + chip->capture_streams)
1276         return SNDRV_PCM_STREAM_CAPTURE;
1277     return SNDRV_PCM_STREAM_PLAYBACK;
1278 }
1279 
1280 /* initialize SD streams */
1281 int azx_init_streams(struct azx *chip)
1282 {
1283     int i;
1284     int stream_tags[2] = { 0, 0 };
1285 
1286     /* initialize each stream (aka device)
1287      * assign the starting bdl address to each stream (device)
1288      * and initialize
1289      */
1290     for (i = 0; i < chip->num_streams; i++) {
1291         struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1292         int dir, tag;
1293 
1294         if (!azx_dev)
1295             return -ENOMEM;
1296 
1297         dir = stream_direction(chip, i);
1298         /* stream tag must be unique throughout
1299          * the stream direction group,
1300          * valid values 1...15
1301          * use separate stream tag if the flag
1302          * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1303          */
1304         if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1305             tag = ++stream_tags[dir];
1306         else
1307             tag = i + 1;
1308         snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1309                      i, dir, tag);
1310     }
1311 
1312     return 0;
1313 }
1314 EXPORT_SYMBOL_GPL(azx_init_streams);
1315 
1316 void azx_free_streams(struct azx *chip)
1317 {
1318     struct hdac_bus *bus = azx_bus(chip);
1319     struct hdac_stream *s;
1320 
1321     while (!list_empty(&bus->stream_list)) {
1322         s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1323         list_del(&s->list);
1324         kfree(stream_to_azx_dev(s));
1325     }
1326 }
1327 EXPORT_SYMBOL_GPL(azx_free_streams);
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