pci/echoaudio/mona_dsp.c

0001 /****************************************************************************
0002
0003    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
0004    All rights reserved
0005    www.echoaudio.com
0006
0007    This file is part of Echo Digital Audio's generic driver library.
0008
0009    Echo Digital Audio's generic driver library is free software;
0010    you can redistribute it and/or modify it under the terms of
0011    the GNU General Public License as published by the Free Software
0012    Foundation.
0013
0014    This program is distributed in the hope that it will be useful,
0015    but WITHOUT ANY WARRANTY; without even the implied warranty of
0016    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0017    GNU General Public License for more details.
0018
0019    You should have received a copy of the GNU General Public License
0020    along with this program; if not, write to the Free Software
0021    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
0022    MA  02111-1307, USA.
0023
0024    *************************************************************************
0025
0026  Translation from C++ and adaptation for use in ALSA-Driver
0027  were made by Giuliano Pochini <pochini@shiny.it>
0028
0029 ****************************************************************************/
0030
0031
0032 static int write_control_reg(struct echoaudio *chip, u32 value, char force);
0033 static int set_input_clock(struct echoaudio *chip, u16 clock);
0034 static int set_professional_spdif(struct echoaudio *chip, char prof);
0035 static int set_digital_mode(struct echoaudio *chip, u8 mode);
0036 static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
0037 static int check_asic_status(struct echoaudio *chip);
0038
0039
0040 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
0041 {
0042     int err;
0043
0044     if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA))
0045         return -ENODEV;
0046
0047     err = init_dsp_comm_page(chip);
0048     if (err) {
0049         dev_err(chip->card->dev,
0050             "init_hw - could not initialize DSP comm page\n");
0051         return err;
0052     }
0053
0054     chip->device_id = device_id;
0055     chip->subdevice_id = subdevice_id;
0056     chip->bad_board = true;
0057     chip->input_clock_types =
0058         ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
0059         ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
0060     chip->digital_modes =
0061         ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
0062         ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
0063         ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
0064
0065     /* Mona comes in both '301 and '361 flavors */
0066     if (chip->device_id == DEVICE_ID_56361)
0067         chip->dsp_code_to_load = FW_MONA_361_DSP;
0068     else
0069         chip->dsp_code_to_load = FW_MONA_301_DSP;
0070
0071     err = load_firmware(chip);
0072     if (err < 0)
0073         return err;
0074     chip->bad_board = false;
0075
0076     return err;
0077 }
0078
0079
0080
0081 static int set_mixer_defaults(struct echoaudio *chip)
0082 {
0083     chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
0084     chip->professional_spdif = false;
0085     chip->digital_in_automute = true;
0086     return init_line_levels(chip);
0087 }
0088
0089
0090
0091 static u32 detect_input_clocks(const struct echoaudio *chip)
0092 {
0093     u32 clocks_from_dsp, clock_bits;
0094
0095     /* Map the DSP clock detect bits to the generic driver clock
0096        detect bits */
0097     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0098
0099     clock_bits = ECHO_CLOCK_BIT_INTERNAL;
0100
0101     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
0102         clock_bits |= ECHO_CLOCK_BIT_SPDIF;
0103
0104     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
0105         clock_bits |= ECHO_CLOCK_BIT_ADAT;
0106
0107     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
0108         clock_bits |= ECHO_CLOCK_BIT_WORD;
0109
0110     return clock_bits;
0111 }
0112
0113
0114
0115 /* Mona has an ASIC on the PCI card and another ASIC in the external box;
0116 both need to be loaded. */
0117 static int load_asic(struct echoaudio *chip)
0118 {
0119     u32 control_reg;
0120     int err;
0121     short asic;
0122
0123     if (chip->asic_loaded)
0124         return 0;
0125
0126     mdelay(10);
0127
0128     if (chip->device_id == DEVICE_ID_56361)
0129         asic = FW_MONA_361_1_ASIC48;
0130     else
0131         asic = FW_MONA_301_1_ASIC48;
0132
0133     err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
0134     if (err < 0)
0135         return err;
0136
0137     chip->asic_code = asic;
0138     mdelay(10);
0139
0140     /* Do the external one */
0141     err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
0142                 FW_MONA_2_ASIC);
0143     if (err < 0)
0144         return err;
0145
0146     mdelay(10);
0147     err = check_asic_status(chip);
0148
0149     /* Set up the control register if the load succeeded -
0150        48 kHz, internal clock, S/PDIF RCA mode */
0151     if (!err) {
0152         control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
0153         err = write_control_reg(chip, control_reg, true);
0154     }
0155
0156     return err;
0157 }
0158
0159
0160
0161 /* Depending on what digital mode you want, Mona needs different ASICs
0162 loaded.  This function checks the ASIC needed for the new mode and sees
0163 if it matches the one already loaded. */
0164 static int switch_asic(struct echoaudio *chip, char double_speed)
0165 {
0166     int err;
0167     short asic;
0168
0169     /* Check the clock detect bits to see if this is
0170     a single-speed clock or a double-speed clock; load
0171     a new ASIC if necessary. */
0172     if (chip->device_id == DEVICE_ID_56361) {
0173         if (double_speed)
0174             asic = FW_MONA_361_1_ASIC96;
0175         else
0176             asic = FW_MONA_361_1_ASIC48;
0177     } else {
0178         if (double_speed)
0179             asic = FW_MONA_301_1_ASIC96;
0180         else
0181             asic = FW_MONA_301_1_ASIC48;
0182     }
0183
0184     if (asic != chip->asic_code) {
0185         /* Load the desired ASIC */
0186         err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
0187                     asic);
0188         if (err < 0)
0189             return err;
0190         chip->asic_code = asic;
0191     }
0192
0193     return 0;
0194 }
0195
0196
0197
0198 static int set_sample_rate(struct echoaudio *chip, u32 rate)
0199 {
0200     u32 control_reg, clock;
0201     short asic;
0202     char force_write;
0203
0204     /* Only set the clock for internal mode. */
0205     if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
0206         dev_dbg(chip->card->dev,
0207             "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
0208         /* Save the rate anyhow */
0209         chip->comm_page->sample_rate = cpu_to_le32(rate);
0210         chip->sample_rate = rate;
0211         return 0;
0212     }
0213
0214     /* Now, check to see if the required ASIC is loaded */
0215     if (rate >= 88200) {
0216         if (chip->digital_mode == DIGITAL_MODE_ADAT)
0217             return -EINVAL;
0218         if (chip->device_id == DEVICE_ID_56361)
0219             asic = FW_MONA_361_1_ASIC96;
0220         else
0221             asic = FW_MONA_301_1_ASIC96;
0222     } else {
0223         if (chip->device_id == DEVICE_ID_56361)
0224             asic = FW_MONA_361_1_ASIC48;
0225         else
0226             asic = FW_MONA_301_1_ASIC48;
0227     }
0228
0229     force_write = 0;
0230     if (asic != chip->asic_code) {
0231         int err;
0232         /* Load the desired ASIC (load_asic_generic() can sleep) */
0233         spin_unlock_irq(&chip->lock);
0234         err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
0235                     asic);
0236         spin_lock_irq(&chip->lock);
0237
0238         if (err < 0)
0239             return err;
0240         chip->asic_code = asic;
0241         force_write = 1;
0242     }
0243
0244     /* Compute the new control register value */
0245     clock = 0;
0246     control_reg = le32_to_cpu(chip->comm_page->control_register);
0247     control_reg &= GML_CLOCK_CLEAR_MASK;
0248     control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
0249
0250     switch (rate) {
0251     case 96000:
0252         clock = GML_96KHZ;
0253         break;
0254     case 88200:
0255         clock = GML_88KHZ;
0256         break;
0257     case 48000:
0258         clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
0259         break;
0260     case 44100:
0261         clock = GML_44KHZ;
0262         /* Professional mode */
0263         if (control_reg & GML_SPDIF_PRO_MODE)
0264             clock |= GML_SPDIF_SAMPLE_RATE0;
0265         break;
0266     case 32000:
0267         clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
0268             GML_SPDIF_SAMPLE_RATE1;
0269         break;
0270     case 22050:
0271         clock = GML_22KHZ;
0272         break;
0273     case 16000:
0274         clock = GML_16KHZ;
0275         break;
0276     case 11025:
0277         clock = GML_11KHZ;
0278         break;
0279     case 8000:
0280         clock = GML_8KHZ;
0281         break;
0282     default:
0283         dev_err(chip->card->dev,
0284             "set_sample_rate: %d invalid!\n", rate);
0285         return -EINVAL;
0286     }
0287
0288     control_reg |= clock;
0289
0290     chip->comm_page->sample_rate = cpu_to_le32(rate);   /* ignored by the DSP */
0291     chip->sample_rate = rate;
0292     dev_dbg(chip->card->dev,
0293         "set_sample_rate: %d clock %d\n", rate, clock);
0294
0295     return write_control_reg(chip, control_reg, force_write);
0296 }
0297
0298
0299
0300 static int set_input_clock(struct echoaudio *chip, u16 clock)
0301 {
0302     u32 control_reg, clocks_from_dsp;
0303     int err;
0304
0305     /* Mask off the clock select bits */
0306     control_reg = le32_to_cpu(chip->comm_page->control_register) &
0307         GML_CLOCK_CLEAR_MASK;
0308     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0309
0310     switch (clock) {
0311     case ECHO_CLOCK_INTERNAL:
0312         chip->input_clock = ECHO_CLOCK_INTERNAL;
0313         return set_sample_rate(chip, chip->sample_rate);
0314     case ECHO_CLOCK_SPDIF:
0315         if (chip->digital_mode == DIGITAL_MODE_ADAT)
0316             return -EAGAIN;
0317         spin_unlock_irq(&chip->lock);
0318         err = switch_asic(chip, clocks_from_dsp &
0319                   GML_CLOCK_DETECT_BIT_SPDIF96);
0320         spin_lock_irq(&chip->lock);
0321         if (err < 0)
0322             return err;
0323         control_reg |= GML_SPDIF_CLOCK;
0324         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
0325             control_reg |= GML_DOUBLE_SPEED_MODE;
0326         else
0327             control_reg &= ~GML_DOUBLE_SPEED_MODE;
0328         break;
0329     case ECHO_CLOCK_WORD:
0330         spin_unlock_irq(&chip->lock);
0331         err = switch_asic(chip, clocks_from_dsp &
0332                   GML_CLOCK_DETECT_BIT_WORD96);
0333         spin_lock_irq(&chip->lock);
0334         if (err < 0)
0335             return err;
0336         control_reg |= GML_WORD_CLOCK;
0337         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
0338             control_reg |= GML_DOUBLE_SPEED_MODE;
0339         else
0340             control_reg &= ~GML_DOUBLE_SPEED_MODE;
0341         break;
0342     case ECHO_CLOCK_ADAT:
0343         dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n");
0344         if (chip->digital_mode != DIGITAL_MODE_ADAT)
0345             return -EAGAIN;
0346         control_reg |= GML_ADAT_CLOCK;
0347         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0348         break;
0349     default:
0350         dev_err(chip->card->dev,
0351             "Input clock 0x%x not supported for Mona\n", clock);
0352         return -EINVAL;
0353     }
0354
0355     chip->input_clock = clock;
0356     return write_control_reg(chip, control_reg, true);
0357 }
0358
0359
0360
0361 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
0362 {
0363     u32 control_reg;
0364     int err, incompatible_clock;
0365
0366     /* Set clock to "internal" if it's not compatible with the new mode */
0367     incompatible_clock = false;
0368     switch (mode) {
0369     case DIGITAL_MODE_SPDIF_OPTICAL:
0370     case DIGITAL_MODE_SPDIF_RCA:
0371         if (chip->input_clock == ECHO_CLOCK_ADAT)
0372             incompatible_clock = true;
0373         break;
0374     case DIGITAL_MODE_ADAT:
0375         if (chip->input_clock == ECHO_CLOCK_SPDIF)
0376             incompatible_clock = true;
0377         break;
0378     default:
0379         dev_err(chip->card->dev,
0380             "Digital mode not supported: %d\n", mode);
0381         return -EINVAL;
0382     }
0383
0384     spin_lock_irq(&chip->lock);
0385
0386     if (incompatible_clock) {   /* Switch to 48KHz, internal */
0387         chip->sample_rate = 48000;
0388         set_input_clock(chip, ECHO_CLOCK_INTERNAL);
0389     }
0390
0391     /* Clear the current digital mode */
0392     control_reg = le32_to_cpu(chip->comm_page->control_register);
0393     control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
0394
0395     /* Tweak the control reg */
0396     switch (mode) {
0397     case DIGITAL_MODE_SPDIF_OPTICAL:
0398         control_reg |= GML_SPDIF_OPTICAL_MODE;
0399         break;
0400     case DIGITAL_MODE_SPDIF_RCA:
0401         /* GML_SPDIF_OPTICAL_MODE bit cleared */
0402         break;
0403     case DIGITAL_MODE_ADAT:
0404         /* If the current ASIC is the 96KHz ASIC, switch the ASIC
0405            and set to 48 KHz */
0406         if (chip->asic_code == FW_MONA_361_1_ASIC96 ||
0407             chip->asic_code == FW_MONA_301_1_ASIC96) {
0408             set_sample_rate(chip, 48000);
0409         }
0410         control_reg |= GML_ADAT_MODE;
0411         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0412         break;
0413     }
0414
0415     err = write_control_reg(chip, control_reg, false);
0416     spin_unlock_irq(&chip->lock);
0417     if (err < 0)
0418         return err;
0419     chip->digital_mode = mode;
0420
0421     dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);
0422     return incompatible_clock;
0423 }