pci/echoaudio/layla24_dsp.c

0001 /****************************************************************************
0002
0003    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
0004    All rights reserved
0005    www.echoaudio.com
0006
0007    This file is part of Echo Digital Audio's generic driver library.
0008
0009    Echo Digital Audio's generic driver library is free software;
0010    you can redistribute it and/or modify it under the terms of
0011    the GNU General Public License as published by the Free Software Foundation.
0012
0013    This program is distributed in the hope that it will be useful,
0014    but WITHOUT ANY WARRANTY; without even the implied warranty of
0015    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0016    GNU General Public License for more details.
0017
0018    You should have received a copy of the GNU General Public License
0019    along with this program; if not, write to the Free Software
0020    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
0021    MA  02111-1307, USA.
0022
0023    *************************************************************************
0024
0025  Translation from C++ and adaptation for use in ALSA-Driver
0026  were made by Giuliano Pochini <pochini@shiny.it>
0027
0028 ****************************************************************************/
0029
0030
0031 static int write_control_reg(struct echoaudio *chip, u32 value, char force);
0032 static int set_input_clock(struct echoaudio *chip, u16 clock);
0033 static int set_professional_spdif(struct echoaudio *chip, char prof);
0034 static int set_digital_mode(struct echoaudio *chip, u8 mode);
0035 static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
0036 static int check_asic_status(struct echoaudio *chip);
0037
0038
0039 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
0040 {
0041     int err;
0042
0043     if (snd_BUG_ON((subdevice_id & 0xfff0) != LAYLA24))
0044         return -ENODEV;
0045
0046     err = init_dsp_comm_page(chip);
0047     if (err) {
0048         dev_err(chip->card->dev,
0049             "init_hw - could not initialize DSP comm page\n");
0050         return err;
0051     }
0052
0053     chip->device_id = device_id;
0054     chip->subdevice_id = subdevice_id;
0055     chip->bad_board = true;
0056     chip->has_midi = true;
0057     chip->dsp_code_to_load = FW_LAYLA24_DSP;
0058     chip->input_clock_types =
0059         ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
0060         ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
0061     chip->digital_modes =
0062         ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
0063         ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
0064         ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
0065
0066     err = load_firmware(chip);
0067     if (err < 0)
0068         return err;
0069     chip->bad_board = false;
0070
0071     err = init_line_levels(chip);
0072     if (err < 0)
0073         return err;
0074
0075     return err;
0076 }
0077
0078
0079
0080 static int set_mixer_defaults(struct echoaudio *chip)
0081 {
0082     chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
0083     chip->professional_spdif = false;
0084     chip->digital_in_automute = true;
0085     return init_line_levels(chip);
0086 }
0087
0088
0089
0090 static u32 detect_input_clocks(const struct echoaudio *chip)
0091 {
0092     u32 clocks_from_dsp, clock_bits;
0093
0094     /* Map the DSP clock detect bits to the generic driver clock detect bits */
0095     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0096
0097     clock_bits = ECHO_CLOCK_BIT_INTERNAL;
0098
0099     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
0100         clock_bits |= ECHO_CLOCK_BIT_SPDIF;
0101
0102     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
0103         clock_bits |= ECHO_CLOCK_BIT_ADAT;
0104
0105     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
0106         clock_bits |= ECHO_CLOCK_BIT_WORD;
0107
0108     return clock_bits;
0109 }
0110
0111
0112
0113 /* Layla24 has an ASIC on the PCI card and another ASIC in the external box;
0114 both need to be loaded. */
0115 static int load_asic(struct echoaudio *chip)
0116 {
0117     int err;
0118
0119     if (chip->asic_loaded)
0120         return 1;
0121
0122
0123     /* Give the DSP a few milliseconds to settle down */
0124     mdelay(10);
0125
0126     /* Load the ASIC for the PCI card */
0127     err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC,
0128                 FW_LAYLA24_1_ASIC);
0129     if (err < 0)
0130         return err;
0131
0132     chip->asic_code = FW_LAYLA24_2S_ASIC;
0133
0134     /* Now give the new ASIC a little time to set up */
0135     mdelay(10);
0136
0137     /* Do the external one */
0138     err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
0139                 FW_LAYLA24_2S_ASIC);
0140     if (err < 0)
0141         return err;
0142
0143     /* Now give the external ASIC a little time to set up */
0144     mdelay(10);
0145
0146     /* See if it worked */
0147     err = check_asic_status(chip);
0148
0149     /* Set up the control register if the load succeeded -
0150        48 kHz, internal clock, S/PDIF RCA mode */
0151     if (!err)
0152         err = write_control_reg(chip, GML_CONVERTER_ENABLE | GML_48KHZ,
0153                     true);
0154
0155     return err;
0156 }
0157
0158
0159
0160 static int set_sample_rate(struct echoaudio *chip, u32 rate)
0161 {
0162     u32 control_reg, clock, base_rate;
0163
0164     if (snd_BUG_ON(rate >= 50000 &&
0165                chip->digital_mode == DIGITAL_MODE_ADAT))
0166         return -EINVAL;
0167
0168     /* Only set the clock for internal mode. */
0169     if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
0170         dev_warn(chip->card->dev,
0171              "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
0172         /* Save the rate anyhow */
0173         chip->comm_page->sample_rate = cpu_to_le32(rate);
0174         chip->sample_rate = rate;
0175         return 0;
0176     }
0177
0178     /* Get the control register & clear the appropriate bits */
0179     control_reg = le32_to_cpu(chip->comm_page->control_register);
0180     control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
0181
0182     clock = 0;
0183
0184     switch (rate) {
0185     case 96000:
0186         clock = GML_96KHZ;
0187         break;
0188     case 88200:
0189         clock = GML_88KHZ;
0190         break;
0191     case 48000:
0192         clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
0193         break;
0194     case 44100:
0195         clock = GML_44KHZ;
0196         /* Professional mode */
0197         if (control_reg & GML_SPDIF_PRO_MODE)
0198             clock |= GML_SPDIF_SAMPLE_RATE0;
0199         break;
0200     case 32000:
0201         clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
0202             GML_SPDIF_SAMPLE_RATE1;
0203         break;
0204     case 22050:
0205         clock = GML_22KHZ;
0206         break;
0207     case 16000:
0208         clock = GML_16KHZ;
0209         break;
0210     case 11025:
0211         clock = GML_11KHZ;
0212         break;
0213     case 8000:
0214         clock = GML_8KHZ;
0215         break;
0216     default:
0217         /* If this is a non-standard rate, then the driver needs to
0218         use Layla24's special "continuous frequency" mode */
0219         clock = LAYLA24_CONTINUOUS_CLOCK;
0220         if (rate > 50000) {
0221             base_rate = rate >> 1;
0222             control_reg |= GML_DOUBLE_SPEED_MODE;
0223         } else {
0224             base_rate = rate;
0225         }
0226
0227         if (base_rate < 25000)
0228             base_rate = 25000;
0229
0230         if (wait_handshake(chip))
0231             return -EIO;
0232
0233         chip->comm_page->sample_rate =
0234             cpu_to_le32(LAYLA24_MAGIC_NUMBER / base_rate - 2);
0235
0236         clear_handshake(chip);
0237         send_vector(chip, DSP_VC_SET_LAYLA24_FREQUENCY_REG);
0238     }
0239
0240     control_reg |= clock;
0241
0242     chip->comm_page->sample_rate = cpu_to_le32(rate);   /* ignored by the DSP ? */
0243     chip->sample_rate = rate;
0244     dev_dbg(chip->card->dev,
0245         "set_sample_rate: %d clock %d\n", rate, control_reg);
0246
0247     return write_control_reg(chip, control_reg, false);
0248 }
0249
0250
0251
0252 static int set_input_clock(struct echoaudio *chip, u16 clock)
0253 {
0254     u32 control_reg, clocks_from_dsp;
0255
0256     /* Mask off the clock select bits */
0257     control_reg = le32_to_cpu(chip->comm_page->control_register) &
0258         GML_CLOCK_CLEAR_MASK;
0259     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0260
0261     /* Pick the new clock */
0262     switch (clock) {
0263     case ECHO_CLOCK_INTERNAL:
0264         chip->input_clock = ECHO_CLOCK_INTERNAL;
0265         return set_sample_rate(chip, chip->sample_rate);
0266     case ECHO_CLOCK_SPDIF:
0267         if (chip->digital_mode == DIGITAL_MODE_ADAT)
0268             return -EAGAIN;
0269         control_reg |= GML_SPDIF_CLOCK;
0270         /* Layla24 doesn't support 96KHz S/PDIF */
0271         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0272         break;
0273     case ECHO_CLOCK_WORD:
0274         control_reg |= GML_WORD_CLOCK;
0275         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
0276             control_reg |= GML_DOUBLE_SPEED_MODE;
0277         else
0278             control_reg &= ~GML_DOUBLE_SPEED_MODE;
0279         break;
0280     case ECHO_CLOCK_ADAT:
0281         if (chip->digital_mode != DIGITAL_MODE_ADAT)
0282             return -EAGAIN;
0283         control_reg |= GML_ADAT_CLOCK;
0284         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0285         break;
0286     default:
0287         dev_err(chip->card->dev,
0288             "Input clock 0x%x not supported for Layla24\n", clock);
0289         return -EINVAL;
0290     }
0291
0292     chip->input_clock = clock;
0293     return write_control_reg(chip, control_reg, true);
0294 }
0295
0296
0297
0298 /* Depending on what digital mode you want, Layla24 needs different ASICs
0299 loaded.  This function checks the ASIC needed for the new mode and sees
0300 if it matches the one already loaded. */
0301 static int switch_asic(struct echoaudio *chip, short asic)
0302 {
0303     s8 *monitors;
0304
0305     /*  Check to see if this is already loaded */
0306     if (asic != chip->asic_code) {
0307         monitors = kmemdup(chip->comm_page->monitors,
0308                     MONITOR_ARRAY_SIZE, GFP_KERNEL);
0309         if (! monitors)
0310             return -ENOMEM;
0311
0312         memset(chip->comm_page->monitors, ECHOGAIN_MUTED,
0313                MONITOR_ARRAY_SIZE);
0314
0315         /* Load the desired ASIC */
0316         if (load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
0317                       asic) < 0) {
0318             memcpy(chip->comm_page->monitors, monitors,
0319                    MONITOR_ARRAY_SIZE);
0320             kfree(monitors);
0321             return -EIO;
0322         }
0323         chip->asic_code = asic;
0324         memcpy(chip->comm_page->monitors, monitors, MONITOR_ARRAY_SIZE);
0325         kfree(monitors);
0326     }
0327
0328     return 0;
0329 }
0330
0331
0332
0333 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
0334 {
0335     u32 control_reg;
0336     int err, incompatible_clock;
0337     short asic;
0338
0339     /* Set clock to "internal" if it's not compatible with the new mode */
0340     incompatible_clock = false;
0341     switch (mode) {
0342     case DIGITAL_MODE_SPDIF_OPTICAL:
0343     case DIGITAL_MODE_SPDIF_RCA:
0344         if (chip->input_clock == ECHO_CLOCK_ADAT)
0345             incompatible_clock = true;
0346         asic = FW_LAYLA24_2S_ASIC;
0347         break;
0348     case DIGITAL_MODE_ADAT:
0349         if (chip->input_clock == ECHO_CLOCK_SPDIF)
0350             incompatible_clock = true;
0351         asic = FW_LAYLA24_2A_ASIC;
0352         break;
0353     default:
0354         dev_err(chip->card->dev,
0355             "Digital mode not supported: %d\n", mode);
0356         return -EINVAL;
0357     }
0358
0359     if (incompatible_clock) {   /* Switch to 48KHz, internal */
0360         chip->sample_rate = 48000;
0361         spin_lock_irq(&chip->lock);
0362         set_input_clock(chip, ECHO_CLOCK_INTERNAL);
0363         spin_unlock_irq(&chip->lock);
0364     }
0365
0366     /* switch_asic() can sleep */
0367     if (switch_asic(chip, asic) < 0)
0368         return -EIO;
0369
0370     spin_lock_irq(&chip->lock);
0371
0372     /* Tweak the control register */
0373     control_reg = le32_to_cpu(chip->comm_page->control_register);
0374     control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
0375
0376     switch (mode) {
0377     case DIGITAL_MODE_SPDIF_OPTICAL:
0378         control_reg |= GML_SPDIF_OPTICAL_MODE;
0379         break;
0380     case DIGITAL_MODE_SPDIF_RCA:
0381         /* GML_SPDIF_OPTICAL_MODE bit cleared */
0382         break;
0383     case DIGITAL_MODE_ADAT:
0384         control_reg |= GML_ADAT_MODE;
0385         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0386         break;
0387     }
0388
0389     err = write_control_reg(chip, control_reg, true);
0390     spin_unlock_irq(&chip->lock);
0391     if (err < 0)
0392         return err;
0393     chip->digital_mode = mode;
0394
0395     dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);
0396     return incompatible_clock;
0397 }