pci/echoaudio/gina24_dsp.c

0001 /****************************************************************************
0002
0003    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
0004    All rights reserved
0005    www.echoaudio.com
0006
0007    This file is part of Echo Digital Audio's generic driver library.
0008
0009    Echo Digital Audio's generic driver library is free software;
0010    you can redistribute it and/or modify it under the terms of
0011    the GNU General Public License as published by the Free Software
0012    Foundation.
0013
0014    This program is distributed in the hope that it will be useful,
0015    but WITHOUT ANY WARRANTY; without even the implied warranty of
0016    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0017    GNU General Public License for more details.
0018
0019    You should have received a copy of the GNU General Public License
0020    along with this program; if not, write to the Free Software
0021    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
0022    MA  02111-1307, USA.
0023
0024    *************************************************************************
0025
0026  Translation from C++ and adaptation for use in ALSA-Driver
0027  were made by Giuliano Pochini <pochini@shiny.it>
0028
0029 ****************************************************************************/
0030
0031
0032 static int write_control_reg(struct echoaudio *chip, u32 value, char force);
0033 static int set_input_clock(struct echoaudio *chip, u16 clock);
0034 static int set_professional_spdif(struct echoaudio *chip, char prof);
0035 static int set_digital_mode(struct echoaudio *chip, u8 mode);
0036 static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
0037 static int check_asic_status(struct echoaudio *chip);
0038
0039
0040 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
0041 {
0042     int err;
0043
0044     if (snd_BUG_ON((subdevice_id & 0xfff0) != GINA24))
0045         return -ENODEV;
0046
0047     err = init_dsp_comm_page(chip);
0048     if (err) {
0049         dev_err(chip->card->dev,
0050             "init_hw - could not initialize DSP comm page\n");
0051         return err;
0052     }
0053
0054     chip->device_id = device_id;
0055     chip->subdevice_id = subdevice_id;
0056     chip->bad_board = true;
0057     chip->input_clock_types =
0058         ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
0059         ECHO_CLOCK_BIT_ESYNC | ECHO_CLOCK_BIT_ESYNC96 |
0060         ECHO_CLOCK_BIT_ADAT;
0061
0062     /* Gina24 comes in both '301 and '361 flavors */
0063     if (chip->device_id == DEVICE_ID_56361) {
0064         chip->dsp_code_to_load = FW_GINA24_361_DSP;
0065         chip->digital_modes =
0066             ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
0067             ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
0068             ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
0069     } else {
0070         chip->dsp_code_to_load = FW_GINA24_301_DSP;
0071         chip->digital_modes =
0072             ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
0073             ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
0074             ECHOCAPS_HAS_DIGITAL_MODE_ADAT |
0075             ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_CDROM;
0076     }
0077
0078     err = load_firmware(chip);
0079     if (err < 0)
0080         return err;
0081     chip->bad_board = false;
0082
0083     return err;
0084 }
0085
0086
0087
0088 static int set_mixer_defaults(struct echoaudio *chip)
0089 {
0090     chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
0091     chip->professional_spdif = false;
0092     chip->digital_in_automute = true;
0093     return init_line_levels(chip);
0094 }
0095
0096
0097
0098 static u32 detect_input_clocks(const struct echoaudio *chip)
0099 {
0100     u32 clocks_from_dsp, clock_bits;
0101
0102     /* Map the DSP clock detect bits to the generic driver clock
0103        detect bits */
0104     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0105
0106     clock_bits = ECHO_CLOCK_BIT_INTERNAL;
0107
0108     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
0109         clock_bits |= ECHO_CLOCK_BIT_SPDIF;
0110
0111     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
0112         clock_bits |= ECHO_CLOCK_BIT_ADAT;
0113
0114     if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ESYNC)
0115         clock_bits |= ECHO_CLOCK_BIT_ESYNC | ECHO_CLOCK_BIT_ESYNC96;
0116
0117     return clock_bits;
0118 }
0119
0120
0121
0122 /* Gina24 has an ASIC on the PCI card which must be loaded for anything
0123 interesting to happen. */
0124 static int load_asic(struct echoaudio *chip)
0125 {
0126     u32 control_reg;
0127     int err;
0128     short asic;
0129
0130     if (chip->asic_loaded)
0131         return 1;
0132
0133     /* Give the DSP a few milliseconds to settle down */
0134     mdelay(10);
0135
0136     /* Pick the correct ASIC for '301 or '361 Gina24 */
0137     if (chip->device_id == DEVICE_ID_56361)
0138         asic = FW_GINA24_361_ASIC;
0139     else
0140         asic = FW_GINA24_301_ASIC;
0141
0142     err = load_asic_generic(chip, DSP_FNC_LOAD_GINA24_ASIC, asic);
0143     if (err < 0)
0144         return err;
0145
0146     chip->asic_code = asic;
0147
0148     /* Now give the new ASIC a little time to set up */
0149     mdelay(10);
0150     /* See if it worked */
0151     err = check_asic_status(chip);
0152
0153     /* Set up the control register if the load succeeded -
0154        48 kHz, internal clock, S/PDIF RCA mode */
0155     if (!err) {
0156         control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
0157         err = write_control_reg(chip, control_reg, true);
0158     }
0159     return err;
0160 }
0161
0162
0163
0164 static int set_sample_rate(struct echoaudio *chip, u32 rate)
0165 {
0166     u32 control_reg, clock;
0167
0168     if (snd_BUG_ON(rate >= 50000 &&
0169                chip->digital_mode == DIGITAL_MODE_ADAT))
0170         return -EINVAL;
0171
0172     /* Only set the clock for internal mode. */
0173     if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
0174         dev_warn(chip->card->dev,
0175              "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
0176         /* Save the rate anyhow */
0177         chip->comm_page->sample_rate = cpu_to_le32(rate);
0178         chip->sample_rate = rate;
0179         return 0;
0180     }
0181
0182     clock = 0;
0183
0184     control_reg = le32_to_cpu(chip->comm_page->control_register);
0185     control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
0186
0187     switch (rate) {
0188     case 96000:
0189         clock = GML_96KHZ;
0190         break;
0191     case 88200:
0192         clock = GML_88KHZ;
0193         break;
0194     case 48000:
0195         clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
0196         break;
0197     case 44100:
0198         clock = GML_44KHZ;
0199         /* Professional mode ? */
0200         if (control_reg & GML_SPDIF_PRO_MODE)
0201             clock |= GML_SPDIF_SAMPLE_RATE0;
0202         break;
0203     case 32000:
0204         clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
0205             GML_SPDIF_SAMPLE_RATE1;
0206         break;
0207     case 22050:
0208         clock = GML_22KHZ;
0209         break;
0210     case 16000:
0211         clock = GML_16KHZ;
0212         break;
0213     case 11025:
0214         clock = GML_11KHZ;
0215         break;
0216     case 8000:
0217         clock = GML_8KHZ;
0218         break;
0219     default:
0220         dev_err(chip->card->dev,
0221             "set_sample_rate: %d invalid!\n", rate);
0222         return -EINVAL;
0223     }
0224
0225     control_reg |= clock;
0226
0227     chip->comm_page->sample_rate = cpu_to_le32(rate);   /* ignored by the DSP */
0228     chip->sample_rate = rate;
0229     dev_dbg(chip->card->dev, "set_sample_rate: %d clock %d\n", rate, clock);
0230
0231     return write_control_reg(chip, control_reg, false);
0232 }
0233
0234
0235
0236 static int set_input_clock(struct echoaudio *chip, u16 clock)
0237 {
0238     u32 control_reg, clocks_from_dsp;
0239
0240
0241     /* Mask off the clock select bits */
0242     control_reg = le32_to_cpu(chip->comm_page->control_register) &
0243         GML_CLOCK_CLEAR_MASK;
0244     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0245
0246     switch (clock) {
0247     case ECHO_CLOCK_INTERNAL:
0248         chip->input_clock = ECHO_CLOCK_INTERNAL;
0249         return set_sample_rate(chip, chip->sample_rate);
0250     case ECHO_CLOCK_SPDIF:
0251         if (chip->digital_mode == DIGITAL_MODE_ADAT)
0252             return -EAGAIN;
0253         control_reg |= GML_SPDIF_CLOCK;
0254         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
0255             control_reg |= GML_DOUBLE_SPEED_MODE;
0256         else
0257             control_reg &= ~GML_DOUBLE_SPEED_MODE;
0258         break;
0259     case ECHO_CLOCK_ADAT:
0260         if (chip->digital_mode != DIGITAL_MODE_ADAT)
0261             return -EAGAIN;
0262         control_reg |= GML_ADAT_CLOCK;
0263         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0264         break;
0265     case ECHO_CLOCK_ESYNC:
0266         control_reg |= GML_ESYNC_CLOCK;
0267         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0268         break;
0269     case ECHO_CLOCK_ESYNC96:
0270         control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;
0271         break;
0272     default:
0273         dev_err(chip->card->dev,
0274             "Input clock 0x%x not supported for Gina24\n", clock);
0275         return -EINVAL;
0276     }
0277
0278     chip->input_clock = clock;
0279     return write_control_reg(chip, control_reg, true);
0280 }
0281
0282
0283
0284 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
0285 {
0286     u32 control_reg;
0287     int err, incompatible_clock;
0288
0289     /* Set clock to "internal" if it's not compatible with the new mode */
0290     incompatible_clock = false;
0291     switch (mode) {
0292     case DIGITAL_MODE_SPDIF_OPTICAL:
0293     case DIGITAL_MODE_SPDIF_CDROM:
0294     case DIGITAL_MODE_SPDIF_RCA:
0295         if (chip->input_clock == ECHO_CLOCK_ADAT)
0296             incompatible_clock = true;
0297         break;
0298     case DIGITAL_MODE_ADAT:
0299         if (chip->input_clock == ECHO_CLOCK_SPDIF)
0300             incompatible_clock = true;
0301         break;
0302     default:
0303         dev_err(chip->card->dev,
0304             "Digital mode not supported: %d\n", mode);
0305         return -EINVAL;
0306     }
0307
0308     spin_lock_irq(&chip->lock);
0309
0310     if (incompatible_clock) {   /* Switch to 48KHz, internal */
0311         chip->sample_rate = 48000;
0312         set_input_clock(chip, ECHO_CLOCK_INTERNAL);
0313     }
0314
0315     /* Clear the current digital mode */
0316     control_reg = le32_to_cpu(chip->comm_page->control_register);
0317     control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
0318
0319     /* Tweak the control reg */
0320     switch (mode) {
0321     case DIGITAL_MODE_SPDIF_OPTICAL:
0322         control_reg |= GML_SPDIF_OPTICAL_MODE;
0323         break;
0324     case DIGITAL_MODE_SPDIF_CDROM:
0325         /* '361 Gina24 cards do not have the S/PDIF CD-ROM mode */
0326         if (chip->device_id == DEVICE_ID_56301)
0327             control_reg |= GML_SPDIF_CDROM_MODE;
0328         break;
0329     case DIGITAL_MODE_SPDIF_RCA:
0330         /* GML_SPDIF_OPTICAL_MODE bit cleared */
0331         break;
0332     case DIGITAL_MODE_ADAT:
0333         control_reg |= GML_ADAT_MODE;
0334         control_reg &= ~GML_DOUBLE_SPEED_MODE;
0335         break;
0336     }
0337
0338     err = write_control_reg(chip, control_reg, true);
0339     spin_unlock_irq(&chip->lock);
0340     if (err < 0)
0341         return err;
0342     chip->digital_mode = mode;
0343
0344     dev_dbg(chip->card->dev,
0345         "set_digital_mode to %d\n", chip->digital_mode);
0346     return incompatible_clock;
0347 }