pci/echoaudio/echoaudio_3g.c

0001 /****************************************************************************
0002
0003    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
0004    All rights reserved
0005    www.echoaudio.com
0006
0007    This file is part of Echo Digital Audio's generic driver library.
0008
0009    Echo Digital Audio's generic driver library is free software;
0010    you can redistribute it and/or modify it under the terms of
0011    the GNU General Public License as published by the Free Software
0012    Foundation.
0013
0014    This program is distributed in the hope that it will be useful,
0015    but WITHOUT ANY WARRANTY; without even the implied warranty of
0016    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0017    GNU General Public License for more details.
0018
0019    You should have received a copy of the GNU General Public License
0020    along with this program; if not, write to the Free Software
0021    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
0022    MA  02111-1307, USA.
0023
0024    *************************************************************************
0025
0026  Translation from C++ and adaptation for use in ALSA-Driver
0027  were made by Giuliano Pochini <pochini@shiny.it>
0028
0029 ****************************************************************************/
0030
0031
0032
0033 /* These functions are common for all "3G" cards */
0034
0035
0036 static int check_asic_status(struct echoaudio *chip)
0037 {
0038     u32 box_status;
0039
0040     if (wait_handshake(chip))
0041         return -EIO;
0042
0043     chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED);
0044     chip->asic_loaded = false;
0045     clear_handshake(chip);
0046     send_vector(chip, DSP_VC_TEST_ASIC);
0047
0048     if (wait_handshake(chip)) {
0049         chip->dsp_code = NULL;
0050         return -EIO;
0051     }
0052
0053     box_status = le32_to_cpu(chip->comm_page->ext_box_status);
0054     dev_dbg(chip->card->dev, "box_status=%x\n", box_status);
0055     if (box_status == E3G_ASIC_NOT_LOADED)
0056         return -ENODEV;
0057
0058     chip->asic_loaded = true;
0059     return box_status & E3G_BOX_TYPE_MASK;
0060 }
0061
0062
0063
0064 static inline u32 get_frq_reg(struct echoaudio *chip)
0065 {
0066     return le32_to_cpu(chip->comm_page->e3g_frq_register);
0067 }
0068
0069
0070
0071 /* Most configuration of 3G cards is accomplished by writing the control
0072 register. write_control_reg sends the new control register value to the DSP. */
0073 static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq,
0074                  char force)
0075 {
0076     __le32 ctl_reg, frq_reg;
0077
0078     if (wait_handshake(chip))
0079         return -EIO;
0080
0081     dev_dbg(chip->card->dev,
0082         "WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq);
0083
0084     ctl_reg = cpu_to_le32(ctl);
0085     frq_reg = cpu_to_le32(frq);
0086
0087     if (ctl_reg != chip->comm_page->control_register ||
0088         frq_reg != chip->comm_page->e3g_frq_register || force) {
0089         chip->comm_page->e3g_frq_register = frq_reg;
0090         chip->comm_page->control_register = ctl_reg;
0091         clear_handshake(chip);
0092         return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
0093     }
0094
0095     dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n");
0096     return 0;
0097 }
0098
0099
0100
0101 /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
0102 static int set_digital_mode(struct echoaudio *chip, u8 mode)
0103 {
0104     u8 previous_mode;
0105     int err, i, o;
0106
0107     /* All audio channels must be closed before changing the digital mode */
0108     if (snd_BUG_ON(chip->pipe_alloc_mask))
0109         return -EAGAIN;
0110
0111     if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
0112         return -EINVAL;
0113
0114     previous_mode = chip->digital_mode;
0115     err = dsp_set_digital_mode(chip, mode);
0116
0117     /* If we successfully changed the digital mode from or to ADAT,
0118      * then make sure all output, input and monitor levels are
0119      * updated by the DSP comm object. */
0120     if (err >= 0 && previous_mode != mode &&
0121         (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) {
0122         spin_lock_irq(&chip->lock);
0123         for (o = 0; o < num_busses_out(chip); o++)
0124             for (i = 0; i < num_busses_in(chip); i++)
0125                 set_monitor_gain(chip, o, i,
0126                          chip->monitor_gain[o][i]);
0127
0128 #ifdef ECHOCARD_HAS_INPUT_GAIN
0129         for (i = 0; i < num_busses_in(chip); i++)
0130             set_input_gain(chip, i, chip->input_gain[i]);
0131         update_input_line_level(chip);
0132 #endif
0133
0134         for (o = 0; o < num_busses_out(chip); o++)
0135             set_output_gain(chip, o, chip->output_gain[o]);
0136         update_output_line_level(chip);
0137         spin_unlock_irq(&chip->lock);
0138     }
0139
0140     return err;
0141 }
0142
0143
0144
0145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
0146 {
0147     control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
0148
0149     switch (rate) {
0150     case 32000 :
0151         control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
0152         break;
0153     case 44100 :
0154         if (chip->professional_spdif)
0155             control_reg |= E3G_SPDIF_SAMPLE_RATE0;
0156         break;
0157     case 48000 :
0158         control_reg |= E3G_SPDIF_SAMPLE_RATE1;
0159         break;
0160     }
0161
0162     if (chip->professional_spdif)
0163         control_reg |= E3G_SPDIF_PRO_MODE;
0164
0165     if (chip->non_audio_spdif)
0166         control_reg |= E3G_SPDIF_NOT_AUDIO;
0167
0168     control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
0169         E3G_SPDIF_COPY_PERMIT;
0170
0171     return control_reg;
0172 }
0173
0174
0175
0176 /* Set the S/PDIF output format */
0177 static int set_professional_spdif(struct echoaudio *chip, char prof)
0178 {
0179     u32 control_reg;
0180
0181     control_reg = le32_to_cpu(chip->comm_page->control_register);
0182     chip->professional_spdif = prof;
0183     control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
0184     return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
0185 }
0186
0187
0188
0189 /* detect_input_clocks() returns a bitmask consisting of all the input clocks
0190 currently connected to the hardware; this changes as the user connects and
0191 disconnects clock inputs. You should use this information to determine which
0192 clocks the user is allowed to select. */
0193 static u32 detect_input_clocks(const struct echoaudio *chip)
0194 {
0195     u32 clocks_from_dsp, clock_bits;
0196
0197     /* Map the DSP clock detect bits to the generic driver clock
0198      * detect bits */
0199     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0200
0201     clock_bits = ECHO_CLOCK_BIT_INTERNAL;
0202
0203     if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD)
0204         clock_bits |= ECHO_CLOCK_BIT_WORD;
0205
0206     switch(chip->digital_mode) {
0207     case DIGITAL_MODE_SPDIF_RCA:
0208     case DIGITAL_MODE_SPDIF_OPTICAL:
0209         if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF)
0210             clock_bits |= ECHO_CLOCK_BIT_SPDIF;
0211         break;
0212     case DIGITAL_MODE_ADAT:
0213         if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT)
0214             clock_bits |= ECHO_CLOCK_BIT_ADAT;
0215         break;
0216     }
0217
0218     return clock_bits;
0219 }
0220
0221
0222
0223 static int load_asic(struct echoaudio *chip)
0224 {
0225     int box_type, err;
0226
0227     if (chip->asic_loaded)
0228         return 0;
0229
0230     /* Give the DSP a few milliseconds to settle down */
0231     mdelay(2);
0232
0233     err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, FW_3G_ASIC);
0234     if (err < 0)
0235         return err;
0236
0237     chip->asic_code = FW_3G_ASIC;
0238
0239     /* Now give the new ASIC some time to set up */
0240     msleep(1000);
0241     /* See if it worked */
0242     box_type = check_asic_status(chip);
0243
0244     /* Set up the control register if the load succeeded -
0245      * 48 kHz, internal clock, S/PDIF RCA mode */
0246     if (box_type >= 0) {
0247         err = write_control_reg(chip, E3G_48KHZ,
0248                     E3G_FREQ_REG_DEFAULT, true);
0249         if (err < 0)
0250             return err;
0251     }
0252
0253     return box_type;
0254 }
0255
0256
0257
0258 static int set_sample_rate(struct echoaudio *chip, u32 rate)
0259 {
0260     u32 control_reg, clock, base_rate, frq_reg;
0261
0262     /* Only set the clock for internal mode. */
0263     if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
0264         dev_warn(chip->card->dev,
0265              "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
0266         /* Save the rate anyhow */
0267         chip->comm_page->sample_rate = cpu_to_le32(rate);
0268         chip->sample_rate = rate;
0269         set_input_clock(chip, chip->input_clock);
0270         return 0;
0271     }
0272
0273     if (snd_BUG_ON(rate >= 50000 &&
0274                chip->digital_mode == DIGITAL_MODE_ADAT))
0275         return -EINVAL;
0276
0277     clock = 0;
0278     control_reg = le32_to_cpu(chip->comm_page->control_register);
0279     control_reg &= E3G_CLOCK_CLEAR_MASK;
0280
0281     switch (rate) {
0282     case 96000:
0283         clock = E3G_96KHZ;
0284         break;
0285     case 88200:
0286         clock = E3G_88KHZ;
0287         break;
0288     case 48000:
0289         clock = E3G_48KHZ;
0290         break;
0291     case 44100:
0292         clock = E3G_44KHZ;
0293         break;
0294     case 32000:
0295         clock = E3G_32KHZ;
0296         break;
0297     default:
0298         clock = E3G_CONTINUOUS_CLOCK;
0299         if (rate > 50000)
0300             clock |= E3G_DOUBLE_SPEED_MODE;
0301         break;
0302     }
0303
0304     control_reg |= clock;
0305     control_reg = set_spdif_bits(chip, control_reg, rate);
0306
0307     base_rate = rate;
0308     if (base_rate > 50000)
0309         base_rate /= 2;
0310     if (base_rate < 32000)
0311         base_rate = 32000;
0312
0313     frq_reg = E3G_MAGIC_NUMBER / base_rate - 2;
0314     if (frq_reg > E3G_FREQ_REG_MAX)
0315         frq_reg = E3G_FREQ_REG_MAX;
0316
0317     chip->comm_page->sample_rate = cpu_to_le32(rate);   /* ignored by the DSP */
0318     chip->sample_rate = rate;
0319     dev_dbg(chip->card->dev,
0320         "SetSampleRate: %d clock %x\n", rate, control_reg);
0321
0322     /* Tell the DSP about it - DSP reads both control reg & freq reg */
0323     return write_control_reg(chip, control_reg, frq_reg, 0);
0324 }
0325
0326
0327
0328 /* Set the sample clock source to internal, S/PDIF, ADAT */
0329 static int set_input_clock(struct echoaudio *chip, u16 clock)
0330 {
0331     u32 control_reg, clocks_from_dsp;
0332
0333
0334     /* Mask off the clock select bits */
0335     control_reg = le32_to_cpu(chip->comm_page->control_register) &
0336         E3G_CLOCK_CLEAR_MASK;
0337     clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
0338
0339     switch (clock) {
0340     case ECHO_CLOCK_INTERNAL:
0341         chip->input_clock = ECHO_CLOCK_INTERNAL;
0342         return set_sample_rate(chip, chip->sample_rate);
0343     case ECHO_CLOCK_SPDIF:
0344         if (chip->digital_mode == DIGITAL_MODE_ADAT)
0345             return -EAGAIN;
0346         control_reg |= E3G_SPDIF_CLOCK;
0347         if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96)
0348             control_reg |= E3G_DOUBLE_SPEED_MODE;
0349         else
0350             control_reg &= ~E3G_DOUBLE_SPEED_MODE;
0351         break;
0352     case ECHO_CLOCK_ADAT:
0353         if (chip->digital_mode != DIGITAL_MODE_ADAT)
0354             return -EAGAIN;
0355         control_reg |= E3G_ADAT_CLOCK;
0356         control_reg &= ~E3G_DOUBLE_SPEED_MODE;
0357         break;
0358     case ECHO_CLOCK_WORD:
0359         control_reg |= E3G_WORD_CLOCK;
0360         if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96)
0361             control_reg |= E3G_DOUBLE_SPEED_MODE;
0362         else
0363             control_reg &= ~E3G_DOUBLE_SPEED_MODE;
0364         break;
0365     default:
0366         dev_err(chip->card->dev,
0367             "Input clock 0x%x not supported for Echo3G\n", clock);
0368         return -EINVAL;
0369     }
0370
0371     chip->input_clock = clock;
0372     return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
0373 }
0374
0375
0376
0377 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
0378 {
0379     u32 control_reg;
0380     int err, incompatible_clock;
0381
0382     /* Set clock to "internal" if it's not compatible with the new mode */
0383     incompatible_clock = false;
0384     switch (mode) {
0385     case DIGITAL_MODE_SPDIF_OPTICAL:
0386     case DIGITAL_MODE_SPDIF_RCA:
0387         if (chip->input_clock == ECHO_CLOCK_ADAT)
0388             incompatible_clock = true;
0389         break;
0390     case DIGITAL_MODE_ADAT:
0391         if (chip->input_clock == ECHO_CLOCK_SPDIF)
0392             incompatible_clock = true;
0393         break;
0394     default:
0395         dev_err(chip->card->dev,
0396             "Digital mode not supported: %d\n", mode);
0397         return -EINVAL;
0398     }
0399
0400     spin_lock_irq(&chip->lock);
0401
0402     if (incompatible_clock) {
0403         chip->sample_rate = 48000;
0404         set_input_clock(chip, ECHO_CLOCK_INTERNAL);
0405     }
0406
0407     /* Clear the current digital mode */
0408     control_reg = le32_to_cpu(chip->comm_page->control_register);
0409     control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
0410
0411     /* Tweak the control reg */
0412     switch (mode) {
0413     case DIGITAL_MODE_SPDIF_OPTICAL:
0414         control_reg |= E3G_SPDIF_OPTICAL_MODE;
0415         break;
0416     case DIGITAL_MODE_SPDIF_RCA:
0417         /* E3G_SPDIF_OPTICAL_MODE bit cleared */
0418         break;
0419     case DIGITAL_MODE_ADAT:
0420         control_reg |= E3G_ADAT_MODE;
0421         control_reg &= ~E3G_DOUBLE_SPEED_MODE;  /* @@ useless */
0422         break;
0423     }
0424
0425     err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
0426     spin_unlock_irq(&chip->lock);
0427     if (err < 0)
0428         return err;
0429     chip->digital_mode = mode;
0430
0431     dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode);
0432     return incompatible_clock;
0433 }