pci/ctxfi/ct20k2reg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
0004  */
0005
0006 #ifndef _20K2REGISTERS_H_
0007 #define _20K2REGISTERS_H_
0008
0009
0010 /* Timer Registers */
0011 #define WC      0x1b7000
0012 #define TIMR        0x1b7004
0013 # define    TIMR_IE     (1<<15)
0014 # define    TIMR_IP     (1<<14)
0015 #define GIP     0x1b7010
0016 #define GIE     0x1b7014
0017
0018 /* I2C Registers */
0019 #define I2C_IF_ADDRESS   0x1B9000
0020 #define I2C_IF_WDATA     0x1B9004
0021 #define I2C_IF_RDATA     0x1B9008
0022 #define I2C_IF_STATUS    0x1B900C
0023 #define I2C_IF_WLOCK     0x1B9010
0024
0025 /* Global Control Registers */
0026 #define GLOBAL_CNTL_GCTL    0x1B7090
0027
0028 /* PLL Registers */
0029 #define PLL_CTL         0x1B7080
0030 #define PLL_STAT        0x1B7084
0031 #define PLL_ENB         0x1B7088
0032
0033 /* SRC Registers */
0034 #define SRC_CTL             0x1A0000 /* 0x1A0000 + (256 * Chn) */
0035 #define SRC_CCR             0x1A0004 /* 0x1A0004 + (256 * Chn) */
0036 #define SRC_IMAP            0x1A0008 /* 0x1A0008 + (256 * Chn) */
0037 #define SRC_CA              0x1A0010 /* 0x1A0010 + (256 * Chn) */
0038 #define SRC_CF              0x1A0014 /* 0x1A0014 + (256 * Chn) */
0039 #define SRC_SA              0x1A0018 /* 0x1A0018 + (256 * Chn) */
0040 #define SRC_LA              0x1A001C /* 0x1A001C + (256 * Chn) */
0041 #define SRC_CTLSWR      0x1A0020 /* 0x1A0020 + (256 * Chn) */
0042 #define SRC_CD          0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */
0043 #define SRC_MCTL        0x1A012C
0044 #define SRC_IP          0x1A102C /* 0x1A102C + (256 * Regn) */
0045 #define SRC_ENB         0x1A282C /* 0x1A282C + (256 * Regn) */
0046 #define SRC_ENBSTAT     0x1A202C
0047 #define SRC_ENBSA       0x1A232C
0048 #define SRC_DN0Z        0x1A0030
0049 #define SRC_DN1Z        0x1A0040
0050 #define SRC_UPZ         0x1A0060
0051
0052 /* GPIO Registers */
0053 #define GPIO_DATA           0x1B7020
0054 #define GPIO_CTRL           0x1B7024
0055 #define GPIO_EXT_DATA       0x1B70A0
0056
0057 /* Virtual memory registers */
0058 #define VMEM_PTPAL          0x1C6300 /* 0x1C6300 + (16 * Chn) */
0059 #define VMEM_PTPAH          0x1C6304 /* 0x1C6304 + (16 * Chn) */
0060 #define VMEM_CTL            0x1C7000
0061
0062 /* Transport Registers */
0063 #define TRANSPORT_ENB       0x1B6000
0064 #define TRANSPORT_CTL       0x1B6004
0065 #define TRANSPORT_INT       0x1B6008
0066
0067 /* Audio IO */
0068 #define AUDIO_IO_AIM        0x1B5000 /* 0x1B5000 + (0x04 * Chn) */
0069 #define AUDIO_IO_TX_CTL     0x1B5400 /* 0x1B5400 + (0x40 * Chn) */
0070 #define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */
0071 #define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */
0072 #define AUDIO_IO_RX_CTL     0x1B5410 /* 0x1B5410 + (0x40 * Chn) */
0073 #define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */
0074 #define AUDIO_IO_MCLK       0x1B5600
0075 #define AUDIO_IO_TX_BLRCLK  0x1B5604
0076 #define AUDIO_IO_RX_BLRCLK  0x1B5608
0077
0078 /* Mixer */
0079 #define MIXER_AMOPLO        0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */
0080 #define MIXER_AMOPHI        0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */
0081 #define MIXER_PRING_LO_HI   0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */
0082 #define MIXER_PMOPLO        0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */
0083 #define MIXER_PMOPHI        0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */
0084 #define MIXER_AR_ENABLE     0x19000C
0085
0086 #endif