pci/cs46xx/dsp_spos.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
0004  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
0005  */
0006
0007 /*
0008  * 2002-07 Benny Sjostrand benny@hostmobility.com
0009  */
0010
0011 #ifdef  CONFIG_SND_CS46XX_NEW_DSP /* hack ... */
0012 #ifndef __DSP_SPOS_H__
0013 #define __DSP_SPOS_H__
0014
0015 #define DSP_MAX_SYMBOLS 1024
0016 #define DSP_MAX_MODULES 64
0017
0018 #define DSP_CODE_BYTE_SIZE             0x00007000UL
0019 #define DSP_PARAMETER_BYTE_SIZE        0x00003000UL
0020 #define DSP_SAMPLE_BYTE_SIZE           0x00003800UL
0021 #define DSP_PARAMETER_BYTE_OFFSET      0x00000000UL
0022 #define DSP_SAMPLE_BYTE_OFFSET         0x00010000UL
0023 #define DSP_CODE_BYTE_OFFSET           0x00020000UL
0024
0025 #define WIDE_INSTR_MASK       0x0040
0026 #define WIDE_LADD_INSTR_MASK  0x0380
0027
0028 /* this instruction types
0029    needs to be reallocated when load
0030    code into DSP */
0031 enum wide_opcode {
0032     WIDE_FOR_BEGIN_LOOP = 0x20,
0033     WIDE_FOR_BEGIN_LOOP2,
0034
0035     WIDE_COND_GOTO_ADDR = 0x30,
0036     WIDE_COND_GOTO_CALL,
0037
0038     WIDE_TBEQ_COND_GOTO_ADDR = 0x70,
0039     WIDE_TBEQ_COND_CALL_ADDR,
0040     WIDE_TBEQ_NCOND_GOTO_ADDR,
0041     WIDE_TBEQ_NCOND_CALL_ADDR,
0042     WIDE_TBEQ_COND_GOTO1_ADDR,
0043     WIDE_TBEQ_COND_CALL1_ADDR,
0044     WIDE_TBEQ_NCOND_GOTOI_ADDR,
0045     WIDE_TBEQ_NCOND_CALL1_ADDR,
0046 };
0047
0048 /* SAMPLE segment */
0049 #define VARI_DECIMATE_BUF1       0x0000
0050 #define WRITE_BACK_BUF1          0x0400
0051 #define CODEC_INPUT_BUF1         0x0500
0052 #define PCM_READER_BUF1          0x0600
0053 #define SRC_DELAY_BUF1           0x0680
0054 #define VARI_DECIMATE_BUF0       0x0780
0055 #define SRC_OUTPUT_BUF1          0x07A0
0056 #define ASYNC_IP_OUTPUT_BUFFER1  0x0A00
0057 #define OUTPUT_SNOOP_BUFFER      0x0B00
0058 #define SPDIFI_IP_OUTPUT_BUFFER1 0x0E00
0059 #define SPDIFO_IP_OUTPUT_BUFFER1 0x1000
0060 #define MIX_SAMPLE_BUF1          0x1400
0061 #define MIX_SAMPLE_BUF2          0x2E80
0062 #define MIX_SAMPLE_BUF3          0x2F00
0063 #define MIX_SAMPLE_BUF4          0x2F80
0064 #define MIX_SAMPLE_BUF5          0x3000
0065
0066 /* Task stack address */
0067 #define HFG_STACK                0x066A
0068 #define FG_STACK                 0x066E
0069 #define BG_STACK                 0x068E
0070
0071 /* SCB's addresses */
0072 #define SPOSCB_ADDR              0x070
0073 #define BG_TREE_SCB_ADDR         0x635
0074 #define NULL_SCB_ADDR            0x000
0075 #define TIMINGMASTER_SCB_ADDR    0x010
0076 #define CODECOUT_SCB_ADDR        0x020
0077 #define PCMREADER_SCB_ADDR       0x030
0078 #define WRITEBACK_SCB_ADDR       0x040
0079 #define CODECIN_SCB_ADDR         0x080
0080 #define MASTERMIX_SCB_ADDR       0x090
0081 #define SRCTASK_SCB_ADDR         0x0A0
0082 #define VARIDECIMATE_SCB_ADDR    0x0B0
0083 #define PCMSERIALIN_SCB_ADDR     0x0C0
0084 #define FG_TASK_HEADER_ADDR      0x600
0085 #define ASYNCTX_SCB_ADDR         0x0E0
0086 #define ASYNCRX_SCB_ADDR         0x0F0
0087 #define SRCTASKII_SCB_ADDR       0x100
0088 #define OUTPUTSNOOP_SCB_ADDR     0x110
0089 #define PCMSERIALINII_SCB_ADDR   0x120
0090 #define SPIOWRITE_SCB_ADDR       0x130
0091 #define REAR_CODECOUT_SCB_ADDR   0x140
0092 #define OUTPUTSNOOPII_SCB_ADDR   0x150
0093 #define PCMSERIALIN_PCM_SCB_ADDR 0x160
0094 #define RECORD_MIXER_SCB_ADDR    0x170
0095 #define REAR_MIXER_SCB_ADDR      0x180
0096 #define CLFE_MIXER_SCB_ADDR      0x190
0097 #define CLFE_CODEC_SCB_ADDR      0x1A0
0098
0099 /* hyperforground SCB's*/
0100 #define HFG_TREE_SCB             0xBA0
0101 #define SPDIFI_SCB_INST          0xBB0
0102 #define SPDIFO_SCB_INST          0xBC0
0103 #define WRITE_BACK_SPB           0x0D0
0104
0105 /* offsets */
0106 #define AsyncCIOFIFOPointer  0xd
0107 #define SPDIFOFIFOPointer    0xd
0108 #define SPDIFIFIFOPointer    0xd
0109 #define TCBData              0xb
0110 #define HFGFlags             0xa
0111 #define TCBContextBlk        0x10
0112 #define AFGTxAccumPhi        0x4
0113 #define SCBsubListPtr        0x9
0114 #define SCBfuncEntryPtr      0xA
0115 #define SRCCorPerGof         0x2
0116 #define SRCPhiIncr6Int26Frac 0xd
0117 #define SCBVolumeCtrl        0xe
0118
0119 /* conf */
0120 #define UseASER1Input 1
0121
0122
0123
0124 /*
0125  * The following defines are for the flags in the rsConfig01/23 registers of
0126  * the SP.
0127  */
0128
0129 #define RSCONFIG_MODULO_SIZE_MASK               0x0000000FL
0130 #define RSCONFIG_MODULO_16                      0x00000001L
0131 #define RSCONFIG_MODULO_32                      0x00000002L
0132 #define RSCONFIG_MODULO_64                      0x00000003L
0133 #define RSCONFIG_MODULO_128                     0x00000004L
0134 #define RSCONFIG_MODULO_256                     0x00000005L
0135 #define RSCONFIG_MODULO_512                     0x00000006L
0136 #define RSCONFIG_MODULO_1024                    0x00000007L
0137 #define RSCONFIG_MODULO_4                       0x00000008L
0138 #define RSCONFIG_MODULO_8                       0x00000009L
0139 #define RSCONFIG_SAMPLE_SIZE_MASK               0x000000C0L
0140 #define RSCONFIG_SAMPLE_8MONO                   0x00000000L
0141 #define RSCONFIG_SAMPLE_8STEREO                 0x00000040L
0142 #define RSCONFIG_SAMPLE_16MONO                  0x00000080L
0143 #define RSCONFIG_SAMPLE_16STEREO                0x000000C0L
0144 #define RSCONFIG_UNDERRUN_ZERO                  0x00004000L
0145 #define RSCONFIG_DMA_TO_HOST                    0x00008000L
0146 #define RSCONFIG_STREAM_NUM_MASK                0x00FF0000L
0147 #define RSCONFIG_MAX_DMA_SIZE_MASK              0x1F000000L
0148 #define RSCONFIG_DMA_ENABLE                     0x20000000L
0149 #define RSCONFIG_PRIORITY_MASK                  0xC0000000L
0150 #define RSCONFIG_PRIORITY_HIGH                  0x00000000L
0151 #define RSCONFIG_PRIORITY_MEDIUM_HIGH           0x40000000L
0152 #define RSCONFIG_PRIORITY_MEDIUM_LOW            0x80000000L
0153 #define RSCONFIG_PRIORITY_LOW                   0xC0000000L
0154 #define RSCONFIG_STREAM_NUM_SHIFT               16L
0155 #define RSCONFIG_MAX_DMA_SIZE_SHIFT             24L
0156
0157 /* SP constants */
0158 #define FG_INTERVAL_TIMER_PERIOD                0x0051
0159 #define BG_INTERVAL_TIMER_PERIOD                0x0100
0160
0161
0162 /* Only SP accessible registers */
0163 #define SP_ASER_COUNTDOWN 0x8040
0164 #define SP_SPDOUT_FIFO    0x0108
0165 #define SP_SPDIN_MI_FIFO  0x01E0
0166 #define SP_SPDIN_D_FIFO   0x01F0
0167 #define SP_SPDIN_STATUS   0x8048
0168 #define SP_SPDIN_CONTROL  0x8049
0169 #define SP_SPDIN_FIFOPTR  0x804A
0170 #define SP_SPDOUT_STATUS  0x804C
0171 #define SP_SPDOUT_CONTROL 0x804D
0172 #define SP_SPDOUT_CSUV    0x808E
0173
0174 static inline u8 _wrap_all_bits (u8 val)
0175 {
0176     u8 wrapped;
0177
0178     /* wrap all 8 bits */
0179     wrapped =
0180         ((val & 0x1 ) << 7) |
0181         ((val & 0x2 ) << 5) |
0182         ((val & 0x4 ) << 3) |
0183         ((val & 0x8 ) << 1) |
0184         ((val & 0x10) >> 1) |
0185         ((val & 0x20) >> 3) |
0186         ((val & 0x40) >> 5) |
0187         ((val & 0x80) >> 7);
0188
0189     return wrapped;
0190 }
0191
0192 static inline void cs46xx_dsp_spos_update_scb (struct snd_cs46xx * chip,
0193                            struct dsp_scb_descriptor * scb)
0194 {
0195     /* update nextSCB and subListPtr in SCB */
0196     snd_cs46xx_poke(chip,
0197             (scb->address + SCBsubListPtr) << 2,
0198             (scb->sub_list_ptr->address << 0x10) |
0199             (scb->next_scb_ptr->address));
0200     scb->updated = 1;
0201 }
0202
0203 static inline void cs46xx_dsp_scb_set_volume (struct snd_cs46xx * chip,
0204                           struct dsp_scb_descriptor * scb,
0205                           u16 left, u16 right)
0206 {
0207     unsigned int val = ((0xffff - left) << 16 | (0xffff - right));
0208
0209     snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl) << 2, val);
0210     snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl + 1) << 2, val);
0211     scb->volume_set = 1;
0212     scb->volume[0] = left;
0213     scb->volume[1] = right;
0214 }
0215 #endif /* __DSP_SPOS_H__ */
0216 #endif /* CONFIG_SND_CS46XX_NEW_DSP  */