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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk> 0004 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit 0005 * Version: 0.0.22 0006 * 0007 * FEATURES currently supported: 0008 * See ca0106_main.c for features. 0009 * 0010 * Changelog: 0011 * Support interrupts per period. 0012 * Removed noise from Center/LFE channel when in Analog mode. 0013 * Rename and remove mixer controls. 0014 * 0.0.6 0015 * Use separate card based DMA buffer for periods table list. 0016 * 0.0.7 0017 * Change remove and rename ctrls into lists. 0018 * 0.0.8 0019 * Try to fix capture sources. 0020 * 0.0.9 0021 * Fix AC3 output. 0022 * Enable S32_LE format support. 0023 * 0.0.10 0024 * Enable playback 48000 and 96000 rates. (Rates other that these do not work, even with "plug:front".) 0025 * 0.0.11 0026 * Add Model name recognition. 0027 * 0.0.12 0028 * Correct interrupt timing. interrupt at end of period, instead of in the middle of a playback period. 0029 * Remove redundent "voice" handling. 0030 * 0.0.13 0031 * Single trigger call for multi channels. 0032 * 0.0.14 0033 * Set limits based on what the sound card hardware can do. 0034 * playback periods_min=2, periods_max=8 0035 * capture hw constraints require period_size = n * 64 bytes. 0036 * playback hw constraints require period_size = n * 64 bytes. 0037 * 0.0.15 0038 * Separated ca0106.c into separate functional .c files. 0039 * 0.0.16 0040 * Implement 192000 sample rate. 0041 * 0.0.17 0042 * Add support for SB0410 and SB0413. 0043 * 0.0.18 0044 * Modified Copyright message. 0045 * 0.0.19 0046 * Added I2C and SPI registers. Filled in interrupt enable. 0047 * 0.0.20 0048 * Added GPIO info for SB Live 24bit. 0049 * 0.0.21 0050 * Implement support for Line-in capture on SB Live 24bit. 0051 * 0.0.22 0052 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC) 0053 * 0054 * This code was initially based on code from ALSA's emu10k1x.c which is: 0055 * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com> 0056 */ 0057 0058 /************************************************************************************************/ 0059 /* PCI function 0 registers, address = <val> + PCIBASE0 */ 0060 /************************************************************************************************/ 0061 0062 #define CA0106_PTR 0x00 /* Indexed register set pointer register */ 0063 /* NOTE: The CHANNELNUM and ADDRESS words can */ 0064 /* be modified independently of each other. */ 0065 /* CNL[1:0], ADDR[27:16] */ 0066 0067 #define CA0106_DATA 0x04 /* Indexed register set data register */ 0068 /* DATA[31:0] */ 0069 0070 #define CA0106_IPR 0x08 /* Global interrupt pending register */ 0071 /* Clear pending interrupts by writing a 1 to */ 0072 /* the relevant bits and zero to the other bits */ 0073 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */ 0074 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */ 0075 #define IPR_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */ 0076 #define IPR_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */ 0077 #define IPR_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */ 0078 #define IPR_SPI 0x00000800 /* SPI transaction completed */ 0079 #define IPR_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */ 0080 #define IPR_I2C_DAC 0x00000200 /* I2C DAC transaction completed */ 0081 #define IPR_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x76 */ 0082 #define IPR_GPI 0x00000080 /* General Purpose input changed */ 0083 #define IPR_SRC_LOCKED 0x00000040 /* SRC lock status changed */ 0084 #define IPR_SPDIF_STATUS 0x00000020 /* SPDIF status changed */ 0085 #define IPR_TIMER2 0x00000010 /* 192000Hz Timer */ 0086 #define IPR_TIMER1 0x00000008 /* 44100Hz Timer */ 0087 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */ 0088 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */ 0089 #define IPR_PCI 0x00000001 /* PCI Bus error */ 0090 0091 #define CA0106_INTE 0x0c /* Interrupt enable register */ 0092 0093 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */ 0094 #define INTE_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */ 0095 #define INTE_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */ 0096 #define INTE_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */ 0097 #define INTE_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */ 0098 #define INTE_SPI 0x00000800 /* SPI transaction completed */ 0099 #define INTE_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */ 0100 #define INTE_I2C_DAC 0x00000200 /* I2C DAC transaction completed */ 0101 #define INTE_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x75 */ 0102 #define INTE_GPI 0x00000080 /* General Purpose input changed */ 0103 #define INTE_SRC_LOCKED 0x00000040 /* SRC lock status changed */ 0104 #define INTE_SPDIF_STATUS 0x00000020 /* SPDIF status changed */ 0105 #define INTE_TIMER2 0x00000010 /* 192000Hz Timer */ 0106 #define INTE_TIMER1 0x00000008 /* 44100Hz Timer */ 0107 #define INTE_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */ 0108 #define INTE_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */ 0109 #define INTE_PCI 0x00000001 /* PCI Bus error */ 0110 0111 #define CA0106_UNKNOWN10 0x10 /* Unknown ??. Defaults to 0 */ 0112 #define CA0106_HCFG 0x14 /* Hardware config register */ 0113 /* 0x1000 causes AC3 to fails. It adds a dither bit. */ 0114 0115 #define HCFG_STAC 0x10000000 /* Special mode for STAC9460 Codec. */ 0116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */ 0117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */ 0118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */ 0119 #define HCFG_FORCE_LOCK 0x01000000 /* For test only. Force input SRC tracker to lock. */ 0120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12dB, 3 = Mute. */ 0121 #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */ 0122 #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */ 0123 #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */ 0124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/ 0125 #define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/ 0126 #define HCFG_MONO 0x00000080 /* 1 = I2S Input mono */ 0127 #define HCFG_I2S_OUTPUT 0x00000010 /* 1 = I2S Output disabled */ 0128 #define HCFG_AC97 0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */ 0129 #define HCFG_LOCK_PLAYBACK_CACHE 0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */ 0130 /* NOTE: This should generally never be used. */ 0131 #define HCFG_LOCK_CAPTURE_CACHE 0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */ 0132 /* NOTE: This should generally never be used. */ 0133 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ 0134 /* Should be set to 1 when the EMU10K1 is */ 0135 /* completely initialized. */ 0136 #define CA0106_GPIO 0x18 /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF. */ 0137 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */ 0138 /* For the Audigy LS, pin 0 (or bit 8) controls the SPDIF/Analog jack. */ 0139 /* SB Live 24bit: 0140 * bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in. 0141 * bit 9 0 = Mute / 1 = Analog out. 0142 * bit 10 0 = Line-in / 1 = Mic-in. 0143 * bit 11 0 = ? / 1 = ? 0144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit. 0145 * bit 13 0 = ? / 1 = ? 0146 * bit 14 0 = Mute / 1 = Analog out 0147 * bit 15 0 = ? / 1 = ? 0148 * Both bit 9 and bit 14 have to be set for analog sound to work on the SB Live 24bit. 0149 */ 0150 /* 8 general purpose programmable In/Out pins. 0151 * GPI [8:0] Read only. Default 0. 0152 * GPO [15:8] Default 0x9. (Default to SPDIF jack enabled for SPDIF) 0153 * GPO Enable [23:16] Default 0x0f. Setting a bit to 1, causes the pin to be an output pin. 0154 */ 0155 #define CA0106_AC97DATA 0x1c /* AC97 register set data register (16 bit) */ 0156 0157 #define CA0106_AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ 0158 0159 /********************************************************************************************************/ 0160 /* CA0106 pointer-offset register set, accessed through the PTR and DATA registers */ 0161 /********************************************************************************************************/ 0162 0163 /* Initially all registers from 0x00 to 0x3f have zero contents. */ 0164 #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */ 0165 /* One list entry: 4 bytes for DMA address, 0166 * 4 bytes for period_size << 16. 0167 * One list entry is 8 bytes long. 0168 * One list entry for each period in the buffer. 0169 */ 0170 /* ADDR[31:0], Default: 0x0 */ 0171 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */ 0172 /* SIZE[21:16], Default: 0x8 */ 0173 #define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */ 0174 /* PTR[5:0], Default: 0x0 */ 0175 #define PLAYBACK_UNKNOWN3 0x03 /* Not used ?? */ 0176 #define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */ 0177 /* DMA[31:0], Default: 0x0 */ 0178 #define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */ 0179 /* SIZE[31:16], Default: 0x0 */ 0180 #define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */ 0181 /* POINTER[15:0], Default: 0x0 */ 0182 #define PLAYBACK_PERIOD_END_ADDR 0x07 /* Playback fifo end address */ 0183 /* END_ADDR[15:0], FLAG[16] 0 = don't stop, 1 = stop */ 0184 #define PLAYBACK_FIFO_OFFSET_ADDRESS 0x08 /* Current fifo offset address [21:16] */ 0185 /* Cache size valid [5:0] */ 0186 #define PLAYBACK_UNKNOWN9 0x09 /* 0x9 to 0xf Unused */ 0187 #define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */ 0188 /* DMA[31:0], Default: 0x0 */ 0189 #define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */ 0190 /* SIZE[31:16], Default: 0x0 */ 0191 #define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */ 0192 /* POINTER[15:0], Default: 0x0 */ 0193 #define CAPTURE_FIFO_OFFSET_ADDRESS 0x13 /* Current fifo offset address [21:16] */ 0194 /* Cache size valid [5:0] */ 0195 #define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played */ 0196 /* 0x21 - 0x3f unused */ 0197 #define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */ 0198 /* Playback (0x1<<channel_id) */ 0199 /* Capture (0x100<<channel_id) */ 0200 /* Playback sample rate 96000 = 0x20000 */ 0201 /* Start Playback [3:0] (one bit per channel) 0202 * Start Capture [11:8] (one bit per channel) 0203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 0204 * Playback mixer in enable [27:24] (one bit per channel) 0205 * Playback mixer out enable [31:28] (one bit per channel) 0206 */ 0207 /* The Digital out jack is shared with the Center/LFE Analogue output. 0208 * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3 0209 * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground 0210 * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground. 0211 * Standard 4 pole Video A/V cable with RCA outputs: 1 -> White, 2 -> Yellow, 3 -> Shield on all three, 4 -> Red. 0212 * So, from this you can see that you cannot use a Standard 4 pole Video A/V cable with the SB Audigy LS card. 0213 */ 0214 /* The Front SPDIF PCM gets mixed with samples from the AC97 codec, so can only work for Stereo PCM and not AC3/DTS 0215 * The Rear SPDIF can be used for Stereo PCM and also AC3/DTS 0216 * The Center/LFE SPDIF cannot be used for AC3/DTS, but can be used for Stereo PCM. 0217 * Summary: For ALSA we use the Rear channel for SPDIF Digital AC3/DTS output 0218 */ 0219 /* A standard 2 pole mono mini-jack to RCA plug can be used for SPDIF Stereo PCM output from the Front channel. 0220 * A standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM output utilising the Rear channel and just one of the RCA plugs. 0221 */ 0222 #define SPCS0 0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006 */ 0223 #define SPCS1 0x42 /* SPDIF output Channel Status 1 register. For Front */ 0224 #define SPCS2 0x43 /* SPDIF output Channel Status 2 register. For Center/LFE */ 0225 #define SPCS3 0x44 /* SPDIF output Channel Status 3 register. Unknown */ 0226 /* When Channel set to 0: */ 0227 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ 0228 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ 0229 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ 0230 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ 0231 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ 0232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ 0233 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ 0234 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ 0235 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ 0236 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ 0237 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ 0238 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ 0239 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ 0240 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ 0241 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ 0242 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ 0243 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ 0244 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ 0245 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ 0246 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ 0247 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ 0248 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ 0249 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ 0250 0251 /* When Channel set to 1: */ 0252 #define SPCS_WORD_LENGTH_MASK 0x0000000f /* Word Length Mask */ 0253 #define SPCS_WORD_LENGTH_16 0x00000008 /* Word Length 16 bit */ 0254 #define SPCS_WORD_LENGTH_17 0x00000006 /* Word Length 17 bit */ 0255 #define SPCS_WORD_LENGTH_18 0x00000004 /* Word Length 18 bit */ 0256 #define SPCS_WORD_LENGTH_19 0x00000002 /* Word Length 19 bit */ 0257 #define SPCS_WORD_LENGTH_20A 0x0000000a /* Word Length 20 bit */ 0258 #define SPCS_WORD_LENGTH_20 0x00000009 /* Word Length 20 bit (both 0xa and 0x9 are 20 bit) */ 0259 #define SPCS_WORD_LENGTH_21 0x00000007 /* Word Length 21 bit */ 0260 #define SPCS_WORD_LENGTH_22 0x00000005 /* Word Length 22 bit */ 0261 #define SPCS_WORD_LENGTH_23 0x00000003 /* Word Length 23 bit */ 0262 #define SPCS_WORD_LENGTH_24 0x0000000b /* Word Length 24 bit */ 0263 #define SPCS_ORIGINAL_SAMPLE_RATE_MASK 0x000000f0 /* Original Sample rate */ 0264 #define SPCS_ORIGINAL_SAMPLE_RATE_NONE 0x00000000 /* Original Sample rate not indicated */ 0265 #define SPCS_ORIGINAL_SAMPLE_RATE_16000 0x00000010 /* Original Sample rate */ 0266 #define SPCS_ORIGINAL_SAMPLE_RATE_RES1 0x00000020 /* Original Sample rate */ 0267 #define SPCS_ORIGINAL_SAMPLE_RATE_32000 0x00000030 /* Original Sample rate */ 0268 #define SPCS_ORIGINAL_SAMPLE_RATE_12000 0x00000040 /* Original Sample rate */ 0269 #define SPCS_ORIGINAL_SAMPLE_RATE_11025 0x00000050 /* Original Sample rate */ 0270 #define SPCS_ORIGINAL_SAMPLE_RATE_8000 0x00000060 /* Original Sample rate */ 0271 #define SPCS_ORIGINAL_SAMPLE_RATE_RES2 0x00000070 /* Original Sample rate */ 0272 #define SPCS_ORIGINAL_SAMPLE_RATE_192000 0x00000080 /* Original Sample rate */ 0273 #define SPCS_ORIGINAL_SAMPLE_RATE_24000 0x00000090 /* Original Sample rate */ 0274 #define SPCS_ORIGINAL_SAMPLE_RATE_96000 0x000000a0 /* Original Sample rate */ 0275 #define SPCS_ORIGINAL_SAMPLE_RATE_48000 0x000000b0 /* Original Sample rate */ 0276 #define SPCS_ORIGINAL_SAMPLE_RATE_176400 0x000000c0 /* Original Sample rate */ 0277 #define SPCS_ORIGINAL_SAMPLE_RATE_22050 0x000000d0 /* Original Sample rate */ 0278 #define SPCS_ORIGINAL_SAMPLE_RATE_88200 0x000000e0 /* Original Sample rate */ 0279 #define SPCS_ORIGINAL_SAMPLE_RATE_44100 0x000000f0 /* Original Sample rate */ 0280 0281 #define SPDIF_SELECT1 0x45 /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */ 0282 /* 0x100 - Front, 0x800 - Rear, 0x200 - Center/LFE. 0283 * But as the jack is shared, use 0xf00. 0284 * The Windows2000 driver uses 0x0000000f for both digital and analog. 0285 * 0xf00 introduces interesting noises onto the Center/LFE. 0286 * If you turn the volume up, you hear computer noise, 0287 * e.g. mouse moving, changing between app windows etc. 0288 * So, I am going to set this to 0x0000000f all the time now, 0289 * same as the windows driver does. 0290 * Use register SPDIF_SELECT2(0x72) to switch between SPDIF and Analog. 0291 */ 0292 /* When Channel = 0: 0293 * Wide SPDIF format [3:0] (one bit for each channel) (0=20bit, 1=24bit) 0294 * Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate) 0295 * SPDIF Bypass enable [19:16] (one bit for each channel) (0=Not bypass, 1=Bypass) 0296 */ 0297 /* When Channel = 1: 0298 * SPDIF 0 User data [7:0] 0299 * SPDIF 1 User data [15:8] 0300 * SPDIF 0 User data [23:16] 0301 * SPDIF 0 User data [31:24] 0302 * User data can be sent by using the SPDIF output frame pending and SPDIF output user bit interrupts. 0303 */ 0304 #define WATERMARK 0x46 /* Test bit to indicate cache usage level */ 0305 #define SPDIF_INPUT_STATUS 0x49 /* SPDIF Input status register. Bits the same as SPCS. 0306 * When Channel = 0: Bits the same as SPCS channel 0. 0307 * When Channel = 1: Bits the same as SPCS channel 1. 0308 * When Channel = 2: 0309 * SPDIF Input User data [16:0] 0310 * SPDIF Input Frame count [21:16] 0311 */ 0312 #define CAPTURE_CACHE_DATA 0x50 /* 0x50-0x5f Recorded samples. */ 0313 #define CAPTURE_SOURCE 0x60 /* Capture Source 0 = MIC */ 0314 #define CAPTURE_SOURCE_CHANNEL0 0xf0000000 /* Mask for selecting the Capture sources */ 0315 #define CAPTURE_SOURCE_CHANNEL1 0x0f000000 /* 0 - SPDIF mixer output. */ 0316 #define CAPTURE_SOURCE_CHANNEL2 0x00f00000 /* 1 - What you hear or . 2 - ?? */ 0317 #define CAPTURE_SOURCE_CHANNEL3 0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */ 0318 #define CAPTURE_SOURCE_RECORD_MAP 0x0000ffff /* Default 0x00e4 */ 0319 /* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to channel2, 3=mapped to channel3 0320 * Record source select for channel 0 [18:16] 0321 * Record source select for channel 1 [22:20] 0322 * Record source select for channel 2 [26:24] 0323 * Record source select for channel 3 [30:28] 0324 * 0 - SPDIF mixer output. 0325 * 1 - i2s mixer output. 0326 * 2 - SPDIF input. 0327 * 3 - i2s input. 0328 * 4 - AC97 capture. 0329 * 5 - SRC output. 0330 */ 0331 #define CAPTURE_VOLUME1 0x61 /* Capture volume per channel 0-3 */ 0332 #define CAPTURE_VOLUME2 0x62 /* Capture volume per channel 4-7 */ 0333 0334 #define PLAYBACK_ROUTING1 0x63 /* Playback routing of channels 0-7. Effects AC3 output. Default 0x32765410 */ 0335 #define ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */ 0336 #define ROUTING1_NULL 0x00770000 /* Channel_id 2 sends to 54, Channel_id 3 sends to 76 */ 0337 #define ROUTING1_CENTER_LFE 0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */ 0338 #define ROUTING1_FRONT 0x00000077 /* Channel_id 2 to CENTER_LFE, Channel_id 3 to NULL. */ 0339 /* Channel_id's handle stereo channels. Channel X is a single mono channel */ 0340 /* Host is input from the PCI bus. */ 0341 /* Host channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7. 0342 * Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7. 0343 * Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7. 0344 * Host channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7. 0345 * Host channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7. 0346 * Host channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7. 0347 * Host channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7. 0348 * Host channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7. 0349 */ 0350 0351 #define PLAYBACK_ROUTING2 0x64 /* Playback Routing . Feeding Capture channels back into Playback. Effects AC3 output. Default 0x76767676 */ 0352 /* SRC is input from the capture inputs. */ 0353 /* SRC channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7. 0354 * SRC channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7. 0355 * SRC channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7. 0356 * SRC channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7. 0357 * SRC channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7. 0358 * SRC channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7. 0359 * SRC channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7. 0360 * SRC channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7. 0361 */ 0362 0363 #define PLAYBACK_MUTE 0x65 /* Unknown. While playing 0x0, while silent 0x00fc0000 */ 0364 /* SPDIF Mixer input control: 0365 * Invert SRC to SPDIF Mixer [7-0] (One bit per channel) 0366 * Invert Host to SPDIF Mixer [15:8] (One bit per channel) 0367 * SRC to SPDIF Mixer disable [23:16] (One bit per channel) 0368 * Host to SPDIF Mixer disable [31:24] (One bit per channel) 0369 */ 0370 #define PLAYBACK_VOLUME1 0x66 /* Playback SPDIF volume per channel. Set to the same PLAYBACK_VOLUME(0x6a) */ 0371 /* PLAYBACK_VOLUME1 must be set to 30303030 for SPDIF AC3 Playback */ 0372 /* SPDIF mixer input volume. 0=12dB, 0x30=0dB, 0xFE=-51.5dB, 0xff=Mute */ 0373 /* One register for each of the 4 stereo streams. */ 0374 /* SRC Right volume [7:0] 0375 * SRC Left volume [15:8] 0376 * Host Right volume [23:16] 0377 * Host Left volume [31:24] 0378 */ 0379 #define CAPTURE_ROUTING1 0x67 /* Capture Routing. Default 0x32765410 */ 0380 /* Similar to register 0x63, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 0381 #define CAPTURE_ROUTING2 0x68 /* Unknown Routing. Default 0x76767676 */ 0382 /* Similar to register 0x64, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 0383 #define CAPTURE_MUTE 0x69 /* Unknown. While capturing 0x0, while silent 0x00fc0000 */ 0384 /* Similar to register 0x65, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 0385 #define PLAYBACK_VOLUME2 0x6a /* Playback Analog volume per channel. Does not effect AC3 output */ 0386 /* Similar to register 0x66, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */ 0387 #define UNKNOWN6b 0x6b /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */ 0388 #define MIDI_UART_A_DATA 0x6c /* Midi Uart A Data */ 0389 #define MIDI_UART_A_CMD 0x6d /* Midi Uart A Command/Status */ 0390 #define MIDI_UART_B_DATA 0x6e /* Midi Uart B Data (currently unused) */ 0391 #define MIDI_UART_B_CMD 0x6f /* Midi Uart B Command/Status (currently unused) */ 0392 0393 /* unique channel identifier for midi->channel */ 0394 0395 #define CA0106_MIDI_CHAN_A 0x1 0396 #define CA0106_MIDI_CHAN_B 0x2 0397 0398 /* from mpu401 */ 0399 0400 #define CA0106_MIDI_INPUT_AVAIL 0x80 0401 #define CA0106_MIDI_OUTPUT_READY 0x40 0402 #define CA0106_MPU401_RESET 0xff 0403 #define CA0106_MPU401_ENTER_UART 0x3f 0404 #define CA0106_MPU401_ACK 0xfe 0405 0406 #define SAMPLE_RATE_TRACKER_STATUS 0x70 /* Readonly. Default 00108000 00108000 00500000 00500000 */ 0407 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0 0408 * Rate Locked [20] 0409 * SPDIF Locked [21] For SPDIF channel only. 0410 * Valid Audio [22] For SPDIF channel only. 0411 */ 0412 #define CAPTURE_CONTROL 0x71 /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */ 0413 /* Channel_id 0: 0x40c81000 must be changed to 0x40c80000 for SPDIF AC3 input or output. */ 0414 /* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */ 0415 /* Sample rate output control register Channel=0 0416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 0417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz) 0418 * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source. 0419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz) 0420 * Record mixer output enable [12:10] 0421 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 0422 * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 0423 * I2S output source select [18] (0=Audio from host, 1=Audio from SRC) 0424 * Record mixer I2S enable [20:19] (enable/disable i2sin1 and i2sin0) 0425 * I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.) 0426 * I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.) 0427 * I2S input mode [23] (0=Slave, 1=Master) 0428 * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz) 0429 * SPDIF output source select [26] (0=host, 1=SRC) 0430 * Not used [27] 0431 * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM) 0432 * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM) 0433 */ 0434 /* Sample rate output control register Channel=1 0435 * I2S Input 0 volume Right [7:0] 0436 * I2S Input 0 volume Left [15:8] 0437 * I2S Input 1 volume Right [23:16] 0438 * I2S Input 1 volume Left [31:24] 0439 */ 0440 /* Sample rate output control register Channel=2 0441 * SPDIF Input volume Right [23:16] 0442 * SPDIF Input volume Left [31:24] 0443 */ 0444 /* Sample rate output control register Channel=3 0445 * No used 0446 */ 0447 #define SPDIF_SELECT2 0x72 /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */ 0448 #define ROUTING2_FRONT_MASK 0x00010000 /* Enable for Front speakers. */ 0449 #define ROUTING2_CENTER_LFE_MASK 0x00020000 /* Enable for Center/LFE speakers. */ 0450 #define ROUTING2_REAR_MASK 0x00080000 /* Enable for Rear speakers. */ 0451 /* Audio output control 0452 * AC97 output enable [5:0] 0453 * I2S output enable [19:16] 0454 * SPDIF output enable [27:24] 0455 */ 0456 #define UNKNOWN73 0x73 /* Unknown. Readonly. Default 0x0 */ 0457 #define CHIP_VERSION 0x74 /* P17 Chip version. Channel_id 0 only. Default 00000071 */ 0458 #define EXTENDED_INT_MASK 0x75 /* Used by both playback and capture interrupt handler */ 0459 /* Sets which Interrupts are enabled. */ 0460 /* 0x00000001 = Half period. Playback. 0461 * 0x00000010 = Full period. Playback. 0462 * 0x00000100 = Half buffer. Playback. 0463 * 0x00001000 = Full buffer. Playback. 0464 * 0x00010000 = Half buffer. Capture. 0465 * 0x00100000 = Full buffer. Capture. 0466 * Capture can only do 2 periods. 0467 * 0x01000000 = End audio. Playback. 0468 * 0x40000000 = Half buffer Playback,Caputre xrun. 0469 * 0x80000000 = Full buffer Playback,Caputre xrun. 0470 */ 0471 #define EXTENDED_INT 0x76 /* Used by both playback and capture interrupt handler */ 0472 /* Shows which interrupts are active at the moment. */ 0473 /* Same bit layout as EXTENDED_INT_MASK */ 0474 #define COUNTER77 0x77 /* Counter range 0 to 0x3fffff, 192000 counts per second. */ 0475 #define COUNTER78 0x78 /* Counter range 0 to 0x3fffff, 44100 counts per second. */ 0476 #define EXTENDED_INT_TIMER 0x79 /* Channel_id 0 only. Used by both playback and capture interrupt handler */ 0477 /* Causes interrupts based on timer intervals. */ 0478 #define SPI 0x7a /* SPI: Serial Interface Register */ 0479 #define I2C_A 0x7b /* I2C Address. 32 bit */ 0480 #define I2C_D0 0x7c /* I2C Data Port 0. 32 bit */ 0481 #define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */ 0482 //I2C values 0483 #define I2C_A_ADC_ADD_MASK 0x000000fe //The address is a 7 bit address 0484 #define I2C_A_ADC_RW_MASK 0x00000001 //bit mask for R/W 0485 #define I2C_A_ADC_TRANS_MASK 0x00000010 //Bit mask for I2c address DAC value 0486 #define I2C_A_ADC_ABORT_MASK 0x00000020 //Bit mask for I2C transaction abort flag 0487 #define I2C_A_ADC_LAST_MASK 0x00000040 //Bit mask for Last word transaction 0488 #define I2C_A_ADC_BYTE_MASK 0x00000080 //Bit mask for Byte Mode 0489 0490 #define I2C_A_ADC_ADD 0x00000034 //This is the Device address for ADC 0491 #define I2C_A_ADC_READ 0x00000001 //To perform a read operation 0492 #define I2C_A_ADC_START 0x00000100 //Start I2C transaction 0493 #define I2C_A_ADC_ABORT 0x00000200 //I2C transaction abort 0494 #define I2C_A_ADC_LAST 0x00000400 //I2C last transaction 0495 #define I2C_A_ADC_BYTE 0x00000800 //I2C one byte mode 0496 0497 #define I2C_D_ADC_REG_MASK 0xfe000000 //ADC address register 0498 #define I2C_D_ADC_DAT_MASK 0x01ff0000 //ADC data register 0499 0500 #define ADC_TIMEOUT 0x00000007 //ADC Timeout Clock Disable 0501 #define ADC_IFC_CTRL 0x0000000b //ADC Interface Control 0502 #define ADC_MASTER 0x0000000c //ADC Master Mode Control 0503 #define ADC_POWER 0x0000000d //ADC PowerDown Control 0504 #define ADC_ATTEN_ADCL 0x0000000e //ADC Attenuation ADCL 0505 #define ADC_ATTEN_ADCR 0x0000000f //ADC Attenuation ADCR 0506 #define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1 0507 #define ADC_ALC_CTRL2 0x00000011 //ADC ALC Control 2 0508 #define ADC_ALC_CTRL3 0x00000012 //ADC ALC Control 3 0509 #define ADC_NOISE_CTRL 0x00000013 //ADC Noise Gate Control 0510 #define ADC_LIMIT_CTRL 0x00000014 //ADC Limiter Control 0511 #define ADC_MUX 0x00000015 //ADC Mux offset 0512 0513 #if 0 0514 /* FIXME: Not tested yet. */ 0515 #define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain 0516 #define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB 0517 #define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute 0518 #define ADC_MUTE 0x000000c0 //Value to mute ADC 0519 #define ADC_OSR 0x00000008 //Mask for ADC oversample rate select 0520 #define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock 0521 #define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter 0522 #define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window 0523 #endif 0524 0525 #define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux 0526 #define ADC_MUX_PHONE 0x00000001 //Value to select TAD at ADC Mux (Not used) 0527 #define ADC_MUX_MIC 0x00000002 //Value to select Mic at ADC Mux 0528 #define ADC_MUX_LINEIN 0x00000004 //Value to select LineIn at ADC Mux 0529 #define ADC_MUX_AUX 0x00000008 //Value to select Aux at ADC Mux 0530 0531 #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */ 0532 #define PCM_FRONT_CHANNEL 0 0533 #define PCM_REAR_CHANNEL 1 0534 #define PCM_CENTER_LFE_CHANNEL 2 0535 #define PCM_UNKNOWN_CHANNEL 3 0536 #define CONTROL_FRONT_CHANNEL 0 0537 #define CONTROL_REAR_CHANNEL 3 0538 #define CONTROL_CENTER_LFE_CHANNEL 1 0539 #define CONTROL_UNKNOWN_CHANNEL 2 0540 0541 0542 /* Based on WM8768 Datasheet Rev 4.2 page 32 */ 0543 #define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */ 0544 #define SPI_REG_SHIFT 9 /* followed by 9 bits of data */ 0545 0546 #define SPI_LDA1_REG 0 /* digital attenuation */ 0547 #define SPI_RDA1_REG 1 0548 #define SPI_LDA2_REG 4 0549 #define SPI_RDA2_REG 5 0550 #define SPI_LDA3_REG 6 0551 #define SPI_RDA3_REG 7 0552 #define SPI_LDA4_REG 13 0553 #define SPI_RDA4_REG 14 0554 #define SPI_MASTDA_REG 8 0555 0556 #define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */ 0557 #define SPI_DA_BIT_0dB 0xff /* 0 dB */ 0558 #define SPI_DA_BIT_infdB 0x00 /* inf dB attenuation (mute) */ 0559 0560 #define SPI_PL_REG 2 0561 #define SPI_PL_BIT_L_M (0<<5) /* left channel = mute */ 0562 #define SPI_PL_BIT_L_L (1<<5) /* left channel = left */ 0563 #define SPI_PL_BIT_L_R (2<<5) /* left channel = right */ 0564 #define SPI_PL_BIT_L_C (3<<5) /* left channel = (L+R)/2 */ 0565 #define SPI_PL_BIT_R_M (0<<7) /* right channel = mute */ 0566 #define SPI_PL_BIT_R_L (1<<7) /* right channel = left */ 0567 #define SPI_PL_BIT_R_R (2<<7) /* right channel = right */ 0568 #define SPI_PL_BIT_R_C (3<<7) /* right channel = (L+R)/2 */ 0569 #define SPI_IZD_REG 2 0570 #define SPI_IZD_BIT (0<<4) /* infinite zero detect */ 0571 0572 #define SPI_FMT_REG 3 0573 #define SPI_FMT_BIT_RJ (0<<0) /* right justified mode */ 0574 #define SPI_FMT_BIT_LJ (1<<0) /* left justified mode */ 0575 #define SPI_FMT_BIT_I2S (2<<0) /* I2S mode */ 0576 #define SPI_FMT_BIT_DSP (3<<0) /* DSP Modes A or B */ 0577 #define SPI_LRP_REG 3 0578 #define SPI_LRP_BIT (1<<2) /* invert LRCLK polarity */ 0579 #define SPI_BCP_REG 3 0580 #define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */ 0581 #define SPI_IWL_REG 3 0582 #define SPI_IWL_BIT_16 (0<<4) /* 16-bit world length */ 0583 #define SPI_IWL_BIT_20 (1<<4) /* 20-bit world length */ 0584 #define SPI_IWL_BIT_24 (2<<4) /* 24-bit world length */ 0585 #define SPI_IWL_BIT_32 (3<<4) /* 32-bit world length */ 0586 0587 #define SPI_MS_REG 10 0588 #define SPI_MS_BIT (1<<5) /* master mode */ 0589 #define SPI_RATE_REG 10 /* only applies in master mode */ 0590 #define SPI_RATE_BIT_128 (0<<6) /* MCLK = LRCLK * 128 */ 0591 #define SPI_RATE_BIT_192 (1<<6) 0592 #define SPI_RATE_BIT_256 (2<<6) 0593 #define SPI_RATE_BIT_384 (3<<6) 0594 #define SPI_RATE_BIT_512 (4<<6) 0595 #define SPI_RATE_BIT_768 (5<<6) 0596 0597 /* They really do label the bit for the 4th channel "4" and not "3" */ 0598 #define SPI_DMUTE0_REG 9 0599 #define SPI_DMUTE1_REG 9 0600 #define SPI_DMUTE2_REG 9 0601 #define SPI_DMUTE4_REG 15 0602 #define SPI_DMUTE0_BIT (1<<3) 0603 #define SPI_DMUTE1_BIT (1<<4) 0604 #define SPI_DMUTE2_BIT (1<<5) 0605 #define SPI_DMUTE4_BIT (1<<2) 0606 0607 #define SPI_PHASE0_REG 3 0608 #define SPI_PHASE1_REG 3 0609 #define SPI_PHASE2_REG 3 0610 #define SPI_PHASE4_REG 15 0611 #define SPI_PHASE0_BIT (1<<6) 0612 #define SPI_PHASE1_BIT (1<<7) 0613 #define SPI_PHASE2_BIT (1<<8) 0614 #define SPI_PHASE4_BIT (1<<3) 0615 0616 #define SPI_PDWN_REG 2 /* power down all DACs */ 0617 #define SPI_PDWN_BIT (1<<2) 0618 #define SPI_DACD0_REG 10 /* power down individual DACs */ 0619 #define SPI_DACD1_REG 10 0620 #define SPI_DACD2_REG 10 0621 #define SPI_DACD4_REG 15 0622 #define SPI_DACD0_BIT (1<<1) 0623 #define SPI_DACD1_BIT (1<<2) 0624 #define SPI_DACD2_BIT (1<<3) 0625 #define SPI_DACD4_BIT (1<<0) /* datasheet error says it's 1 */ 0626 0627 #define SPI_PWRDNALL_REG 10 /* power down everything */ 0628 #define SPI_PWRDNALL_BIT (1<<4) 0629 0630 #include "ca_midi.h" 0631 0632 struct snd_ca0106; 0633 0634 struct snd_ca0106_channel { 0635 struct snd_ca0106 *emu; 0636 int number; 0637 int use; 0638 void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel); 0639 struct snd_ca0106_pcm *epcm; 0640 }; 0641 0642 struct snd_ca0106_pcm { 0643 struct snd_ca0106 *emu; 0644 struct snd_pcm_substream *substream; 0645 int channel_id; 0646 unsigned short running; 0647 }; 0648 0649 struct snd_ca0106_details { 0650 u32 serial; 0651 char * name; 0652 int ac97; /* ac97 = 0 -> Select MIC, Line in, TAD in, AUX in. 0653 ac97 = 1 -> Default to AC97 in. */ 0654 int gpio_type; /* gpio_type = 1 -> shared mic-in/line-in 0655 gpio_type = 2 -> shared side-out/line-in. */ 0656 int i2c_adc; /* with i2c_adc=1, the driver adds some capture volume 0657 controls, phone, mic, line-in and aux. */ 0658 u16 spi_dac; /* spi_dac = 0 -> no spi interface for DACs 0659 spi_dac = 0x<front><rear><center-lfe><side> 0660 -> specifies DAC id for each channel pair. */ 0661 }; 0662 0663 // definition of the chip-specific record 0664 struct snd_ca0106 { 0665 struct snd_card *card; 0666 const struct snd_ca0106_details *details; 0667 struct pci_dev *pci; 0668 0669 unsigned long port; 0670 int irq; 0671 0672 unsigned int serial; /* serial number */ 0673 unsigned short model; /* subsystem id */ 0674 0675 spinlock_t emu_lock; 0676 0677 struct snd_ac97 *ac97; 0678 struct snd_pcm *pcm[4]; 0679 0680 struct snd_ca0106_channel playback_channels[4]; 0681 struct snd_ca0106_channel capture_channels[4]; 0682 u32 spdif_bits[4]; /* s/pdif out default setup */ 0683 u32 spdif_str_bits[4]; /* s/pdif out per-stream setup */ 0684 int spdif_enable; 0685 int capture_source; 0686 int i2c_capture_source; 0687 u8 i2c_capture_volume[4][2]; 0688 int capture_mic_line_in; 0689 0690 struct snd_dma_buffer *buffer; 0691 0692 struct snd_ca_midi midi; 0693 struct snd_ca_midi midi2; 0694 0695 u16 spi_dac_reg[16]; 0696 0697 #ifdef CONFIG_PM_SLEEP 0698 #define NUM_SAVED_VOLUMES 9 0699 unsigned int saved_vol[NUM_SAVED_VOLUMES]; 0700 #endif 0701 }; 0702 0703 int snd_ca0106_mixer(struct snd_ca0106 *emu); 0704 int snd_ca0106_proc_init(struct snd_ca0106 * emu); 0705 0706 unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu, 0707 unsigned int reg, 0708 unsigned int chn); 0709 0710 void snd_ca0106_ptr_write(struct snd_ca0106 *emu, 0711 unsigned int reg, 0712 unsigned int chn, 0713 unsigned int data); 0714 0715 int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value); 0716 0717 int snd_ca0106_spi_write(struct snd_ca0106 * emu, 0718 unsigned int data); 0719 0720 #ifdef CONFIG_PM_SLEEP 0721 void snd_ca0106_mixer_suspend(struct snd_ca0106 *chip); 0722 void snd_ca0106_mixer_resume(struct snd_ca0106 *chip); 0723 #else 0724 #define snd_ca0106_mixer_suspend(chip) do { } while (0) 0725 #define snd_ca0106_mixer_resume(chip) do { } while (0) 0726 #endif
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